C16 Project - CPU Board

C16 Project - 65C816 Board

As told, the 65C816 board is the same board used in MB01 project with some modifications (one little change in the circuit, and new gal for decoder section). Below the new schematics that reflect these modifications, and the gal equations.

First of all a looking at schematic part 1: U6 (GAL22V10 code #0050) is the master clock, that divide by 4 (or 8) the 16MHz signal, and drive the system clock PHI2 and the "artificial" PHI0 clock. Basis on my experience writing cycles in somes not-65XX i/o devices can be very critical, especially for data hold time; for this reason i provided this PHI0 signal, advanced by 10ns or 20ns, respect the PHI2 clock. PHI0 can be used for sync. the write signal in all cases where the PHI2 syncing can fall into issues (example: dma chip 82C37, counter 82C54). Note that this delay PHI0/PHI2 is due to intrinsic delay of GAL device, that is very precise and stable. SW1-1 select this delay: if is off the delay is 10ns, if on the delay is 20ns. SW1-2 select the PHI2 clock rate: 4MHz if off, 2MHz if on. SW1-4 select a delay on enabling the data buffer U5: in fact this switch must be keep in off position. About SW1-3, the function is explained later. Note that the PHI2 clock output by U6 is routed to buffer U7: in my first design i was afraid that gal output not able to drive PHI2 input of cpu at the right CMOS level, so choosed this solution; but in fact the gal can directly drive the clock input of 65C816. U5 must be a CMOS-series, because data bus on 65C816 is CMOS-level (not TTL-compatible).
U6 generate the following signals too:

/VMA: a valid memory access, active low, that is the inverted or of cpu VPA and VDA signal (look at equations)
ALE: a latch signal, active high, that drive U4. Note that this signal is the and of RDY and /PHI2 (inverted). The raison of the anding with RDY is for handle situations where RDY is used for access slow devices: when RDY is low the cpu "frozen" addresses and data, so the latch must be low. Of course this solution work fine if RDY go low just after the rising edge of PHI2, and return high after rising edge of PHI2.
/GOE: enable signal, active low, for U5. In fact this signal is identical to ALE.

Looking at schematic part 2 for the i/o & memory decoder, and the control register that allow to change memory configuration. The control register is based on the addressable latch U11, that allow to reset/set the control lines simply writing to even/odd address on the range $00FC00 - $00FC0F. U12 allow to read back the level of control lines in the same address range. U10 drive the /CRW line (for enable latch, active low) to U11, and the /CRR line (active low) for U12. The /DBE line is the "data bus enable" signal for data transceiver tha drive main data bus. The circuit modification, respect the original design, is the connession between U12-pin 4 and the sensing line SNS that is connected to SW1-3, pulled up by a resistor. At boot, the cpu can sense this line for decide if firmware should be copied, into system ram, from flash chip or from rom emulator. Below the general memory map:

 
|| 	$000000 - $00FBFF MAPPING
||	---------------------------------------
||	ALWAYS MAP TO SYSTEM RAM
||
|| 	$00FC00 - $00FDFF MAPPING
||	---------------------------------------
||	ALWAYS MAP TO SYSTEM I/O (/IO0 & /IO1)
||
|| 	$00FE00 - $00FFFF MAPPING
||	---------------------------------------
|| 	SYS	RW			MAP TO:
||	0	1			FLASH (/FE)
||	0	0			RAM   (/ME)
||	1	X			RAM   (/ME)
||
|| 	$010000 - $013FFF MAPPING
||	---------------------------------------
||	MAP TO EXPANSION RAM (/CX0 & /CX1)
||
|| 	$014000 - $07FFFF MAPPING
||	---------------------------------------
||	ALWAYS MAP TO SYSTEM RAM
||
|| 	$080000 - $0FFFFF MAPPING
||	---------------------------------------
||	EEN				MAP TO:
||	0				RAM   (/ME)
||	1				EEROM (/EE)
||
|| 	$100000 - $DFFFFF MAPPING
||	---------------------------------------
||	ALWAYS MAP TO SYSTEM RAM
||
|| 	$E00000 - $EFFFFF MAPPING
||	---------------------------------------
||	X2E				MAP TO:
||	0				RAM  (/ME)
||	1				DMA  (/CX2)
||
|| 	$F00000 - $F7FFFF MAPPING
||	---------------------------------------
||	RUN	SEL	RW		MAP TO:
||	0	0	1		FLASH
||	0	1	1		EEROM
||	1	0	X		RAM
||	1	1	X		FLASH
||
|| 	$F80000 - $FFFFFF MAPPING
||	---------------------------------------
||	ALWAYS MAP TO SYSTEM RAM
||

Al signals: SYS, RUN, X2E, SEL & EEN are low at reset; in this configuration the range $00FE00 - $00FFFF is mapped, read-only, to flash chip that of course will store the boot code (all vectors are mapped to flash chip at reset). The range $F00000 - $F7FFFF (with RUN=0) is mapped or to flash chip (SEL = 0) or to rom emulator (SEL = 1). The cpu, sensing switch SW1-3, decide the source of the firmware that will be copied in system ram in range $F80000 - $FFFFFF. The boot code in flash chip (should be in range $00FE00 - $00FFFF), can look like this:


	clc
	xce			; native mode
	phk
	plb			; DBR = PBR = 0
	lda	.ABS.$FC00	; sww1-3 sensing
	beq	go		; firmware from flash
	sta	.ABS.$FC09	; set SEL: firmware from rom emulator
go:	ldy	#0
	rep	00110000B	; all 16 bit
	tyx
	lda	#$FFFF		; move a full bank
	mvn	#$F0, #$F8
	mvn	#$F1, #$F9
	mvn	#$F2, #$FA
	mvn	#$F3, #$FB
	mvn	#$F4, #$FC
	mvn	#$F5, #$FD
	mvn	#$F6, #$FE
	mvn	#$F7, #$FF
	sep	00110000B	; all 8 bit
	phk
	plb			; DBR = PBR = 0
	sta	.ABS.$FC08	; reset SEL
	jml	$F80000		; jump to start routine in system ram
	
; the start routine should copy vectors, map  range $00FE00 - $00FFFF to system ram
; setting line SYS, and after set RUN line for final configuration

When system is full running from ram, flash chip can be switched on in range $F00000 - $F7FFFF (read/write) setting the line sel; rom emulator can be switched on on range $080000 - $0FFFFF (read/write) setting the line EEN. On this way flash can be programmed "in-circuit" or with ram as source, or with rom emulator as source.
Schematic part 3 show the main bus connector; the data bus is driven by U15, the R/W, PHI0 & PHI2 are buffered by U16.

Schematics:

GAL equations:

A note about gal equations. I use an alder Orcad PLD compiler, that have a "strange" syntax:

All sources lines must begin with "|"
All comment lines must begin with "||"
The NOT operator is "'"
The AND operator is "&"
The OR operator is "#"
The EX-OR operator is "##"
The CLK operator is "//"
The 3-state operator is "??"
Output level must be specified