||	FILE:	#0050.PLD
||	PROJ:	20180705
||		C16 - CPU 65C816 BOARD
||
||	PART:	G22V10-#0050
||
||	DEV :	GAL22V10
||
|| 	DESC:	MASTER CLOCK
||
|
|GAL22V10
|
|| INPUT
|  1:CLK, 2:PD, 3:F2, 4:S0, 5:VPA, 6:VDA, 7:RES, 8:P2IN, 9:P1IN, 10:P0IN,
|  11:P4IN, 13:RDY,
|| OUTPUT 
|  14:P2O, 15:Q0, 16:Q1, 17:Q2, 18:VMA, 19:ALE, 20:GOE, 
|  21:PHI1, 22:PHI0, 23:P4O
|
| ACTIVE-LOW: VMA
|
| SIGNATURE: "0050    "
|
|| /F2 = 0 SELECT PHI2 = 2MHz
|| /S0 = 0 DELAY THE /GOE SIGNAL (DON'T USE)
|| /PD = 0 DELAY PHI0->PHI2 = 2T
|| P2O = SYSTEM PHI2 CLOCK
|| PHI0 = ARTIFICIAL SYSTEM PHI0 CLOCK
|| P4O  = DELAYED CLOCK
|| CONNECT P0IN TO PHI0
|| CONNECT P1IN TO PHI1
|| CONNECT P4IN TO P4O
||
|| Q0 = 8M, Q1 = 4M, Q2 = 2M  
|  Q[2..0] = CLK // Q[2..0] + 1 
|  A = Q2 & F2'				|| 2MHz
|  B = Q1 & F2				|| 4MHz
|  PHI0 = (A # B)			|| PHI0 CLK
|  P4O = P0IN				|| DELAYED PHI0
|
|| P0IN -> PHI0 DELAYED BY  T (SELECT IF PD = 1)
|| P4IN -> PHI0 DELAYED BY 2T (SELECT IF PD = 0)
|  P2O = ((P0IN & PD) # (P4IN & PD'))	|| PHI2 CLK DELAYED RESPECT PHI0
|
|  PHI1 = P2IN'				|| PHI1 DELAYED RESPECT PHI2
|
|  VMA  = ((VDA & RES) # (VPA & RES))	|| VALID MEM. ACCESS
|
|  ALE    = (RDY & P0IN' & P2IN')	|| ACTIVE WHEN PHI2 LOW & RDY HIGH
|
|| local data bus enable
|  DBEA   = (RDY & P2IN' & S0)		|| LOW WHEN RDY=0 OR PHI2=0 OR S0=0
|  DBEB   = (RDY & P1IN  & S0')		|| LOW WHEN RDY=0 OR PHI1=1 OR S0=1
|  GOE    = (DBEA # DBEB)		|| NOTE: WORK FINE IF S0=1 (DBEA)