||	FILE:	#0054.PLD
||	PROJ:	20180705
||		C16 - CPU 65C816 BOARD
||
||	PART:	G16V8-#0054
||
||	DEV :	GAL16V8
||
|| 	DESC:	DECODER CONTROL REGISTER
||
|
|GAL16V8A
|
|| INPUT
|  1:A4, 2:A5, 3:A6, 4:A7, 5:VMA, 6:IO0, 7:PHI0, 8:RW, 9:PHI2,
|  11:X1, 12:X2,
|| OUTPUT 
|  13:PHI2N, 14:DBE, 15:Y1, 16:Y2, 17:IVR, 18:CRW, 19:CRR
|
|  PROPERTY: "SIMPLE"
|
|  ACTIVE-LOW: PHI2N, Y1, Y2, IVR, CRW, CRR
|
|  SIGNATURE: "0054    "
|
|| IOX -> FC00 - FC0F
|  IOX = (IO0' & A7' & A6' & A5' & A4')
|  CRR = (IOX & RW & PHI2)		|| read  $FC00 - $FC0F
|  CRW = (IOX & RW' & PHI0 & PHI2)	|| write $FC00 - $FC0F
|  IVR = (IOX & RW & PHI2)		|| not used
|  PHI2N = PHI2				|| not used
|  Y1 = X1				|| not used
|  Y2 = X2				|| not used
|
|| data bus enable (low): both IOX and VMA must be low
|  DBE   = (IOX # VMA)