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  Tue Jul 17 11:11:08 2018                                                                                               Page    1







          2500 A.D. 65816 Macro Assembler #26960 - Version 5.02g
          -----------------------------------------------------

                       Input  Filename : src\F8\start.asm
                       Output Filename : obj\F8\start.obj
                       Listing Has Been Relocated                               


 2596                           .LIST           on
 2597                           
 2598  F8FE00                           .INCLUDE inc\dirp00.inc
 2599                           ;----------------------------------------------------------
 2600                           ; DIRP00.ASM
 2601                           ; PROGETTO: B1601
 2602                           ;
 2603                           ; Variabili in Direct Page $00
 2604                           ;----------------------------------------------------------
 2605                           
 2606                           ; sezione COMMON -- questo permette di includere il file in piu' file
 2607                           
 2608                           .LIST on
 2609                           
 2610                           DIRP00: .SECTION page0, ref_only, common        ;Direct-Page 00
 2611                           
 2612  000000                           .ABSOLUTE               ;; inizia sempre da $00
 2613  000000                           .ORG            0x00
 2614  000000                           
 2615  000000  0000             JiffyClk        .DW                     ; contatore 10ms 32 bit
 2616  000002  0000                             .DW
 2617  000004                   SysTmr          .DS     SYSTMRCNT       ; system timer 0 (10ms)
 2618  000008                   SysTMF          .DS     SYSTMRCNT       ; flag timer (80 -> start)
 2619  00000C  00               Bnk0Flag        .DB                     ; <7>: flag test RAM banco 0 ok
 2620                                                                   ; <6>: flag warm reset
 2621  00000D  00               RTCFlag         .DB
 2622                           
 2623  00000E                   diskstat        .DS     2       ; flag device on ata bus #0 & #1
 2624                                                           ; <7>: device ready
 2625                                                           ; <6>: compact flash device (C.F.)
 2626                                                           ; <5>: device identification ok
 2627                                                           ; <4>: MBR loaded
 2628                                                           ; <3>: valid signature in MBR
 2629                                                           ; <2>: first partition found&active
 2630                                                           ; <1>:
 2631                                                           ; <0>: valid partition flag
 2632                           
 2633                                                           ; <7>: device ready
 2634                                                           ; <6>: USB device
 2635                                                           ; <5>: compact flash device (C.F.)
 2636                                                           ; <4>: device identification ok
 2637                                                           ; <3>: MBR loaded
 2638                                                           ; <2>: first partition found&active
 2639                                                           ; <1>: always 1
 2640                                                           ; <0>: valid partition flag
 2641  000010                                                   
  Tue Jul 17 11:11:08 2018                                                                                               Page    2




 2642                           
 2643          00000E           atadev          .EQU    diskstat
 2644                           
 2645  000010                   usbdev          .DS     2       ; flag flash disk on usb bus #0
 2646                                                           ; <7>: device plugged and ready
 2647                                                           ; <6>: always 1 
 2648                                                           ; <5>: device identification ok
 2649                                                           ; <4>: MBR loaded
 2650                                                           ; <3>: valid signature in MBR
 2651                                                           ; <2>: first partition found&active
 2652                                                           ; <1>:
 2653                                                           ; <0>: valid partition flag
 2654                           
 2655  000012                   diskmax         .DS     16      ; disk max. sector's
 2656          000012           atasec          .EQU    diskmax
 2657          00001A           usbsec          .EQU    diskmax+8
 2658                           
 2659                           
 2660  000022                   atambr          .DS     8       ; data for first partition found in mbr
 2661                                                           ; first 3 bytes for start sector of partition
 2662                                                           ; last byte for partition type
 2663  00002A                   usbmbr          .DS     8
 2664                           
 2665  000032                   ataprt          .DS     8       ; total sec's of first partition
 2666  00003A                   usbprt          .DS     8       ; total sec's of first partition
 2667                           
 2668                           
 2669  000042  00               usb0ch          .DB     ; usb0 (ch375/ch376) flag
 2670                                                   ; <7>: module on
 2671                                                   ; <6>: ch376 flag
 2672                                                   ; <5:0>: chip version
 2673                           
 2674  000043  00               usb0st          .DB     ; usb0 status
 2675                                                   ; <7>: usb0 host mode ok
 2676                                                   ; <6>: flash disk attached flag
 2677                                                   ; <5>: usb device attached
 2678                           
 2679  000044  00               fdcdrv          .DB             ; phisycal drive status (drive #0)
 2680                                                           ; <7>: disk format established in bit 0&1 
 2681                                                           ; <6>: double step seek done
 2682                                                           ; <5>: trust format bit's (set after ok r/w)
 2683                                                           ; <4>: write protect bit (if disk in drive)
 2684                                                           ; <3>: don't care
 2685                                                           ; <2>: don't care                               
 2686                                                           ; <1>: HD disk if set else DD disk
 2687                                                           ; <0>: CBM format if set else IBM format
 2688                           
 2689  000045  00               vdrive          .DB             ; virtual drive status (ram disk, drive #1)
 2690                                                           ; <7>: disk format established in bit 0&1 
 2691                                                           ; <6>: change disk simulation (after format)
 2692                                                           ; <5>: don't care
 2693                                                           ; <4>: write protect bit (under sw control)
 2694                                                           ; <3>: don't care
 2695                                                           ; <2>: don't care                               
 2696                                                           ; <1>: HD disk if set else DD disk
 2697                                                           ; <0>: CBM format if set else IBM format
 2698                           
  Tue Jul 17 11:11:08 2018                                                                                               Page    3




 2699  000046  00               fdcctl          .DB             ; fdc controller status
 2700                                                           ; <7>: drive is attached
 2701                                                           ; <6>: drive need recalibration (restore)
 2702                                                           ; <5>: FDC controller ok
 2703                                                           ; <4>: motor on
 2704                                                           ; <3>: dma is active
 2705                                                           ; <2>: dma chip ok (post routine)
 2706                                                           ; <1>: clock rate (1=HD,0=DD)
 2707                                                           ; <0>: disk ready
 2708                           
 2709  000047  00               fdctrk          .DB             ; fd: current seek track
 2710  000048  00               fdcerr          .DB             ; fd: last error code
 2711  000049  00               ataerr          .DB             ; ata: last error code
 2712  00004A  00               ataxer          .DB             ; ata: last extended error code
 2713                           
 2714  00004B  00               CtrlBrk         .DB             ; flag CTRL+BREAK (NMI)
 2715                           
 2716  00004C  0000             MemTop          .DW             ; top memoria RAM
 2717  00004E  00                               .DB             ; banco top mem
 2718                           
 2719  00004F  00               DflTxtIn        .DB             ; device di default text input 
 2720  000050  00               DflTxtOut       .DB             ; device di default text output
 2721                           
 2722  000051                   COPPtr          LP              ; long pointer for COP decoding
 2723  000054  00               COPIdx          .DB             ; COP signature/index
 2724                           
 2725  000055  00               BiosEnt         .DB             ; flag accesso a bios setup
 2726                           
 2727                           ; variabili utilizzate da ACIA
 2728  000056                   spwrk           .DS     $30
 2729                           
 2730                           ; bios mem
 2731  000086  0000             nsize           .DW     ; dimensione blocco da allocare
 2732                           ;bsize          .DW     ; dimensione vera blocco free
 2733  000088  0000             splitsz         .DW     ; dimensione blocco splittato
 2734  00008A  0000             bfree           .DW     ; puntatore blocco free
 2735  00008C  0000             hdrptr          .DW     ; puntatore header heap
 2736                           
 2737  00008E  0000             pbrklv          .DW     ; current break level of current process
 2738  000090  0000             pbrkmin         .DW     ; minimum breal level of current process
 2739  000092  0000             pbrkmax         .DW     ; maximum breal level of current process
 2740  000094                           
 2741                           ; bios temp. work area
 2742  000094                   bwrktmp         .DS     $28
 2743                           
 2744  0000BC  00               coptmp          .DB     ; temp. used while cop
 2745                           
 2746  0000BD  00               tstser          .DB     ; check ser/usb test board post
 2747                                                   ; <7>: VIA2 ok
 2748                                                   ; <6>: PICRAM ok
 2749                                                   ; <1>: UART 16C550 ok
 2750                                                   ; <0>: R65C51 ok
 2751                           
 2752                           
 2753                           ;crc16          .DW
 2754                           
 2755  0000BD                           .RELATIVE
  Tue Jul 17 11:11:08 2018                                                                                               Page    4




 2756                           
 2757                                   .ENDS
 2758                           
 2759          [01]             .IFDEF          _ACIA_INC_
 2760  F8FE00                           .INCLUDE INC\SP.INC
 2761                           ;;
 2762                           ;; Copyright (c) 2016 Marco Granati <mg@unet.bz>
 2763                           ;;
 2764                           ;; Permission to use, copy, modify, and distribute this software for any
 2765                           ;; purpose with or without fee is hereby granted, provided that the above
 2766                           ;; copyright notice and this permission notice appear in all copies.
 2767                           ;;
 2768                           ;; THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 2769                           ;; WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 2770                           ;; MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 2771                           ;; ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 2772                           ;; WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 2773                           ;; ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 2774                           ;; OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 2775                           ;;
 2776                           
 2777                           ;; name: sp.inc 
 2778                           ;; rev.: 2016/07/28
 2779                           ;; bios C816 version v1.0
 2780                           
 2781                           .LIST on
 2782                           
 2783          000001           SOH             .EQU    $01
 2784          000002           STX             .EQU    $02
 2785          000003           ETX             .EQU    $03
 2786          000004           EOT             .EQU    $04
 2787          000005           ENQ             .EQU    $05
 2788          000006           ACK             .EQU    $06
 2789          000010           DLE             .EQU    $10
 2790          000016           SYN             .EQU    $16
 2791                           
 2792          002000           SOBUFSIZ        .EQU    $2000   ; dimensione coda TX1/TX2 ACIA (8K)
 2793                           ;SOBUFSIZ       .EQU    $0100   ; dimensione coda TX1/TX2 ACIA (8K)
 2794          004000           SIBUFSIZ        .EQU    $4000   ; dimensione coda RX1/RX2 ACIA (16K)
 2795                           ;SIBUFSIZ       .EQU    $0100   ; dimensione coda RX1/RX2 ACIA (16K)
 2796                           
 2797          000080           NGUARD1         .EQU    $80     ; numero bytes di guardia buffer RX XON/XOFF
 2798          000040           NGUARD2         .EQU    $40     ; numero bytes di guardia buffer RX handshake
 2799                           ;NGUARD1                .EQU    $40     ; numero bytes di guardia buffer RX XON/XOFF
 2800                           ;NGUARD2                .EQU    $20     ; numero bytes di guardia buffer RX handshake
 2801          001000           NFREE1          .EQU    $1000   ; minimo posto in coda RX per cancellare pausa remota
 2802          000800           NFREE2          .EQU    $0800
 2803                           ;NGUARD3                .EQU    $F0
 2804                           ;NGUARD4                .EQU    $F8
 2805                           
 2806                           ;---------------------------------------------------------------------------
 2807                           ; direct page var's for serial ports handling 
 2808                           ;---------------------------------------------------------------------------
 2809                           
 2810                           DPSP:   .SECTION page0, common, ref_only, offset spwrk  ;ACIA D.P.
 2811                           
 2812  000056                   _DPSP_START     .DS     0
  Tue Jul 17 11:11:08 2018                                                                                               Page    5




 2813                           
 2814                           ; WARNING: not change order and type of the following variables
 2815                           
 2816                           ; acia 1 var's
 2817  000056  00               splin           .DB             ; interrupt status register
 2818  000057  00               spcsr           .DB             ; control status register
 2819  000058  00               spfr            .DB             ; format register
 2820  000059  00               spout           .DB             ; XON/XOFF send flag
 2821                           
 2822                           ; acia 2 var's
 2823  00005A  00               splin2          .DB             ; interrupt status register
 2824  00005B  00               spcsr2          .DB             ; control status register
 2825  00005C  00               spfr2           .DB             ; format register
 2826  00005D  00               spout2          .DB             ; XON/XOFF send flag
 2827                           
 2828                           ; serial port's mode & status
 2829  00005E  00               spmode          .DB             ; <7>: 0=no handshake, 1=handshake
 2830                                                           ; <6>: 0=software/1=hardware handshake
 2831                                                           ; <5>: not used
 2832                                                           ; <4>: baud rate: 0=19200, 1=38400
 2833                                                           ; <3>: 0=odd parity, 1=even parity
 2834                                                           ; <2>: 0=no parity, 1=parity as specified
 2835                                                           ;      by bit <3>
 2836                                                           ; <1>: interface type: 0=RS232, 1=RS485
 2837                                                           ; <0>: RS232: uplink flow control (RTS/DCD)
 2838                                                           ;      RS485: 120 ohm termination on
 2839                                                           ; if bit 7=1 and bit 1=1, bit 6 is forced to 0
 2840  00005F                                           
 2841  00005F  00               spstat          .DB             ; serial port status            
 2842                                                           ; <7>: rx error (data discarded)
 2843                                                           ; <6>: rx buffer overflow
 2844                                                           ; <5>: remote disconnession (DSR line = 1)
 2845                                                           ; <4>: output buffer overflow
 2846                                                           ; <3>: not used
 2847                                                           ; <2>: framing error
 2848                                                           ; <1>: parity error
 2849                                                           ; <0>: overrun error
 2850                           
 2851  000060  00               sppause         .DB             ; local/remote pause flag's             
 2852                                                           ; <7>: remote pause (sent an XON or set RTS=1)
 2853                                                           ; <6>: local pause (received an XON or CTS=1)
 2854                           
 2855  000061  00               sptmp           .DB             ; temp. byte used while get data
 2856                           
 2857                           ; serial port's mode & status
 2858  000062  00               spmode2         .DB             ; <7>: 0=no handshake, 1=handshake
 2859                                                           ; <6>: 0=software/1=hardware handshake
 2860                                                           ; <5>: not used
 2861                                                           ; <4>: baud rate: 0=19200, 1=38400
 2862                                                           ; <3>: 0=odd parity, 1=even parity
 2863                                                           ; <2>: 0=no parity, 1=parity as specified
 2864                                                           ;      by bit <3>
 2865                                                           ; <1>: interface type: 0=RS232, 1=RS485
 2866                                                           ; <0>: RS232: uplink flow control (RTS/DCD)
 2867                                                           ;      RS485: 120 ohm termination on
 2868                                                           ; if bit 7=1 and bit 1=1, bit 6 is forced to 0
 2869  000063                                           
  Tue Jul 17 11:11:08 2018                                                                                               Page    6




 2870  000063  00               spstat2         .DB             ; serial port status            
 2871                                                           ; <7>: rx error (data discarded)
 2872                                                           ; <6>: rx buffer overflow
 2873                                                           ; <5>: remote disconnession (DSR line = 1)
 2874                                                           ; <4>: output buffer overflow
 2875                                                           ; <3>: not used
 2876                                                           ; <2>: framing error
 2877                                                           ; <1>: parity error
 2878                                                           ; <0>: overrun error
 2879                           
 2880  000064  00               sppause2        .DB             ; local/remote pause flag's             
 2881                                                           ; <7>: remote pause (sent XOFF/XON or RTS=1/0)
 2882                                                           ; <6>: local pause (rx XOFF/XON or CTS=0/1)
 2883                           
 2884  000065  00               sppost          .DB             ; after POST must hold $C0
 2885                           
 2886  000066  0000             ibuftail        .DW             ; pointer to tail of input buffer
 2887  000068  0000             ibufhead        .DW             ; pointer to head of input buffer
 2888  00006A  0000             ibuftail2       .DW
 2889  00006C  0000             ibufhead2       .DW
 2890                           
 2891  00006E  0000             obuftail        .DW             ; pointer to tail of output buffer
 2892  000070  0000             obufhead        .DW             ; pointer to head of output buffer
 2893  000072  0000             obuftail2       .DW
 2894  000074  0000             obufhead2       .DW
 2895                           
 2896  000076  0000             ibufcnt         .DW             ; count of bytes in input buffer
 2897  000078  0000             obufcnt         .DW             ; count of bytes in output buffer
 2898  00007A  0000             ibufcnt2        .DW
 2899  00007C  0000             obufcnt2        .DW
 2900                           
 2901  00007E  0000             icntmin         .DW             ; min. count for clear remote pause  
 2902  000080  0000             icntmax         .DW             ; max. count for set remote pause
 2903  000082  0000             icntmin2        .DW
 2904  000084  0000             icntmax2        .DW
 2905                           
 2906  000086                   _DPSP_END       .DS     0
 2907          000030           DPSPSIZ         .EQU    (_DPSP_END - _DPSP_START)
 2908                           
 2909                           
 2910                                   .ENDS
 2911                           
 2912          00005F           ACIArxe_1       .EQU    spstat
 2913          000063           ACIArxe_2       .EQU    spstat2
 2914          00005E           ACIAhsk_1       .EQU    spmode
 2915          000062           ACIAhsk_2       .EQU    spmode2
 2916          000060           ACIAPause_1     .EQU    sppause
 2917          000064           ACIAPause_2     .EQU    sppause2
 2918          000057           ACIAcsr_1       .EQU    spcsr
 2919          00005B           ACIAcsr_2       .EQU    spcsr2
 2920          000058           ACIAfr_1        .EQU    spfr
 2921          00005C           ACIAfr_2        .EQU    spfr2
 2922          000060           ACIAOut_1       .EQU    sppause
 2923          000064           ACIAOut_2       .EQU    sppause2
 2924          000076           ACIAICnt_1      .EQU    ibufcnt
 2925          00007A           ACIAICnt_2      .EQU    ibufcnt2
 2926          000068           ACIAIHead_1     .EQU    ibufhead
  Tue Jul 17 11:11:08 2018                                                                                               Page    7




 2927          00006C           ACIAIHead_2     .EQU    ibufhead2
 2928          000066           ACIAITail_1     .EQU    ibuftail
 2929          00006A           ACIAITail_2     .EQU    ibuftail2
 2930          000078           ACIAOCnt_1      .EQU    obufcnt
 2931          00007C           ACIAOCnt_2      .EQU    obufcnt2
 2932          000070           ACIAOHead_1     .EQU    obufhead
 2933          000074           ACIAOHead_2     .EQU    obufhead2
 2934          00006E           ACIAOTail_1     .EQU    obuftail
 2935          000072           ACIAOTail_2     .EQU    obuftail2
 2936                           
 2937          002000           ACIAOBUFLEN     .EQU    SOBUFSIZ
 2938          004000           ACIAIBUFLEN     .EQU    SIBUFSIZ
 2939          050000           ACIAOUTBUF1     .EQU    SPOUTBUFF
 2940          052000           ACIAOUTBUF2     .EQU    SPOUTBUFF2
 2941          054000           ACIAINBUF1      .EQU    SPINBUFF
 2942          058000           ACIAINBUF2      .EQU    SPINBUFF2
 2943                           
 2944          000061           ACIATmp         .EQU    sptmp
 2945                           
 2963                           .LIST on
 2964                           
 2965          000060           KBDBUFLEN       .EQU    96              ; dimensione buffer di tastiera
 2966                           
 2967                           DIRP01: .SECTION page0, ref_only, common        ;Direct-Page 01
 2968                           
 2969  000000                           .ABSOLUTE               ;; inizia sempre da $00
 2970  000000                           .ORG            0x00
 2971                           
 2972  000000                           
 2973  000000                   KbdBuf          .DS     KBDBUFLEN       ; buffer della tastiera
 2974  000060  00               KbdITail        .DB                     ; coda buffer tastiera
 2975  000061  00               KbdIHead        .DB                     ; testa buffer tastiera
 2976  000062  00               KbdCnt          .DB                     ; numero bytes nel buffer
 2977  000063  00               KbdShift        .DB
 2978  000064  00               KbdFlag         .DB
 2979  000065  00               KbdToggle       .DB
 2980  000066  00               KbdSt           .DB                     ; status tastiera dopo reset
 2981  000067  00               PS2Ctl          .DB                     ; flag controller PS2 keyboard
 2982                           
 2983  000068  00               LCDFlag         .DB
 2984  000069  00               LCDTmp          .DB
 2985  00006A  0000             LCDVal          .DW
 2986                           
 2987  00006C  00               VBBFlag         .DB             ; flag video board
 2988  00006D  00               VBBRam          .DB             ; flag video RAM
 2989                           
 2990  00006E  00               ScnLinTmp       .DB
 2991  00006F  00               ScnChBase       .DB             ; base video ram VDC
 2992  000070  00               ScnAttBase      .DB             ; base ram attributi VDC
 2993  000071  00               ScnCursMode     .DB             ; VDC cursore default
 2994  000072  00               ScnSaveAttr     .DB
 2995  000073  00               ScnInsert       .DB
 2996  000074  00               ScnAutoIns      .DB             ; bit 7 -> autoins - bit 6 -> modo input
 2997  000075  00               ScnScroll       .DB
 2998  000076  00               ScnMaxRow       .DB             ; max. righe finestra (-1)
 2999  000077  00               ScnMaxCols      .DB             ; max. colonne finestra (-1)
 3000                           
  Tue Jul 17 11:11:08 2018                                                                                               Page    8




 3001  000078                   ScnMapTabs1     .DS     10
 3002  000082                   ScnMapTabs2     .DS     4
 3003  000086                           
 3004  000086  0000             ScnPtr          .DW             ; puntatore video ram linea corrente
 3005  000088  00                               .DB
 3006                           
 3007  000089  00               ScnFiltLen      .DB             ; lunghezza set caratteri filtro
 3008                           
 3009  00008A  0000             ScnAtPtr        .DW             ; puntatore attributi ram linea corrente
 3010  00008C  00                               .DB
 3011                           
 3012  00008D  00               ScnTmpx         .DB             ; temporaneo: durante put char
 3013  00008E                                   
 3014  00008E  00               ScnTop          .DB             ; riga superiore finestra
 3015  00008F  00               ScnLeft         .DB             ; colonna sinistra finestra
 3016  000090  00               ScnBottom       .DB             ; riga inferiore finestra
 3017  000091  00               ScnRight        .DB             ; colonna destra finestra
 3018  000092  00               ScnAttr         .DB             ; attributo default
 3019  000093  00               ScnAttr2        .DB             ; attributo alternativo
 3020  000094  00               ScnRow          .DB             ; riga cursore
 3021  000095  00               ScnCol          .DB             ; colonna cursore
 3022  000096  00               ScnRowStart     .DB             ; riga di start input 
 3023  000097  00               ScnInput        .DB             ; riga di fine input 
 3024  000098  00               ScnColStart     .DB             ; colonna di start input 
 3025  000099  00               ScnSaveX        .DB
 3026  00009A  00               ScnSaveY        .DB
 3027  00009B  00               ScnTmpL         .DB
 3028  00009C  00               ScnTmpH         .DB
 3029  00009D  00               ScnSaveRow      .DB
 3030  00009E  00               ScnSaveCol      .DB
 3031  00009F  00               ScnCurChr       .DB
 3032  0000A0  00               ScnLstChr       .DB
 3033  0000A1  00               ScnCR           .DB
 3034  0000A2  0000             ScnPrm          .DW             ; puntatore long utilizzato da print imm
 3035  0000A4  00                               .DB             ; banco puntatore ScnPrm
 3036  0000A5  00               ScnMode         .DB             ; flag modo schermo
 3037                           
 3038  0000A6                   ScnPtr1         LP
 3039                           
 3040  0000A9  00               ScnDefCol       .DB             ; default foreground color
 3041                           
 3042  0000AA                   ScnPtr2         LP
 3043                           
 3044  0000AD  00               ScnDefBkgCol    .DB             ; default background color
 3045  0000AE  00               ScnInpRow       .DB             ; modo input line: riga start input
 3046  0000AF  00               ScnInpCol       .DB             ; modo input line: colonna start input
 3047  0000B0  00               ScnLstRow       .DB             ; modo input line: riga stop input
 3048  0000B1  00               ScnLstCol       .DB             ; modo input line: colonna stop input
 3049  0000B2  00               ScnFlag         .DB             ; Bit 7: input line - Bit 6: input riga unica
 3050  0000B3  00               ScnMask         .DB             ; flag tasti funzione editor di linea
 3051  0000B4  00               ScnFilt         .DB             ; filtro tasti editor di linea
 3052  0000B5  00               ScnCntrl        .DB             ; flag ASCII/CONTROL
 3053                           ;DflTxtIn       .DB             ; device di default text input 
 3054                           ;DflTxtOut      .DB             ; device di default text output
 3055  0000B6                           
 3056          000047           SCNCLRLEN       .EQU    ($ - ScnLinTmp - 1)
 3057                           
  Tue Jul 17 11:11:08 2018                                                                                               Page    9




 3058                           ;SCNCLRLEN      .EQU    (DflTxtOut - ScnLinTmp)
 3059                           
 3060                           ; variabili monitor
 3061  0000B6  00               SMAddrL         .DB     ; address low/high
 3062  0000B7  00               SMAddrH         .DB
 3063  0000B8  00               SMAddrK         .DB     ; address bank
 3064  0000B9  00               SMFlag32        .DB     ; flag parametro 32 bit
 3065  0000BA  00               SMTmpL          .DB     ; temp. low/high
 3066  0000BB  00               SMTmpH          .DB
 3067  0000BC  00               SMTmpK          .DB     ; temp. bank
 3068  0000BD  00               SMTmpKK         .DB     ; high byte param. 32 bit
 3069  0000BE  00               SMSizeL         .DB     ; size low/high
 3070  0000BF  00               SMSizeH         .DB
 3071  0000C0  00               SMSizeK         .DB     ; size bank
 3072  0000C1  00               SMXAddrL        .DB     ; address low/high XM
 3073  0000C2  00               SMXAddrH        .DB
 3074  0000C3  00               SMXAddrK        .DB     ; address bank XM
 3075  0000C4  00               SMbndx          .DB     ; indice input buffer
 3076  0000C5  00               SMnprm          .DB     ; numero parametri riga di comando
 3077  0000C6  00               SMdumb          .DB
 3078  0000C7  00               SMkr            .DB
 3079  0000C8  0000             SMpc            .DW
 3080  0000CA  00               SMsr            .DB
 3081  0000CB  00               SMbr            .DB
 3082  0000CC  0000             SMdp            .DW
 3083  0000CE  0000             SMac            .DW
 3084  0000D0  0000             SMxr            .DW
 3085  0000D2  0000             SMyr            .DW
 3086  0000D4  0000             SMsp            .DW
 3087                           
 3088  0000D6  00               SMAuxL          .DB
 3089  0000D7  00               SMAuxH          .DB
 3090                           
 3091  0000D8  00               asmlong         .DB     ; flag for CPU in 16 mode
 3092                                                   ; <7> -> A/M in 16 bit mode
 3093                                                   ; <6> -> X/Y in 16 bit mode
 3094  0000D9  00               asmcpu          .DB     ; <7> -> 8 bit family
 3095                                                   ; <6> -> 65C02 cmos version
 3096                           
 3097  0000DA  00               SMctx           .DB     ; context (if = $00 no quit command)
 3098  0000DB                   SMrsm           LP      ; long pointer to resume caller context
 3099                           
 3100  0000DE  00               rtcadr          .DB     ; rtc internal ram address
 3101  0000DF  00               rtcbnk          .DB     ; RTC internal bank ram
 3102  0000E0  00               cmdlin          .DB     ;
 3103  0000E1  00               SMesc           .DB
 3104                           
 3105  0000E2                   SMXTmp:         .DS     26      ; 26 bytes tmp
 3106                           
 3107          0000E2           SMTmp2          .EQU    SMXTmp
 3108          0000E4           SMTmp3          .EQU    SMXTmp+2
 3109          0000E6           SMdwTmp1        .EQU    SMXTmp+4
 3110          0000EA           SMdwTmp2        .EQU    SMXTmp+8
 3111          0000EE           SMFsrc          .EQU    SMXTmp+12       ; source bank for flash update
 3112          0000EF           SMFflag         .EQU    SMXTmp+13       ; flag file for flash update
 3113          0000F0           SMXPos2         .EQU    SMXTmp+14
 3114          0000F1           SMYPos2         .EQU    SMXTmp+15
  Tue Jul 17 11:11:08 2018                                                                                               Page   10




 3115          0000F2           SMXPos3         .EQU    SMXTmp+16
 3116          0000F3           SMYPos3         .EQU    SMXTmp+17
 3117                           ;SMAuxL         .EQU    SMXTmp+18
 3118                           ;SMAuxH         .EQU    SMXTmp+19
 3119          0000F6           SMXPos          .EQU    SMXTmp+20
 3120          0000F7           SMYPos          .EQU    SMXTmp+21
 3121          0000F8           SMdwTmp3        .EQU    SMXTmp+22
 3122                           
 3123          0000E2           atcmd           .EQU    SMXTmp          ; save @ command
 3124          0000E3           atnum           .EQU    SMXTmp+1        ; @ command index
 3125          0000E4           atflag          .EQU    SMXTmp+2        ; @ L,S,V,R,W start address flag
 3126          0000E5           atbnk           .EQU    SMXTmp+3        ; @ L,S,V,R,W bank
 3127          0000E6           atstr           .EQU    SMXTmp+4        ; @ command string start (word)
 3128          0000E8           atstart         .EQU    SMXTmp+6        ; @ L,S,V,R,W start address (word)
 3129          0000EA           atend           .EQU    SMXTmp+8        ; @ S,W end address (word)
 3130          0000EC           atbuf           .EQU    SMXTmp+10       ; @ local buffer pointer (word)
 3131          0000EE           atipb           .EQU    SMXTmp+12       ; @ bank of input buffer
 3132          0000EF           atdir           .EQU    SMXTmp+13       ; @ load dir flag
 3133          0000F0           atptr           .EQU    SMXTmp+14       ; @ load dir pointer (word)
 3134          0000F2           atsiz           .EQU    SMXTmp+16       ; @ buffer size (word) 
 3135          0000F5           atlp            .EQU    SMXTmp+19       ; @ long pointer
 3136          0000F8           atsa            .EQU    SMXTmp+22       ; @ sa
 3137                           
 3138          0000E2           btmpx           .EQU    SMXTmp          ; asc2bin conversion
 3139          0000E3           brtcsec         .EQU    SMXTmp+1
 3140          0000E4           brtcmin         .EQU    SMXTmp+2
 3141          0000E5           brtchour        .EQU    SMXTmp+3
 3142          0000E6           brtcday         .EQU    SMXTmp+4
 3143          0000E7           brtcmonth       .EQU    SMXTmp+5
 3144          0000E8           brtcyear        .EQU    SMXTmp+6
 3145          0000E9           brtcct          .EQU    SMXTmp+7
 3146                           
 3147                           
 3148  0000FC                           .RELATIVE
 3149                           
 3150                                   .ENDS
 3151                           
 3175                           .LIST on
 3176                           
 3177          05C000           SOBUFADDR3      .EQU    SPOUTBUFF3
 3178          05D000           SIBUFADDR3      .EQU    SPINBUFF3
 3179          001000           SOBUFSIZ3       .EQU    $1000
 3180          001000           SIBUFSIZ3       .EQU    $1000
 3181                           
 3182          060000           SOBUFADDR4      .EQU    SPOUTBUFF4
 3183          068000           SIBUFADDR4      .EQU    SPINBUFF4
 3184                           ;SOBUFSIZ4      .EQU    $1000
 3185                           ;SIBUFSIZ4      .EQU    $1000
 3186          008000           SOBUFSIZ4       .EQU    $8000
 3187          008000           SIBUFSIZ4       .EQU    $8000
 3188                           
 3189          000200           NGUARD31        .EQU    $0200   ; numero bytes di guardia buffer RX XON/XOFF
 3190          000100           NGUARD32        .EQU    $0100   ; numero bytes di guardia buffer RX handshake
 3191          000800           NFREE31         .EQU    $0800   ; minimo posto in coda RX per cancellare pausa remota
 3192          000400           NFREE32         .EQU    $0400
 3193                           
 3194                           ;---------------------------------------------------------------------------
  Tue Jul 17 11:11:08 2018                                                                                               Page   11




 3195                           ; direct page var's for test serial ports/usb handling 
 3196                           ;---------------------------------------------------------------------------
 3197                           
 3198                           DPSP2:  .SECTION page0, common, ref_only        ;UART D.P.
 3199                           
 3200  000000  00               usbslv          .DB     ; <7>: plugged-in, <6>: plug-in pending 
 3201  000001  00               usbum           .DB     ; <7>: pending message, <6>: connected  
 3202  000002  00               usbcnt1         .DB     ; timeout UM245 plug-in detection
 3203  000003                   usbbuf          .DS     8       
 3204  00000B  00               usbtim          .DB
 3205  00000C  00               usbcnt          .DB
 3206  00000D  00               usbmst          .DB
 3207  00000E  0000             usbsiz          .DW
 3208  000010                   usbptr          LP
 3209  000013  00               usbtmp          .DB
 3210  000014  00               usbcmp          .DB
 3211                           
 3212                           ; serial port 65C51
 3213  000015  00               spmode3         .DB     ; <7>: 0=no handshake, 1=handshake
 3214                                                   ; <6>: 0=software/1=hardware handshake
 3215                                                   ; <5>: not used
 3216                                                   ; <4>: not used
 3217                                                   ; <3>: 0=odd parity, 1=even parity
 3218                                                   ; <2>: 0=no parity, 1=parity as specified
 3219                                                   ;      by bit <3>
 3220                                                   ; <1:0> : baud rate
 3221                                                   ;       00 =  19200
 3222                                                   ;       01 =  38400
 3223                                                   ;       10 =  57600
 3224                                                   ;       11 = 115200
 3225  000016                                           
 3226  000016  00               splin3          .DB     ; <7>: /CTS line level
 3227                                                   ; <6>: /DSR line status
 3228  000017                                           
 3229  000017  00               sppause3        .DB
 3230  000018  00               spout3          .DB
 3231  000019  00               spstat3         .DB     ; staus
 3232                                                   ; <7>: rx error (data discarded)
 3233                                                   ; <6>: rx buffer overflow
 3234                                                   ; <5>: remote disconnession (/DSR line = 1)
 3235                                                   ; <4>: output buffer overflow
 3236                                                   ; <3>: not used
 3237                                                   ; <2>: framing error
 3238                                                   ; <1>: parity error
 3239                                                   ; <0>: overrun error
 3240                           
 3241  00001A  00               sptmp3          .DB
 3242                           
 3243  00001B  0000             ibuftail3       .DW
 3244  00001D  0000             ibufhead3       .DW
 3245  00001F  0000             obuftail3       .DW
 3246  000021  0000             obufhead3       .DW
 3247  000023  0000             ibufcnt3        .DW
 3248  000025  0000             obufcnt3        .DW
 3249  000027  0000             icntmin3        .DW
 3250  000029  0000             icntmax3        .DW
 3251                           
  Tue Jul 17 11:11:08 2018                                                                                               Page   12




 3252                           ; serial port 16C550
 3253  00002B  00               spmode4         .DB     ; <7>: 0=no handshake, 1=handshake
 3254                                                   ; <6>: 0=software/1=hardware handshake
 3255                                                   ; <5>: not used
 3256                                                   ; <4>: not used
 3257                                                   ; <3>: 0=odd parity, 1=even parity
 3258                                                   ; <2>: 0=no parity, 1=parity as specified
 3259                                                   ;      by bit <3>
 3260                                                   ; <1:0> : baud rate
 3261                                                   ;       00 =  19200
 3262                                                   ;       01 =  38400
 3263                                                   ;       10 =  57600
 3264                                                   ;       11 = 115200
 3265  00002C                                           
 3266  00002C  00               splin4          .DB     ; <7>: /DSR line level
 3267                                                   ; <6>: /CTS line status
 3268  00002D                                           
 3269  00002D  00               sppause4        .DB
 3270  00002E  00               spout4          .DB
 3271  00002F  00               spstat4         .DB     ; staus
 3272                                                   ; <7>: rx error (data discarded)
 3273                                                   ; <6>: rx buffer overflow
 3274                                                   ; <5>: remote disconnession (/DSR line = 1)
 3275                                                   ; <4>: output buffer overflow
 3276                                                   ; <3>: break
 3277                                                   ; <2>: framing error
 3278                                                   ; <1>: parity error
 3279                                                   ; <0>: overrun error
 3280                           
 3281  000030  00               sptmp4          .DB
 3282                           
 3283  000031  0000             ibuftail4       .DW
 3284  000033  0000             ibufhead4       .DW
 3285  000035  0000             obuftail4       .DW
 3286  000037  0000             obufhead4       .DW
 3287  000039  0000             ibufcnt4        .DW
 3288  00003B  0000             obufcnt4        .DW
 3289  00003D  0000             icntmin4        .DW
 3290  00003F  0000             icntmax4        .DW
 3291                           
 3292  000041  00               spcnt4          .DB
 3293  000042  00               uartlsr         .DB
 3294  000043  00               uartiir         .DB
 3295                           
 3296  000044                   usb0name        .DS     36
 3297                           
 3298                                   .ENDS
 3299                           
 3305                                   .LIST on
 3306                           
 3307                                   .CODEF8
 3308                           
 3309                           ;----------------------------------------------------------
 3310                           ; ---- CODICE START & INTERRUPT
 3311                           ;----------------------------------------------------------
 3312                           
 3313                                   .SYSCODE
  Tue Jul 17 11:11:08 2018                                                                                               Page   13




 3314  F8F000                           
 3315          000162           _KbdCnt         .EQU    (DP01ADDR + KbdCnt)
 3316          000165           _KbdToggle      .EQU    (DP01ADDR + KbdToggle)
 3317          000166           _KbdSt          .EQU    (DP01ADDR + KbdSt)
 3318          000167           _PS2Ctl         .EQU    (DP01ADDR + PS2Ctl)
 3319          000160           _KbdITail       .EQU    (DP01ADDR + KbdITail)
 3320          000161           _KbdIHead       .EQU    (DP01ADDR + KbdIHead)
 3321          000163           _KbdShift       .EQU    (DP01ADDR + KbdShift)
 3322          000164           _KbdFlag        .EQU    (DP01ADDR + KbdFlag)
 3323  F8F000                           
 3324  F8F000                           LONG_OFF
 3325                                   .LONGA  off
 3326                                   .LONGI  off
 3327                                   .MNLIST
 3328  F8F000                           
 3329                                   .GLOBAL _KbdCnt, _KbdToggle, _KbdSt, _PS2Ctl, _KbdITail
 3330                                   .GLOBAL _KbdIHead, _KbdShift, _KbdFlag
 3331                                   .GLOBAL TORAM
 3332                           
 3333  F8F000                   TORAM:  
 3334                           ; vettori ISR
 3335  F8F000                   intsr:
 3336  F8F000  10F0 04F1 F8F1           .DW     int0sr, int1sr, int2sr, int3sr
               ACF2 
 3337  F8F008  D3F3 C9F5 C9F5           .DW     int4sr, int5sr, int6sr, int7sr
               CAF5 
 3338                           
 3339  F8F010                   int0sr:
 3340  F8F010                           SPISR   0
 3341          [01]                     .IFZ    0
 3342          000000           k       .SET    0
 3343          050000           SOBUFADDR       .SET    SPOUTBUFF
 3344          054000           SIBUFADDR       .SET    SPINBUFF
 3345          [01]                     .ELSE
 3346                           k       .SET    4
 3347                           SOBUFADDR       .SET    SPOUTBUFF2
 3348                           SIBUFADDR       .SET    SPINBUFF2
 3349          [00]                     .ENDIF
 3350                           
 3351  F8F010  AC 50 FD                 ldy     .ABS.ACIAISR+k  ; interrupt status reg. (clear bit 3,4,5)
 3352  F8F013  AD 51 FD                 lda     .ABS.ACIACSR+k  ; control status register
 3353                                   ;sty    spisr+k         ; save interrupt status reg. 
 3354  F8F016  85 57                    sta     spcsr+k         ; save control status reg.
 3355  F8F018  98                       tya                     ; Y=status reg.
 3356  F8F019  4A                       lsr     a               ; test RDRF bit
 3357  F8F01A  90 76                    bcc     ?lin            ; go to test control lines
 3358  F8F01C  AE 53 FD                 ldx     .ABS.ACIARDR+k  ; fetch rx data (clear int. status bits 0,1,2)
 3359  F8F01F  24 5F                    bit     spstat+k        ; rx error pending?
 3360  F8F021  30 6F                    bmi     ?lin            ; yes, discard received data & test ctr. lines
 3361  F8F023  29 03                    and     #00000011B      ; 1: overrun/frame error, 2: parity error
 3362  F8F025  24 57                    bit     spcsr+k         ; test control status reg. bit 7: FE
 3363  F8F027  10 04                    bpl     ?nof            ; no framing error
 3364  F8F029  09 04                    ora     #00000100B      ; set framing error bit...
 3365  F8F02B  29 FE                    and     #$FE            ; ...and clear overrun error
 3366  F8F02D  C9 00            ?nof:   cmp     #0
 3367  F8F02F  F0 04                    beq     ?rxok           ; no rx error
 3368  F8F031  09 80                    ora     #10000000B      ; set rx error bit
  Tue Jul 17 11:11:08 2018                                                                                               Page   14




 3369  F8F033  80 45                    bra     ?sst            ; set stus reg. & discard received data
 3370  F8F035  8A               ?rxok:  txa                     ; A=received data       
 3371  F8F036                           INDEX16
 3372                                   .MLIST
 3373  F8F036  C2 10                    rep     #PXFLAG
 3374                                   .LONGI  on
 3375                                   .MNLIST
 3376  F8F038  A6 76                    ldx     ibufcnt+k       ; count of bytes stored in input buffer
 3377  F8F03A  24 5E                    bit     spmode+k        ; test if handshake is active
 3378  F8F03C  10 35                    bpl     ?chk            ; bit 7=0 -> no handshake so check input buff.
 3379  F8F03E  70 14                    bvs     ?tst            ; bit 6=1 -> hardware handshake
 3380  F8F040  C9 11                    cmp     #SPXON          ; received an XON control byte?
 3381  F8F042  D0 06                    bne     ?xoff           ; no, check if received an XOFF
 3382  F8F044  A9 40                    lda     #$40            ; received an XON: clear local pause flag
 3383  F8F046  14 60                    trb     sppause+k       ; bit 6=0 -> local pause off (resume tx)
 3384  F8F048  80 46                    bra     ?cnt            ; discard received data
 3385  F8F04A  C9 13            ?xoff:  cmp     #SPXOFF         ; received an XOFF control byte?
 3386  F8F04C  D0 06                    bne     ?tst            ; no, check condition for remote pause
 3387  F8F04E  A9 40                    lda     #$40            ; set local pause flag
 3388  F8F050  04 60                    tsb     sppause+k       ; bit 6=1 -> local pause on (stop tx operation)
 3389  F8F052  80 3C                    bra     ?cnt            ; discard received data
 3390  F8F054  E4 80            ?tst:   cpx     icntmax+k       ; check input buff. for remote pause condition
 3391  F8F056  90 26                    bcc     ?str            ; below guard limit: store data
 3392  F8F058  24 60                    bit     sppause+k       ; remote pause is already on ?
 3393  F8F05A  30 17                    bmi     ?chk            ; yes, so check input buffer
 3394  F8F05C  EB                       xba                     ; B = received data
 3395  F8F05D  24 5E                    bit     spmode+k        ; test handshake type
 3396  F8F05F  70 06                    bvs     ?rtsh           ; bit 6=1 -> hardware handshake so set RTS=1
 3397  F8F061  A9 13                    lda     #SPXOFF         ; send an XOFF to remote terminal
 3398  F8F063  85 59                    sta     spout+k         ; XOFF sending deffered until TDRE is set
 3399  F8F065  80 0B                    bra     ?xba            ; check input buffer            
 3400  F8F067  A5 58            ?rtsh:  lda     spfr+k          ; hardware handshake...
 3401  F8F069  09 81                    ora     #10000001B      ; ...set RTS=1
 3402  F8F06B  8D 51 FD                 sta     .ABS.ACIAFR+k   ; update format register
 3403  F8F06E  A9 80                    lda     #$80            ; set remote pause
 3404  F8F070  04 60                    tsb     sppause+k       ; bit 7=1 -> remote pause on
 3405  F8F072  EB               ?xba:   xba                     ; A = received data
 3406  F8F073  E0 00 40         ?chk:   cpx     #SIBUFSIZ       ; left room in input buffer?
 3407  F8F076  90 06                    bcc     ?str            ; yes, store received byte
 3408  F8F078  A9 C0                    lda     #$C0            ; set bit 7: rx error, bit 6: rx overflow
 3409  F8F07A  85 5F            ?sst:   sta     spstat+k        ; set status register
 3410  F8F07C  80 12                    bra     ?cnt            ; discard received data
 3411  F8F07E  E8               ?str:   inx                     ; now store received data
 3412  F8F07F  86 76                    stx     ibufcnt+k       ; update bytes count
 3413  F8F081  A6 66                    ldx     ibuftail+k      ; pointer to rx tail queue
 3414  F8F083  9F 00 40 05              sta     >SIBUFADDR,x
 3415  F8F087  E8                       inx                     ; update tail pointer
 3416  F8F088                           CPU16
 3417                                   .MLIST
 3418  F8F088  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 3419                                   .LONGA  on
 3420                                   .LONGI  on
 3421                                   .MNLIST
 3422  F8F08A  8A                       txa
 3423  F8F08B  29 FF 3F                 and     #(SIBUFSIZ-1)   ; circular queue
 3424  F8F08E  85 66                    sta     ibuftail+k
 3425  F8F090                   ?cnt:   CPU08                   ; continue...   
  Tue Jul 17 11:11:08 2018                                                                                               Page   15




 3426                                   .MLIST
 3427  F8F090  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 3428                                   .LONGA  off
 3429                                   .LONGI  off
 3430                                   .MNLIST
 3431  F8F092  A5 57            ?lin:   lda     spcsr+k         ; get control lines status 
 3432  F8F094  29 3B                    and     #00111011B      ; mask lines level
 3433  F8F096  89 08                    bit     #00001000B      ; check DSR line level
 3434  F8F098  F0 02                    beq     ?lin2           ; DSR is low
 3435  F8F09A  09 40                    ora     #01000000B      ; DSR is high
 3436  F8F09C  0A               ?lin2:  asl     a               ; 7:DSR, 6:CTS, 5:DCD, 2:DTR, 1:RTS
 3437  F8F09D  85 56                    sta     splin+k         ; save lines level
 3438                                   ;tya
 3439  F8F09F  24 5E                    bit     spmode+k        ; test for active handshake
 3440  F8F0A1  10 24                    bpl     ?cnt2           ; no handshake, so ignore CTS/DCD trans.
 3441  F8F0A3  50 22                    bvc     ?cnt2           ; softw. handshake, so ignore CTS/DCD trans.
 3442                                   ;bit    #00001000B      ; change state on DSR line?
 3443                                   ;beq    ?cts            ; no, go to check CTS line
 3444                                   ;ldx    #00100000B      ; remote disconnession flag
 3445                                   ;lda    #00001000B      ; check DSR line level
 3446                                   ;bit    spcsr+k
 3447                                   ;beq    ?dsrl           ; DSR line at low level
 3448                                   ;txa                    ; remote disconnession
 3449                                   ;tsb    spstat+k        ; set status register
 3450                                   ;bra    ?cts
 3451                           ;?dsrl: ;txa                    ; remote terminal ready
 3452                                   ;trb    spstat+k        ; set status register
 3453                           ;?cts:  
 3454  F8F0A5  A5 5E                    lda     spmode+k
 3455  F8F0A7  4A                       lsr     a               ; check if uplink handshake (RTS/DCD control)
 3456  F8F0A8  98                       tya                     ; A=interrupt status reg.
 3457  F8F0A9  B0 08                    bcs     ?dcd            ; yes, so check DCD line (uplink cable)
 3458  F8F0AB  89 20                    bit     #00100000B      ; change state on CTS line?
 3459  F8F0AD  F0 19                    beq     ?chkt           ; no, so check TDRE flag
 3460  F8F0AF  A9 20                    lda     #00100000B      ; check CTS line level
 3461  F8F0B1  80 06                    bra     ?lvl
 3462  F8F0B3  89 10            ?dcd:   bit     #00010000B      ; change state on DCD line?
 3463  F8F0B5  F0 11                    beq     ?chkt           ; no, so check TDRE flag
 3464  F8F0B7  A9 10                    lda     #00010000B      ; check DCD line level
 3465  F8F0B9  A2 40            ?lvl:   ldx     #$40            ; local pause flag      
 3466  F8F0BB  24 57                    bit     spcsr+k
 3467  F8F0BD  F0 05                    beq     ?clp            ; CTS (or DCD) = low so clear local pause
 3468  F8F0BF  8A                       txa                     ; CTS (or DCD) = high so set local pause
 3469  F8F0C0  04 60                    tsb     sppause+k
 3470  F8F0C2  80 03                    bra     ?cnt2
 3471  F8F0C4  8A               ?clp:   txa
 3472  F8F0C5  14 60                    trb     sppause+k
 3473  F8F0C7  98               ?cnt2:  tya
 3474  F8F0C8  0A               ?chkt:  asl     a               ; check TDRE bit
 3475  F8F0C9  10 11                    bpl     ?end            ; TDRE=0: can't transmit at this time
 3476  F8F0CB  A5 59                    lda     spout+k         ; pending an XON/XOFF sending?
 3477  F8F0CD  F0 13                    beq     ?cklp           ; no... check local pause flag
 3478  F8F0CF  8D 53 FD                 sta     .ABS.ACIATDR+k  ; send XON/XOFF
 3479  F8F0D2  64 59                    stz     spout+k         ; clear XON/XOFF flag   
 3480  F8F0D4  C9 13                    cmp     #SPXOFF
 3481  F8F0D6  F0 05                    beq     ?srp            ; sent an XOFF
 3482  F8F0D8  A9 80                    lda     #$80            ; sent an XON: clear remote pause flag  
  Tue Jul 17 11:11:08 2018                                                                                               Page   16




 3483  F8F0DA  14 60                    trb     sppause+k       ; bit 7 = 0 -> remote pause off
 3484  F8F0DC  60               ?end:   rts                     ; done
 3485  F8F0DD  A9 80            ?srp:   lda     #$80            ; set remote pause flag
 3486  F8F0DF  04 60                    tsb     sppause+k
 3487  F8F0E1  60                       rts
 3488  F8F0E2  24 60            ?cklp:  bit     sppause+k       ; local pause is set ?
 3489  F8F0E4  70 F6                    bvs     ?end            ; yes, no tx possible at this time
 3490                                   ;bit    spcsr+k         ; check if remote terminal is ready
 3491                                   ;bmi    ?end            ; not ready, skip tx    
 3492  F8F0E6                           INDEX16
 3493                                   .MLIST
 3494  F8F0E6  C2 10                    rep     #PXFLAG
 3495                                   .LONGI  on
 3496                                   .MNLIST
 3497  F8F0E8  A6 78                    ldx     obufcnt+k       ; count of bytes in output buffer
 3498  F8F0EA  F0 15                    beq     ?done           ; output buffer is empty: nothing to send
 3499  F8F0EC  CA                       dex                     ; update count 
 3500  F8F0ED  86 78                    stx     obufcnt+k
 3501  F8F0EF  A6 70                    ldx     obufhead+k      ; pointer to head of out buffer
 3502  F8F0F1  BF 00 00 05              lda     >SOBUFADDR,x    ; get data from output buffer
 3503  F8F0F5  8D 53 FD                 sta     .ABS.ACIATDR+k  ; send data
 3504  F8F0F8  E8                       inx                     ; update head pointer
 3505  F8F0F9                           CPU16
 3506                                   .MLIST
 3507  F8F0F9  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 3508                                   .LONGA  on
 3509                                   .LONGI  on
 3510                                   .MNLIST
 3511  F8F0FB  8A                       txa
 3512  F8F0FC  29 FF 1F                 and     #(SOBUFSIZ-1)   ; circular queue
 3513  F8F0FF  85 70                    sta     obufhead+k
 3514  F8F101                   ?done:  CPU08
 3515                                   .MLIST
 3516  F8F101  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 3517                                   .LONGA  off
 3518                                   .LONGI  off
 3519                                   .MNLIST
 3520  F8F103  60                       rts
 3521  F8F104                           .ENDM
 3522                           
 3523  F8F104                   int1sr: 
 3524  F8F104                           SPISR   1
 3525                           
 3526                                   .MLIST
 3527          [01]                     .IFZ    1
 3528                           k       .SET    0
 3529                           SOBUFADDR       .SET    SPOUTBUFF
 3530                           SIBUFADDR       .SET    SPINBUFF
 3531          [01]                     .ELSE
 3532          000004           k       .SET    4
 3533          052000           SOBUFADDR       .SET    SPOUTBUFF2
 3534          058000           SIBUFADDR       .SET    SPINBUFF2
 3535          [00]                     .ENDIF
 3536                           
 3537  F8F104  AC 54 FD                 ldy     .ABS.ACIAISR+k  ; interrupt status reg. (clear bit 3,4,5)
 3538  F8F107  AD 55 FD                 lda     .ABS.ACIACSR+k  ; control status register
 3539                                   ;sty    spisr+k         ; save interrupt status reg. 
  Tue Jul 17 11:11:08 2018                                                                                               Page   17




 3540  F8F10A  85 5B                    sta     spcsr+k         ; save control status reg.
 3541  F8F10C  98                       tya                     ; Y=status reg.
 3542  F8F10D  4A                       lsr     a               ; test RDRF bit
 3543  F8F10E  90 76                    bcc     ?lin            ; go to test control lines
 3544  F8F110  AE 57 FD                 ldx     .ABS.ACIARDR+k  ; fetch rx data (clear int. status bits 0,1,2)
 3545  F8F113  24 63                    bit     spstat+k        ; rx error pending?
 3546  F8F115  30 6F                    bmi     ?lin            ; yes, discard received data & test ctr. lines
 3547  F8F117  29 03                    and     #00000011B      ; 1: overrun/frame error, 2: parity error
 3548  F8F119  24 5B                    bit     spcsr+k         ; test control status reg. bit 7: FE
 3549  F8F11B  10 04                    bpl     ?nof            ; no framing error
 3550  F8F11D  09 04                    ora     #00000100B      ; set framing error bit...
 3551  F8F11F  29 FE                    and     #$FE            ; ...and clear overrun error
 3552  F8F121  C9 00            ?nof:   cmp     #0
 3553  F8F123  F0 04                    beq     ?rxok           ; no rx error
 3554  F8F125  09 80                    ora     #10000000B      ; set rx error bit
 3555  F8F127  80 45                    bra     ?sst            ; set stus reg. & discard received data
 3556  F8F129  8A               ?rxok:  txa                     ; A=received data       
 3557  F8F12A                           INDEX16
 3558                                   .MLIST
 3559  F8F12A  C2 10                    rep     #PXFLAG
 3560                                   .LONGI  on
 3561                                   .MNLIST
 3562  F8F12C  A6 7A                    ldx     ibufcnt+k       ; count of bytes stored in input buffer
 3563  F8F12E  24 62                    bit     spmode+k        ; test if handshake is active
 3564  F8F130  10 35                    bpl     ?chk            ; bit 7=0 -> no handshake so check input buff.
 3565  F8F132  70 14                    bvs     ?tst            ; bit 6=1 -> hardware handshake
 3566  F8F134  C9 11                    cmp     #SPXON          ; received an XON control byte?
 3567  F8F136  D0 06                    bne     ?xoff           ; no, check if received an XOFF
 3568  F8F138  A9 40                    lda     #$40            ; received an XON: clear local pause flag
 3569  F8F13A  14 64                    trb     sppause+k       ; bit 6=0 -> local pause off (resume tx)
 3570  F8F13C  80 46                    bra     ?cnt            ; discard received data
 3571  F8F13E  C9 13            ?xoff:  cmp     #SPXOFF         ; received an XOFF control byte?
 3572  F8F140  D0 06                    bne     ?tst            ; no, check condition for remote pause
 3573  F8F142  A9 40                    lda     #$40            ; set local pause flag
 3574  F8F144  04 64                    tsb     sppause+k       ; bit 6=1 -> local pause on (stop tx operation)
 3575  F8F146  80 3C                    bra     ?cnt            ; discard received data
 3576  F8F148  E4 84            ?tst:   cpx     icntmax+k       ; check input buff. for remote pause condition
 3577  F8F14A  90 26                    bcc     ?str            ; below guard limit: store data
 3578  F8F14C  24 64                    bit     sppause+k       ; remote pause is already on ?
 3579  F8F14E  30 17                    bmi     ?chk            ; yes, so check input buffer
 3580  F8F150  EB                       xba                     ; B = received data
 3581  F8F151  24 62                    bit     spmode+k        ; test handshake type
 3582  F8F153  70 06                    bvs     ?rtsh           ; bit 6=1 -> hardware handshake so set RTS=1
 3583  F8F155  A9 13                    lda     #SPXOFF         ; send an XOFF to remote terminal
 3584  F8F157  85 5D                    sta     spout+k         ; XOFF sending deffered until TDRE is set
 3585  F8F159  80 0B                    bra     ?xba            ; check input buffer            
 3586  F8F15B  A5 5C            ?rtsh:  lda     spfr+k          ; hardware handshake...
 3587  F8F15D  09 81                    ora     #10000001B      ; ...set RTS=1
 3588  F8F15F  8D 55 FD                 sta     .ABS.ACIAFR+k   ; update format register
 3589  F8F162  A9 80                    lda     #$80            ; set remote pause
 3590  F8F164  04 64                    tsb     sppause+k       ; bit 7=1 -> remote pause on
 3591  F8F166  EB               ?xba:   xba                     ; A = received data
 3592  F8F167  E0 00 40         ?chk:   cpx     #SIBUFSIZ       ; left room in input buffer?
 3593  F8F16A  90 06                    bcc     ?str            ; yes, store received byte
 3594  F8F16C  A9 C0                    lda     #$C0            ; set bit 7: rx error, bit 6: rx overflow
 3595  F8F16E  85 63            ?sst:   sta     spstat+k        ; set status register
 3596  F8F170  80 12                    bra     ?cnt            ; discard received data
  Tue Jul 17 11:11:08 2018                                                                                               Page   18




 3597  F8F172  E8               ?str:   inx                     ; now store received data
 3598  F8F173  86 7A                    stx     ibufcnt+k       ; update bytes count
 3599  F8F175  A6 6A                    ldx     ibuftail+k      ; pointer to rx tail queue
 3600  F8F177  9F 00 80 05              sta     >SIBUFADDR,x
 3601  F8F17B  E8                       inx                     ; update tail pointer
 3602  F8F17C                           CPU16
 3603                                   .MLIST
 3604  F8F17C  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 3605                                   .LONGA  on
 3606                                   .LONGI  on
 3607                                   .MNLIST
 3608  F8F17E  8A                       txa
 3609  F8F17F  29 FF 3F                 and     #(SIBUFSIZ-1)   ; circular queue
 3610  F8F182  85 6A                    sta     ibuftail+k
 3611  F8F184                   ?cnt:   CPU08                   ; continue...   
 3612                                   .MLIST
 3613  F8F184  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 3614                                   .LONGA  off
 3615                                   .LONGI  off
 3616                                   .MNLIST
 3617  F8F186  A5 5B            ?lin:   lda     spcsr+k         ; get control lines status 
 3618  F8F188  29 3B                    and     #00111011B      ; mask lines level
 3619  F8F18A  89 08                    bit     #00001000B      ; check DSR line level
 3620  F8F18C  F0 02                    beq     ?lin2           ; DSR is low
 3621  F8F18E  09 40                    ora     #01000000B      ; DSR is high
 3622  F8F190  0A               ?lin2:  asl     a               ; 7:DSR, 6:CTS, 5:DCD, 2:DTR, 1:RTS
 3623  F8F191  85 5A                    sta     splin+k         ; save lines level
 3624                                   ;tya
 3625  F8F193  24 62                    bit     spmode+k        ; test for active handshake
 3626  F8F195  10 24                    bpl     ?cnt2           ; no handshake, so ignore CTS/DCD trans.
 3627  F8F197  50 22                    bvc     ?cnt2           ; softw. handshake, so ignore CTS/DCD trans.
 3628                                   ;bit    #00001000B      ; change state on DSR line?
 3629                                   ;beq    ?cts            ; no, go to check CTS line
 3630                                   ;ldx    #00100000B      ; remote disconnession flag
 3631                                   ;lda    #00001000B      ; check DSR line level
 3632                                   ;bit    spcsr+k
 3633                                   ;beq    ?dsrl           ; DSR line at low level
 3634                                   ;txa                    ; remote disconnession
 3635                                   ;tsb    spstat+k        ; set status register
 3636                                   ;bra    ?cts
 3637                           ;?dsrl: ;txa                    ; remote terminal ready
 3638                                   ;trb    spstat+k        ; set status register
 3639                           ;?cts:  
 3640  F8F199  A5 62                    lda     spmode+k
 3641  F8F19B  4A                       lsr     a               ; check if uplink handshake (RTS/DCD control)
 3642  F8F19C  98                       tya                     ; A=interrupt status reg.
 3643  F8F19D  B0 08                    bcs     ?dcd            ; yes, so check DCD line (uplink cable)
 3644  F8F19F  89 20                    bit     #00100000B      ; change state on CTS line?
 3645  F8F1A1  F0 19                    beq     ?chkt           ; no, so check TDRE flag
 3646  F8F1A3  A9 20                    lda     #00100000B      ; check CTS line level
 3647  F8F1A5  80 06                    bra     ?lvl
 3648  F8F1A7  89 10            ?dcd:   bit     #00010000B      ; change state on DCD line?
 3649  F8F1A9  F0 11                    beq     ?chkt           ; no, so check TDRE flag
 3650  F8F1AB  A9 10                    lda     #00010000B      ; check DCD line level
 3651  F8F1AD  A2 40            ?lvl:   ldx     #$40            ; local pause flag      
 3652  F8F1AF  24 5B                    bit     spcsr+k
 3653  F8F1B1  F0 05                    beq     ?clp            ; CTS (or DCD) = low so clear local pause
  Tue Jul 17 11:11:08 2018                                                                                               Page   19




 3654  F8F1B3  8A                       txa                     ; CTS (or DCD) = high so set local pause
 3655  F8F1B4  04 64                    tsb     sppause+k
 3656  F8F1B6  80 03                    bra     ?cnt2
 3657  F8F1B8  8A               ?clp:   txa
 3658  F8F1B9  14 64                    trb     sppause+k
 3659  F8F1BB  98               ?cnt2:  tya
 3660  F8F1BC  0A               ?chkt:  asl     a               ; check TDRE bit
 3661  F8F1BD  10 11                    bpl     ?end            ; TDRE=0: can't transmit at this time
 3662  F8F1BF  A5 5D                    lda     spout+k         ; pending an XON/XOFF sending?
 3663  F8F1C1  F0 13                    beq     ?cklp           ; no... check local pause flag
 3664  F8F1C3  8D 57 FD                 sta     .ABS.ACIATDR+k  ; send XON/XOFF
 3665  F8F1C6  64 5D                    stz     spout+k         ; clear XON/XOFF flag   
 3666  F8F1C8  C9 13                    cmp     #SPXOFF
 3667  F8F1CA  F0 05                    beq     ?srp            ; sent an XOFF
 3668  F8F1CC  A9 80                    lda     #$80            ; sent an XON: clear remote pause flag  
 3669  F8F1CE  14 64                    trb     sppause+k       ; bit 7 = 0 -> remote pause off
 3670  F8F1D0  60               ?end:   rts                     ; done
 3671  F8F1D1  A9 80            ?srp:   lda     #$80            ; set remote pause flag
 3672  F8F1D3  04 64                    tsb     sppause+k
 3673  F8F1D5  60                       rts
 3674  F8F1D6  24 64            ?cklp:  bit     sppause+k       ; local pause is set ?
 3675  F8F1D8  70 F6                    bvs     ?end            ; yes, no tx possible at this time
 3676                                   ;bit    spcsr+k         ; check if remote terminal is ready
 3677                                   ;bmi    ?end            ; not ready, skip tx    
 3678  F8F1DA                           INDEX16
 3679                                   .MLIST
 3680  F8F1DA  C2 10                    rep     #PXFLAG
 3681                                   .LONGI  on
 3682                                   .MNLIST
 3683  F8F1DC  A6 7C                    ldx     obufcnt+k       ; count of bytes in output buffer
 3684  F8F1DE  F0 15                    beq     ?done           ; output buffer is empty: nothing to send
 3685  F8F1E0  CA                       dex                     ; update count 
 3686  F8F1E1  86 7C                    stx     obufcnt+k
 3687  F8F1E3  A6 74                    ldx     obufhead+k      ; pointer to head of out buffer
 3688  F8F1E5  BF 00 20 05              lda     >SOBUFADDR,x    ; get data from output buffer
 3689  F8F1E9  8D 57 FD                 sta     .ABS.ACIATDR+k  ; send data
 3690  F8F1EC  E8                       inx                     ; update head pointer
 3691  F8F1ED                           CPU16
 3692                                   .MLIST
 3693  F8F1ED  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 3694                                   .LONGA  on
 3695                                   .LONGI  on
 3696                                   .MNLIST
 3697  F8F1EF  8A                       txa
 3698  F8F1F0  29 FF 1F                 and     #(SOBUFSIZ-1)   ; circular queue
 3699  F8F1F3  85 74                    sta     obufhead+k
 3700  F8F1F5                   ?done:  CPU08
 3701                                   .MLIST
 3702  F8F1F5  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 3703                                   .LONGA  off
 3704                                   .LONGI  off
 3705                                   .MNLIST
 3706  F8F1F7  60                       rts
 3707  F8F1F8                           .ENDM
 3708                           
 3709  F8F1F8                           
 3710                           ; gestione IRQ2 - VIA 0 (T1, CA2, CB2, CA1)     
  Tue Jul 17 11:11:08 2018                                                                                               Page   20




 3711  F8F1F8                   int2sr:
 3712  F8F1F8  AC 0D FD                 ldy     VIA0+VIAIFR     ; flag IFR VIA
 3713  F8F1FB  10 48                    bpl     ?50             ; no irq da VIA
 3714  F8F1FD  98                       tya                     ; IFR
 3715  F8F1FE  0A                       asl     a               ; N = bit 6 (T1IFRB)
 3716  F8F1FF  10 1C                    bpl     ?20             ; no T1 IRQ
 3717                                   ;tay
 3718  F8F201                           ACC16                   ; A,M -> 16 bit
 3719                                   .MLIST
 3720  F8F201  C2 20                    rep     #PMFLAG
 3721                                   .LONGA  on
 3722                                   .MNLIST
 3723  F8F203  E6 00                    inc     JiffyClk        ; incrementa contatore clock 10ms
 3724  F8F205  D0 02                    bne     ?02
 3725  F8F207  E6 02                    inc     JiffyClk+2
 3726  F8F209                   ?02:    ACC08                   ; A,M -> 8 bit
 3727  F8F209  E2 20                    sep     #PMFLAG
 3728                                   .LONGA  off
 3729                                   .MNLIST
 3730  F8F20B  A2 03                    ldx     #SYSTMRCNT-1    ; System Timer (max. 2560ms)
 3731  F8F20D  34 08            ?04:    bit     SysTMF,x        ; timer attivo ?
 3732  F8F20F  10 06                    bpl     ?05             ; no
 3733  F8F211  D6 04                    dec     SysTmr,x        ; update timer x
 3734  F8F213  D0 02                    bne     ?05
 3735  F8F215  74 08                    stz     SysTMF,x        ; cancella timer
 3736  F8F217  CA               ?05:    dex
 3737  F8F218  10 F3                    bpl     ?04
 3738  F8F21A  AD 04 FD                 lda     VIA0+VIAT1CL    ; clear flag T1
 3739  F8F21D  98               ?20:    tya                     ; IFR
 3740  F8F21E  4A                       lsr     a               ; C  = CA2IFRB
 3741  F8F21F  90 0B                    bcc     ?30             ; no IRQ CA2 da controller tastiera
 3742  F8F221  20 46 F2                 jsr     KbInt           ; gestione IRQ tastiera 
 3743  F8F224  A9 01                    lda     #CA2IFRB        ; azzera flag CA2
 3744  F8F226  8D 0D FD                 sta     VIA0+VIAIFR
 3745  F8F229  8D 46 FD                 sta     KBCLRIRQ        ; azzera linea INT
 3746  F8F22C  98               ?30:    tya                     ; IFR
 3747  F8F22D  29 08                    and     #CB2IFRB        ; CB2-TMF0 abilitato ?
 3748  F8F22F  2D 0E FD                 and     VIA0+VIAIER     ;  e Timer motor spirato ?
 3749  F8F232  F0 11                    beq     ?40             ; no
 3750  F8F234  A9 10                    lda     #00010000B
 3751  F8F236  14 46                    trb     fdcctl          ; flag motor off
 3752  F8F238  A9 0C                    lda     #00001100B
 3753  F8F23A  8D DA FD                 sta     !FDCDOR         ; enable controller, motor off
 3754  F8F23D  A9 08                    lda     #CB2IFRB        ; disabilita CB2-TMF0
 3755  F8F23F  8D 0E FD                 sta     VIA0+VIAIER
 3756  F8F242  8D 0D FD                 sta     VIA0+VIAIFR     ; clear flag CB2
 3757  F8F245                   ?40:
 3758  F8F245  60               ?50:    rts
 3759  F8F246                           
 3760  F8F246                   KbInt:
 3761  F8F246  F4 00 01                 pea     #DP01ADDR       ; DP = pagina 1
 3762  F8F249  2B                       pld
 3763  F8F24A  AE 40 FD                 ldx     KBFR            ; primo byte (flag)
 3764  F8F24D  10 2E                    bpl     ?20             ; bit 7 = 0 -> codice ASCII
 3765  F8F24F  8A                       txa
 3766  F8F250  29 B0                    and     #$B0            ; maschera 4 bit alti - ignora release (6)
 3767  F8F252  C9 80                    cmp     #$80            ; codice FLAG ?
  Tue Jul 17 11:11:08 2018                                                                                               Page   21




 3768  F8F254  D0 10                    bne     ?10             ; no
 3769  F8F256  8A                       txa
 3770  F8F257  29 03                    and     #$03            ; bit 7 e 6 di KbdShift
 3771  F8F259  4A                       lsr     a               ; C = bit 6
 3772  F8F25A  6A                       ror     a               ; C = bit 7
 3773  F8F25B  6A                       ror     a
 3774  F8F25C  29 C0                    and     #$C0            ; maschera bit 7,6
 3775  F8F25E  85 63                    sta     KbdShift
 3776  F8F260  AD 41 FD                 lda     KBFR+1          ; flag
 3777  F8F263  85 64                    sta     KbdFlag
 3778  F8F265  60                       rts
 3779  F8F266  C9 90            ?10:    cmp     #$90            ; toggle bit ?
 3780  F8F268  D0 13                    bne     ?20             ; no
 3781  F8F26A  AD 41 FD                 lda     KBFR+1          ; toggle bit
 3782  F8F26D  85 65                    sta     KbdToggle
 3783  F8F26F  29 20                    and     #SCROLLLOCKB    ; test SCROLL LOCK BIT
 3784  F8F271  08                       php
 3785  F8F272  A9 80                    lda     #$80            ; SCOLL LOCK bit di ScnScroll
 3786  F8F274  28                       plp
 3787  F8F275  F0 03                    beq     ?12
 3788  F8F277  04 75                    tsb     ScnScroll       ; disabilita scroll
 3789  F8F279  60                       rts
 3790  F8F27A  14 75            ?12:    trb     ScnScroll       ; abilita scroll
 3791  F8F27C  60                       rts
 3792  F8F27D  A4 62            ?20:    ldy     KbdCnt          ; test spazio nel buffer
 3793  F8F27F  C0 60                    cpy     #KBDBUFLEN
 3794  F8F281  B0 28                    bcs     ?90             ; no room - scarta tasto
 3795  F8F283  8A                       txa
 3796  F8F284  89 10                    bit     #$10            ; test 4 bit bassi toggle
 3797  F8F286  F0 0A                    beq     ?30             ; no toggle
 3798  F8F288  A9 0F                    lda     #$0F            ; azzera 4 bit bassi di KbdToggle
 3799  F8F28A  14 65                    trb     KbdToggle
 3800  F8F28C  8A                       txa 
 3801  F8F28D  29 0F                    and     #$0F            ; 4 bit bassi di KbdToggle
 3802  F8F28F  04 65                    tsb     KbdToggle       ; imposta 4 bit bassi di KbdToggle
 3803  F8F291  8A                       txa
 3804                           ?30:                            ; inserisce codice tasto nel buffer
 3805  F8F292  29 C0                    and     #$C0            ; bit 7 -> ASCII(0) oppure CONTROL(1)
 3806                                                           ; bit 6 -> MAKE(0) oppure RELEASE(1)
 3807  F8F294  A6 60                    ldx     KbdITail        ; indice coda buffer
 3808  F8F296  95 00                    sta     KbdBuf,x        ; inserisce flag tasto
 3809  F8F298  E8                       inx
 3810  F8F299  AD 41 FD                 lda     KBFR+1          ; codice tasto
 3811  F8F29C  95 00                    sta     KbdBuf,x
 3812  F8F29E  E8                       inx
 3813  F8F29F  C8                       iny                     ; aggiorna contatore bytes
 3814  F8F2A0  C8                       iny
 3815  F8F2A1  84 62                    sty     KbdCnt
 3816  F8F2A3  E0 60                    cpx     #KBDBUFLEN      ; test coda piena
 3817  F8F2A5  90 02                    bcc     ?40             ; no
 3818  F8F2A7  A2 00                    ldx     #0              ; coda circolare
 3819  F8F2A9  86 60            ?40:    stx     KbdITail        ; aggiorna ptr. coda buffer
 3820  F8F2AB  60               ?90:    rts
 3821                           
 3822                           
 3823                           ; ISR for VIA2/VIA3
 3824                           ; VIA3
  Tue Jul 17 11:11:08 2018                                                                                               Page   22




 3825                           ; CB2 (neg. edge) : ch375/376 interrupt line
 3826                           ;
 3827                           ; VIA2
 3828                           ; CA1 (negative edge) : interrupt from pic usb host
 3829                           ; CA2 (negative edge) : interrupt from UM245R (usb slave)
 3830                           ; CB1
 3831                           ; CB2 (pos/neg. edge) : acia CTS sensing
 3832                           ; T1 free-run interrupt
 3833  F8F2AC                   int3sr:
 3834                                   .EXTERN usbdskon, umgetcmd
 3835                           
 3836  F8F2AC  AD CD FD                 lda     !VIA3+VIAIFR
 3837  F8F2AF  10 25                    bpl     ?via2
 3838  F8F2B1  8D CD FD                 sta     !VIA3+VIAIFR    ; clear interrupt flags
 3839  F8F2B4  89 08                    bit     #CB2IFRB
 3840  F8F2B6  F0 1E                    beq     ?via2           ; no usb interrupt
 3841  F8F2B8  A9 22                    lda     #CMD_GET_STATUS
 3842  F8F2BA  8D D1 FD                 sta     usb0cmd
 3843  F8F2BD  EA                       nop                     ; 2uS
 3844  F8F2BE  EA                       nop
 3845  F8F2BF  EA                       nop
 3846  F8F2C0  EA                       nop
 3847  F8F2C1  AD D0 FD                 lda     usb0dat
 3848  F8F2C4  C9 16                    cmp     #USB_INT_DISCONNECT
 3849  F8F2C6  D0 06                    bne     ?nxt
 3850  F8F2C8  A9 7F                    lda     #$7F            ; clear all status bits but not bit 7
 3851  F8F2CA  14 43                    trb     usb0st
 3852  F8F2CC  80 08                    bra     ?via2           ; check via2
 3853  F8F2CE  C9 15            ?nxt:   cmp     #USB_INT_CONNECT
 3854  F8F2D0  D0 04                    bne     ?via2
 3855  F8F2D2  22 53 B2 F8              jsl     usbdskon        
 3856  F8F2D6  F4 00 05         ?via2:  pea     #DP05ADDR
 3857  F8F2D9  2B                       pld
 3858  F8F2DA  AD 1D FC                 lda     !VIA2+VIAIFR
 3859  F8F2DD  30 01                    bmi     ?go
 3860  F8F2DF  60                       rts                     ; no interrupt from VIA3
 3861  F8F2E0  2D 1E FC         ?go:    and     !VIA2+VIAIER    ; mask off disbled flags
 3862  F8F2E3  4A                       lsr     a               ; <0>: CA2 int. ?
 3863  F8F2E4  90 4B                    bcc     ?ca1            ; no, test bit <1>
 3864  F8F2E6                           
 3865                                   ; /RXF line from UM245R request service 
 3866                                   ; if UM245 is already plugged to usb host then have data on FIFO
 3867                                   ; if UM245 was previously unplugged then it assert some pulses
 3868                                   ; on /RXF line with dummy data: FF, 1D, 3D, 3D or FF, 3D, 3D
 3869                                   ; last two bytes must be 3D 3D
 3870                                   ;
 3871  F8F2E6  A8                       tay                     ; save flags
 3872  F8F2E7  A2 01                    ldx     #CA2IFRB        ; clear CA2 flag
 3873  F8F2E9  8E 1D FC                 stx     .ABS.VIA2+VIAIFR
 3874  F8F2EC  24 00                    bit     usbslv          ; UM245 already plugged to usb host?
 3875  F8F2EE  30 11                    bmi     ?umrx           ; yes so this is incoming data
 3876  F8F2F0                           
 3877                                   ; sensing a plug in
 3878                                   ;
 3879  F8F2F0  AE 2F FC                 ldx     .ABS.UM245R     ; read UM245 port and discard data
 3880  F8F2F3  24 00                    bit     usbslv          ; first transition?
 3881  F8F2F5  70 3A                    bvs     ?ca1            ; no
  Tue Jul 17 11:11:08 2018                                                                                               Page   23




 3882  F8F2F7  A2 40                    ldx     #$40            ; set usb host pending plug-in flag
 3883  F8F2F9  86 00                    stx     usbslv
 3884  F8F2FB  A2 28                    ldx     #40             ; 600ms timeout
 3885  F8F2FD  86 02                    stx     usbcnt1
 3886                                   ;tya                    ; restore flags
 3887  F8F2FF  80 30                    bra     ?ca1            ; go to test CA1 flag
 3888                           
 3889                           ?umrx:  ; /RXF line low mean data is available from UM245 FIFO
 3890                                   ; expect 8 bytes
 3891  F8F301  A2 00                    ldx     #0
 3892  F8F303  A9 01            ?umrxl: lda     #CA2IFRB        ; clear CA2 flag
 3893  F8F305  8D 1D FC                 sta     !VIA2+VIAIFR
 3894  F8F308  AD 2F FC                 lda     !UM245R
 3895  F8F30B  95 03                    sta     usbbuf,x
 3896  F8F30D  E8                       inx
 3897  F8F30E  E0 08                    cpx     #8
 3898  F8F310  B0 1A                    bcs     ?umrx3
 3899  F8F312  9C 18 FC                 stz     VIA2+VIAT2CL
 3900  F8F315  9C 19 FC                 stz     VIA2+VIAT2CH
 3901  F8F318  A9 01            ?umrx2: lda     #CA2IFRB        ; check CA2 flag
 3902  F8F31A  2C 1D FC                 bit     VIA2+VIAIFR
 3903  F8F31D  D0 E4                    bne     ?umrxl
 3904  F8F31F  A9 20                    lda     #T2IFRB
 3905  F8F321  2C 1D FC                 bit     VIA2+VIAIFR
 3906  F8F324  F0 F2                    beq     ?umrx2
 3907  F8F326  A9 40                    lda     #$40
 3908  F8F328  14 01                    trb     usbum
 3909  F8F32A  80 04                    bra     ?ca1r
 3910                           
 3911                           ;?umrx3:        bit     usbum
 3912                           ;       bmi     ?setu           ; already connected
 3913  F8F32C                           
 3914                                   ; check connession request
 3915                           ;       dex
 3916                           ;?umrx4:        lda     usbbuf,x
 3917                           ;       cmp     .ABS.?usbt,x
 3918                           ;       beq     ?umrx5
 3919                           ;       lda     #$55
 3920                           ;       sta     !UM245R
 3921                           ;       bra     ?ca1r
 3922                           ;?umrx5: dex
 3923                           ;       bpl     ?umrx4
 3924                           ;       lda     #$AA
 3925                           ;       sta     !UM245R
 3926                           ;       lda     #$80
 3927                           ;       tsb     usbum
 3928                           ;       bra     ?ca1r
 3929                           ;?setu: lda     #$40
 3930                           
 3931  F8F32C  A9 40            ?umrx3: lda     #$40
 3932  F8F32E  04 01                    tsb     usbum           ; set bit <6>: fifo data available
 3933  F8F330  98               ?ca1r:  tya                     ; restore flag
 3934  F8F331                           
 3935  F8F331  4A               ?ca1:   lsr     a               ; <1>: CA1 int.?
 3936  F8F332  90 0B                    bcc     ?cb2            ; no, test bit <3>
 3937  F8F334                           
 3938                                   ; this is pic that request a service (usb host)
  Tue Jul 17 11:11:08 2018                                                                                               Page   24




 3939                                   ;
 3940  F8F334  A8                       tay                     ; save flags
 3941  F8F335  A9 02                    lda     #CA1IFRB        ; clear CA1 flag
 3942  F8F337  8D 1D FC                 sta     !VIA2+VIAIFR
 3943  F8F33A  A9 80                    lda     #$80
 3944  F8F33C  04 0D                    tsb     usbmst          ; set usb master flag request
 3945  F8F33E  98                       tya                     ; restore flag
 3946  F8F33F                           
 3947  F8F33F  4A               ?cb2:   lsr     a               ; discard bit <2>
 3948  F8F340  4A                       lsr     a               ; <3>: CB2 int.?
 3949  F8F341  90 36                    bcc     ?cb1            ; no, test bit <4>
 3950                           
 3951                                   ; /CTS line of R65C51 changed state (transition)
 3952                                   ;
 3953  F8F343  A8                       tay                     ; save flags
 3954  F8F344  A9 08                    lda     #CB2IFRB        ; clear CB2 flag
 3955  F8F346  8D 1D FC                 sta     !VIA2+VIAIFR
 3956  F8F349  A9 01                    lda     #$01
 3957  F8F34B  04 16                    tsb     splin3          ; transition on /CST line
 3958  F8F34D  A2 40                    ldx     #$40
 3959  F8F34F  A9 08                    lda     #00001000B      ; check /CTS line level: PA<3>
 3960  F8F351  2C 1F FC                 bit     !VIA2+VIAPRANH
 3961  F8F354  F0 0A                    beq     ?ctsl           ; was a negative transition: /CTS is low
 3962                           
 3963                                   ; positive edge transition on /CTS line: /CTS line is high
 3964                                   ;
 3965  F8F356  8A                       txa
 3966  F8F357  1C 1C FC                 trb     !VIA2+VIAPCR    ; next time sense a negative edge on /CTS line
 3967  F8F35A  A9 80                    lda     #$80
 3968  F8F35C  04 16                    tsb     splin3          ; now /CTS line is high
 3969  F8F35E  80 09                    bra     ?hsk            ; check handshake mode for R65C51 (CF=1 here)
 3970  F8F360                           
 3971                           ?ctsl:  ; negative edge transition on /CTS line: /CTS line is low
 3972                                   ;
 3973  F8F360  8A                       txa
 3974  F8F361  0C 1C FC                 tsb     !VIA2+VIAPCR    ; next time sense a positive edge on /CTS line
 3975  F8F364  A9 80                    lda     #$80
 3976  F8F366  14 16                    trb     splin3          ; now /CTS line is low
 3977  F8F368  18                       clc                     ; CF=0: resume TX
 3978                           
 3979                           ?hsk:   ; if 65C51 is in hardware handshake mode then must handle
 3980                                   ; local pause flag and TX interrupt state
 3981                                   ;
 3982  F8F369  24 15                    bit     spmode3         ; test for active handshake
 3983  F8F36B  10 0B                    bpl     ?cnt            ; no handshake, so ignore CTS trans.
 3984  F8F36D  50 09                    bvc     ?cnt            ; softw. handshake, so ignore CTS trans.
 3985  F8F36F  8A                       txa
 3986  F8F370  90 04                    bcc     ?clp            ; /CTS low clear local pause and resume TX
 3987  F8F372  04 17                    tsb     sppause3        ; /CTS high set local pause and stop TX
 3988  F8F374  80 02                    bra     ?cnt
 3989  F8F376  14 17            ?clp:   trb     sppause3        
 3990  F8F378  98               ?cnt:   tya                     ; restore flag
 3991                           
 3992  F8F379  4A               ?cb1:   lsr     a               ; <4>: CB1 int.?
 3993  F8F37A  90 03                    bcc     ?t1             ; no, test bit <6>
 3994  F8F37C  AE 10 FC                 ldx     .ABS.VIA2+VIAPRB
 3995  F8F37F                           
  Tue Jul 17 11:11:08 2018                                                                                               Page   25




 3996  F8F37F  4A               ?t1:    lsr     a               ; discadrd bit <5>
 3997  F8F380  4A                       lsr     a               ; <6>: T1 int.?
 3998  F8F381  90 47                    bcc     ?end            ; no
 3999                           
 4000                                   ; T1 used for check UM245 /TXE line: if this line is high
 4001                                   ; for long time this mean that usb host was unplugged,
 4002                                   ; and used for check /DSR line when ACIA interrupt is disabled
 4003                                   ; T1 timeout = 15ms
 4004  F8F383  AD 14 FC                 lda     !VIA2+VIAT1CL   ; clear T1 flag
 4005  F8F386  24 00                    bit     usbslv          ; plug-in pending?
 4006  F8F388  50 08                    bvc     ?t2             ; no
 4007  F8F38A  C6 02                    dec     usbcnt1         ; update counter
 4008  F8F38C  D0 04                    bne     ?t2             ; timeout not expired
 4009  F8F38E  A9 80                    lda     #$80
 4010  F8F390  85 00                    sta     usbslv          ; assume UM245 plugged-in
 4011  F8F392  AD 2A FC         ?t2:    lda     !ACIACMD
 4012  F8F395  4A                       lsr     a               ; check bit <0>
 4013  F8F396  B0 0F                    bcs     ?usb            ; ACIA interrupt is enabled
 4014  F8F398  AD 29 FC                 lda     !ACIASR         ; is safe to read ACIA status now
 4015  F8F39B  29 40                    and     #01000000B      ; mask off all bits but /DSR
 4016  F8F39D  F0 04                    beq     ?dsr            ; clear /DSR flag
 4017  F8F39F  04 16                    tsb     splin3          ; set /DSR flag
 4018  F8F3A1  80 04                    bra     ?usb
 4019  F8F3A3  A9 40            ?dsr:   lda     #$40
 4020  F8F3A5  14 16                    trb     splin3  
 4021  F8F3A7  24 00            ?usb:   bit     usbslv
 4022  F8F3A9  10 15                    bpl     ?txel           ; usb unplugged: nothing to do
 4023  F8F3AB  2C 1F FC                 bit     !VIA2+VIAPRANH  ; check /TXE
 4024  F8F3AE  50 10                    bvc     ?txel           ; /TXE is low: clear timeout
 4025  F8F3B0  A5 0B                    lda     usbtim          ; timeout started?
 4026  F8F3B2  D0 06                    bne     ?dec            ; yes, update counter
 4027  F8F3B4  A9 2C                    lda     #44             ; set 660ms (44 x 15) timeout
 4028  F8F3B6  85 0B                    sta     usbtim
 4029  F8F3B8  80 10                    bra     ?end
 4030  F8F3BA  C6 0B            ?dec:   dec     usbtim          ; update counter
 4031  F8F3BC  D0 0C                    bne     ?end            ; no timeout
 4032  F8F3BE  64 00                    stz     usbslv          ; assume cable unplugged
 4033  F8F3C0  64 0B            ?txel:  stz     usbtim          ; clear any pending timeout     
 4034  F8F3C2                           
 4035                           ;?umrx: ldx     usbcnt
 4036                           ;?lp1:  lda     !VIA2+VIAPRA    ; check /RXF line
 4037                           ;       cmp     !VIA2+VIAPRA
 4038                           ;       bne     ?lp1
 4039                           ;       tay
 4040                           ;       asl     a
 4041                           ;       bcs     ?xx
 4042                           ;       lda     !UM245R         ; read um245 port
 4043                           ;       sta     !$8000,x
 4044                           ;       tya
 4045                           ;       sta     !$8100,x
 4046                           ;       inx
 4047                           ;?xx:   stx     usbcnt
 4048                           
 4049  F8F3C2  24 01                    bit     usbum
 4050  F8F3C4  50 04                    bvc     ?end
 4051  F8F3C6  22 5E 0E F8              jsl     umgetcmd
 4052  F8F3CA                   ?end:
  Tue Jul 17 11:11:08 2018                                                                                               Page   26




 4053  F8F3CA  60                       rts
 4054                           
 4055  F8F3CB  87 E9 5D 93 B7   ?usbt:  .DB     $87, $E9, $5D, $93, $B7, $57, $7D, $3B
               57 7D 3B 
 4056                           
 4057                           ; serial test board interrupt from 16C550 & 65C51
 4058  F8F3D3                   int4sr:
 4059  F8F3D3  F4 00 05                 pea     #DP05ADDR
 4060  F8F3D6  2B                       pld
 4061  F8F3D7  AD 29 FC                 lda     !ACIASR
 4062  F8F3DA  30 03                    bmi     ?acia
 4063  F8F3DC  4C B8 F4                 jmp     uartisr         ; 16C550 interrupt?
 4064  F8F3DF  89 08            ?acia:  bit     #ACIARDRF       ; rx data?
 4065  F8F3E1  F0 6F                    beq     ?lin            ; no, check lines
 4066  F8F3E3  A8                       tay                     ; Y = status
 4067  F8F3E4  AE 28 FC                 ldx     .ABS.ACIADR     ; X = received data
 4068  F8F3E7  29 07                    and     #00000111B      ; any rx error pending?
 4069  F8F3E9  F0 0B                    beq     ?rx             ; no
 4070  F8F3EB  0A                       asl     a               ; translate overrun (bit 3) to bit 0
 4071  F8F3EC  89 08                    bit     #00001000B      ; test overrun
 4072  F8F3EE  F0 02                    beq     $+4             ; skip next instruction if not overrun
 4073  F8F3F0  09 01                    ora     #$01            ; overrun bit (bit<0>)
 4074  F8F3F2  09 80                    ora     #$80            ; set x error bit
 4075  F8F3F4  80 43                    bra     ?sst            ; set status reg. & discard received data
 4076  F8F3F6  8A               ?rx:    txa                     ; A = received data
 4077  F8F3F7                           INDEX16
 4078  F8F3F7  C2 10                    rep     #PXFLAG
 4079                                   .LONGI  on
 4080                                   .MNLIST
 4081  F8F3F9  A6 23                    ldx     ibufcnt3        ; count of bytes stored in input queue
 4082  F8F3FB  24 15                    bit     spmode3         ; test for active handshake
 4083  F8F3FD  10 33                    bpl     ?chk            ; no handshake: goto to check input queue
 4084  F8F3FF  70 14                    bvs     ?tst            ; hardware handshake (check queue overflow)
 4085  F8F401  C9 11                    cmp     #SPXON          ; received an XON control byte?
 4086  F8F403  D0 06                    bne     ?xoff           ; no, check if received an XOFF
 4087  F8F405  A9 40                    lda     #$40            ; clear local pause flag
 4088  F8F407  14 17                    trb     sppause3        ; bit<6> = 0 -> local pause off (resume tx)
 4089  F8F409  80 44                    bra     ?cnt            ; discard received data
 4090  F8F40B  C9 13            ?xoff:  cmp     #SPXOFF         ; received an XOFF control byte?
 4091  F8F40D  D0 06                    bne     ?tst            ; no, so check queue overflow
 4092  F8F40F  A9 40                    lda     #$40            ; set local pause flag
 4093  F8F411  04 17                    tsb     sppause3        ; bit<6> = 1 -> local pause on (stop tx)
 4094  F8F413  80 3A                    bra     ?cnt            ; discard received data
 4095  F8F415  E4 29            ?tst:   cpx     icntmax3        ; check input buff. for remote pause condition
 4096  F8F417  90 24                    bcc     ?sto            ; below guard limit: store data
 4097  F8F419  24 17                    bit     sppause3        ; remote pause is already on ?
 4098  F8F41B  30 15                    bmi     ?chk            ; yes, so check input buffer
 4099  F8F41D  EB                       xba                     ; B = received data
 4100  F8F41E  24 15                    bit     spmode3         ; test handshake type
 4101  F8F420  70 06                    bvs     ?rtsh           ; bit 6=1 -> hardware handshake so set RTS=1
 4102  F8F422  A9 13                    lda     #SPXOFF         ; send an XOFF to remote terminal
 4103  F8F424  85 18                    sta     spout3          ; XOFF sending deffered until TDRE is set
 4104  F8F426  80 09                    bra     ?xba            ; check input buffer            
 4105  F8F428  A9 04            ?rtsh:  lda     #$04            ; hardware handshake...
 4106  F8F42A  0C 1F FC                 tsb     !VIA2+VIAPRANH  ; ...set RTS=1
 4107  F8F42D  A9 80                    lda     #$80            ; set remote pause
 4108  F8F42F  04 17                    tsb     sppause3        ; bit 7=1 -> remote pause on
  Tue Jul 17 11:11:08 2018                                                                                               Page   27




 4109  F8F431  EB               ?xba:   xba                     ; A = received data
 4110  F8F432  E0 00 10         ?chk:   cpx     #SIBUFSIZ3      ; left room in input buffer?
 4111  F8F435  90 06                    bcc     ?sto            ; yes, store received byte
 4112  F8F437  A9 C0                    lda     #$C0            ; set bit 7: rx error, bit 6: rx overflow
 4113  F8F439  85 19            ?sst:   sta     spstat3         ; set status register
 4114  F8F43B  80 12                    bra     ?cnt            ; discard received data
 4115  F8F43D  E8               ?sto:   inx                     ; now store received data
 4116  F8F43E  86 23                    stx     ibufcnt3        ; update bytes count
 4117  F8F440  A6 1B                    ldx     ibuftail3       ; pointer to rx tail queue
 4118  F8F442  9F 00 D0 05              sta     >SIBUFADDR3,x
 4119  F8F446  E8                       inx                     ; update tail pointer
 4120  F8F447                           CPU16
 4121  F8F447  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 4122                                   .LONGA  on
 4123                                   .LONGI  on
 4124                                   .MNLIST
 4125                                   .MLIST
 4126  F8F449  8A                       txa
 4127  F8F44A  29 FF 0F                 and     #(SIBUFSIZ3-1)  ; circular queue
 4128  F8F44D  85 1B                    sta     ibuftail3
 4129  F8F44F                   ?cnt:   CPU08                   ; continue...   
 4130                                   .MLIST
 4131  F8F44F  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 4132                                   .LONGA  off
 4133                                   .LONGI  off
 4134                                   .MNLIST
 4135  F8F451  98                       tya                     ; A = acia status
 4136  F8F452  A8               ?lin:   tay     
 4137  F8F453  29 40                    and     #01000000B      ; mask off all bits but /DSR
 4138  F8F455  F0 04                    beq     ?dsr            ; clear /DSR flag
 4139  F8F457  04 16                    tsb     splin3          ; set /DSR flag
 4140  F8F459  80 04                    bra     ?cnt2
 4141  F8F45B  A9 40            ?dsr:   lda     #$40
 4142  F8F45D  14 16                    trb     splin3  
 4143  F8F45F  98               ?cnt2:  tya     
 4144  F8F460  89 10                    bit     #ACIATDRE       ; TX reg. empty?
 4145  F8F462  F0 23                    beq     ?end            ; no
 4146  F8F464  A6 18                    ldx     spout3          ; pending an XON/XOFF sending?
 4147  F8F466  F0 23                    beq     ?cklp           ; no... check local pause flag
 4148  F8F468                           
 4149                                   ; if send an XON then we will re-enable tx interrupt
 4150                                   ; else we will disable tx interrupt
 4151                                   ;
 4152  F8F468  A9 0C                    lda     #00001100B      ; disable tx for now (is safe)
 4153  F8F46A  1C 2A FC                 trb     !ACIACMD
 4154  F8F46D  E0 11                    cpx     #SPXON
 4155  F8F46F  D0 04                    bne     ?di
 4156  F8F471  A9 04                    lda     #00000100B      ; re-enable tx interrupt
 4157  F8F473  80 02                    bra     ?cmd
 4158  F8F475  A9 08            ?di:    lda     #00001000B      ; disable tx interrupt
 4159  F8F477  0C 2A FC         ?cmd:   tsb     !ACIACMD
 4160  F8F47A  8E 28 FC                 stx     .ABS.ACIADR     ; send XON/XOFF
 4161  F8F47D  64 18                    stz     spout3          ; clear XON/XOFF flag   
 4162  F8F47F  A9 80                    lda     #$80            ; remote pause flag
 4163  F8F481  E0 13                    cpx     #SPXOFF
 4164  F8F483  F0 03                    beq     ?srp            ; sent an XOFF: set remote pause flag           
 4165  F8F485  14 17                    trb     sppause3        ; sent an XON: clear remote pause flag
  Tue Jul 17 11:11:08 2018                                                                                               Page   28




 4166  F8F487  60               ?end:   rts                     ; done
 4167  F8F488  04 17            ?srp:   tsb     sppause3        ; set remote pause flag
 4168  F8F48A  60                       rts
 4169  F8F48B  24 17            ?cklp:  bit     sppause3        ; local pause is set ?
 4170  F8F48D  70 06                    bvs     ?off            ; yes, no tx possible at this time
 4171  F8F48F                           INDEX16
 4172  F8F48F  C2 10                    rep     #PXFLAG
 4173                                   .LONGI  on
 4174                                   .MNLIST
 4175  F8F491  A6 25                    ldx     obufcnt3        ; count of bytes in output buffer
 4176  F8F493  D0 0C                    bne     ?snd            ; output buffer inot empty: send next byte
 4177  F8F495  A9 0C            ?off:   lda     #00001100B      ; disable TX interrupt for avoid cont. int.
 4178  F8F497  1C 2A FC                 trb     !ACIACMD
 4179  F8F49A  A9 08                    lda     #00001000B
 4180  F8F49C  0C 2A FC                 tsb     !ACIACMD
 4181  F8F49F  80 15                    bra     ?done
 4182  F8F4A1  CA               ?snd:   dex                     ; update count 
 4183  F8F4A2  86 25                    stx     obufcnt3
 4184  F8F4A4  A6 21                    ldx     obufhead3       ; pointer to head of out buffer
 4185  F8F4A6  BF 00 C0 05              lda     >SOBUFADDR3,x   ; get data from output buffer
 4186  F8F4AA  8D 28 FC                 sta     .ABS.ACIADR     ; send data
 4187  F8F4AD  E8                       inx                     ; update head pointer
 4188  F8F4AE                           CPU16
 4189  F8F4AE  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 4190                                   .LONGA  on
 4191                                   .LONGI  on
 4192                                   .MNLIST
 4193  F8F4B0  8A                       txa
 4194  F8F4B1  29 FF 0F                 and     #(SOBUFSIZ3-1)  ; circular queue
 4195  F8F4B4  85 21                    sta     obufhead3
 4196  F8F4B6                   ?done:  CPU08
 4197  F8F4B6  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 4198                                   .LONGA  off
 4199                                   .LONGI  off
 4200                                   .MNLIST
 4201                                   ;rts
 4202                           
 4203                           ; 16C550 interrupt
 4204                           ; ISR routine (prologue and epilogue code for context switching not showed here)
 4205                           ; handle 16C550 interrupt
 4206                           ; WARNING: assume DBR = 0 and DP saved by interrupt handler prologue code       
 4207  F8F4B8                   uartisr:
 4208  F8F4B8  AD 22 FC                 lda     !UART_IIR
 4209  F8F4BB  85 43                    sta     uartiir         ; save for late check FIFO enabled
 4210  F8F4BD  4A                       lsr     a               ; if bit <0> = 1 no interrupt
 4211  F8F4BE  90 01                    bcc     $+3             ; interrupt pending
 4212  F8F4C0  60                       rts
 4213  F8F4C1  29 03                    and     #0000011B       ; mask on priority code
 4214  F8F4C3  0A                       asl     a
 4215  F8F4C4  AA                       tax
 4216                           ;       ldy     #40
 4217                           ;?00:   dey
 4218                           ;       bne     ?00
 4219                                   ; RX timeout interrupt and RX data available interrupt use the same routine
 4220  F8F4C5  7C C8 F4                 jmp     (?uarttbl,x)    ; jump to right routine
 4221                           
 4222  F8F4C8                   ?uarttbl:
  Tue Jul 17 11:11:08 2018                                                                                               Page   29




 4223  F8F4C8  D5F4 DAF4 DFF4           .DW     ?msr, ?tx, ?rx, ?lsr
               D0F4 
 4224                           
 4225  F8F4D0  20 5A F5         ?lsr:   jsr     uartilsr
 4226                                   ;rts
 4227  F8F4D3  80 E3                    bra     uartisr         ; check again interrupt (was a test)
 4228  F8F4D5                           
 4229  F8F4D5  20 E4 F4         ?msr:   jsr     uartmsr         ; MSR: modem status register
 4230                                   ;rts
 4231  F8F4D8  80 DE                    bra     uartisr         ; check again iterrupt
 4232  F8F4DA                           
 4233  F8F4DA  20 15 F5         ?tx:    jsr     uarttx          ; TX FIFO or THR is empty
 4234                                   ;rts
 4235  F8F4DD  80 D9                    bra     uartisr         ; check again interrupt
 4236                           
 4237  F8F4DF  20 7A F5         ?rx:    jsr     uartrx          ; data available in RX FIFO or RHR
 4238                                   ;rts
 4239  F8F4E2  80 D4                    bra     uartisr         ; check again interrupt
 4240                           
 4241                           ; this interrupt is raised when one of the modem lines change state
 4242                           ; here just DSR and CTS are used: DSR for signaling remote disconnession,
 4243                           ; CTS for hardware handshake (put local TX in pause)
 4244  F8F4E4                   uartmsr:
 4245  F8F4E4  AD 26 FC                 lda     !UART_MSR       ; clear interrupt
 4246  F8F4E7  AA                       tax
 4247  F8F4E8  0A                       asl     a
 4248  F8F4E9  0A                       asl     a               ; <7>: /DSR, <6>: /CTS
 4249  F8F4EA  49 C0                    eor     #$C0
 4250  F8F4EC  85 2C                    sta     splin4          ; update line status
 4251  F8F4EE  24 2B                    bit     spmode4
 4252  F8F4F0  10 22                    bpl     ?end            ; no handshake: ignore line changes
 4253  F8F4F2  A8                       tay
 4254  F8F4F3  10 04                    bpl     ?cts            ; /DSR is low, check /CTS
 4255  F8F4F5  A9 A0                    lda     #$A0            ; /DSR is high
 4256  F8F4F7  04 2F                    tsb     spstat4         ; remote terminal disconnected
 4257  F8F4F9  8A               ?cts:   txa
 4258  F8F4FA  4A                       lsr     a               ; check /CTS transition
 4259  F8F4FB  90 17                    bcc     ?end            ; no /CTS transition
 4260  F8F4FD  A2 40                    ldx     #$40            ; local pause flag
 4261  F8F4FF  98                       tya
 4262  F8F500  0A                       asl     a
 4263  F8F501  10 09                    bpl     ?clp            ; transition /CTS high->low: clear local pause
 4264  F8F503  8A                       txa
 4265  F8F504  04 2D                    tsb     sppause4        ; /CTS high -> set local pause
 4266  F8F506  A9 02                    lda     #00000010B      ; disable TX interrupt
 4267  F8F508  1C 21 FC                 trb     !UART_IER
 4268  F8F50B  60                       rts
 4269  F8F50C  8A               ?clp:   txa
 4270  F8F50D  14 2D                    trb     sppause4        ; /CTS low -> clear local pause
 4271  F8F50F  A9 02                    lda     #00000010B      ; enable TX interrupt
 4272  F8F511  0C 21 FC                 tsb     !UART_IER
 4273  F8F514  60               ?end:   rts
 4274                           
 4275                           ; this interrupt is raised either when THR is empty
 4276                           ; or when TX FIFO is empty
 4277  F8F515                   uarttx:
 4278  F8F515  A9 02                    lda     #00000010B      ; disable TX interrupt
  Tue Jul 17 11:11:08 2018                                                                                               Page   30




 4279  F8F517  1C 21 FC                 trb     !UART_IER
 4280  F8F51A  24 2D                    bit     sppause4        ; local pause is set ?
 4281  F8F51C  70 39                    bvs     ?done           ; yes, no tx possible at this time
 4282  F8F51E                           INDEX16
 4283  F8F51E  C2 10                    rep     #PXFLAG
 4284                                   .LONGI  on
 4285                                   .MNLIST
 4286  F8F520  A4 3B                    ldy     obufcnt4        ; count of bytes in output buffer
 4287  F8F522  F0 33                    beq     ?done           ; nothing to send at this time
 4288  F8F524  A6 35                    ldx     obuftail4       ; pointer to tail of out buffer
 4289                                   ;lda    spcnt4          ; set the bytes count
 4290  F8F526  A9 10                    lda     #16             ; set the bytes count
 4291  F8F528  85 30                    sta     sptmp4
 4292  F8F52A  BF 00 00 06      ?txl:   lda     >SOBUFADDR4,x   ; get data from the tail of output buffer
 4293  F8F52E  8D 27 FC                 sta     !UART_SCP
 4294  F8F531  EA                       nop
 4295  F8F532  EA                       nop
 4296  F8F533  EA                       nop
 4297  F8F534  EA                       nop
 4298  F8F535  8D 27 FC                 sta     !UART_SCP       
 4299  F8F538  EA                       nop
 4300  F8F539  EA                       nop
 4301  F8F53A  EA                       nop
 4302  F8F53B  EA                       nop
 4303  F8F53C  EA                       nop
 4304  F8F53D  EA                       nop
 4305  F8F53E  8F 20 FC 00              sta     >UART_RXTX      ; load data into FIFO/THR
 4306  F8F542  E8                       inx                     ; update head pointer
 4307  F8F543                           ACC16
 4308  F8F543  C2 20                    rep     #PMFLAG
 4309                                   .LONGA  on
 4310                                   .MNLIST
 4311  F8F545  8A                       txa
 4312  F8F546  29 FF 7F                 and     #(SOBUFSIZ4-1)  ; circular queue
 4313  F8F549  AA                       tax
 4314  F8F54A                           ACC08
 4315  F8F54A  E2 20                    sep     #PMFLAG
 4316                                   .LONGA  off
 4317                                   .MNLIST
 4318  F8F54C  88                       dey                     ; update count
 4319  F8F54D  F0 04                    beq     ?upd            ; nothing else to send
 4320  F8F54F  C6 30                    dec     sptmp4
 4321  F8F551  D0 D7                    bne     ?txl            ; loop: load more bytes if FIFO enabled
 4322  F8F553  86 35            ?upd:   stx     obuftail4
 4323  F8F555  84 3B                    sty     obufcnt4
 4324  F8F557                   ?done:  CPU08                   ; NOTE: tx interrupt will be re-enabled by put routine
 4325  F8F557  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 4326                                   .LONGA  off
 4327                                   .LONGI  off
 4328                                   .MNLIST
 4329  F8F559  60                       rts                     ; or by a negative /CTS transition 
 4330                           
 4331                           ; this interrupt is raised when receive a byte with some errors
 4332  F8F55A                   uartilsr:
 4333  F8F55A  A9 05                    lda     #00000101B      ; disable LSR & RX interrupt
 4334  F8F55C  1C 21 FC                 trb     UART_IER
 4335  F8F55F  AD 25 FC                 lda     !UART_LSR       ; get line status and clear interrupt
  Tue Jul 17 11:11:08 2018                                                                                               Page   31




 4336  F8F562  85 42                    sta     uartlsr         ; save for further debugging
 4337  F8F564  4A                       lsr     a               ; CF = 1 if available a new rx byte
 4338  F8F565  29 0F                    and     #$0F            ; mask on rx errors
 4339                                   ;beq    uartrx1
 4340  F8F567  09 80                    ora     #$80            ; set rx error bit
 4341  F8F569  85 2F                    sta     spstat4         ; set status register
 4342  F8F56B  90 0C                    bcc     ?done           ; no new char received
 4343  F8F56D  AD 20 FC                 lda     !UART_RXTX      ; get top fifo data or THR & discard
 4344  F8F570  24 43                    bit     uartiir
 4345  F8F572  50 05                    bvc     ?done           ; no FIFO enabled
 4346  F8F574  A9 83                    lda     #10000011B      ; clear RX FIFO
 4347  F8F576  8D 22 FC                 sta     !UART_FCR
 4348  F8F579  60               ?done:  rts                     ; after rx error, rx interrupt are disabled
 4349                           
 4350                           ; this interrupt is raised either when RHR is full or when RX FIFO reach the
 4351                           ; programmed trigger level (in this case 8)
 4352  F8F57A                   uartrx:
 4353  F8F57A  EA                       nop
 4354  F8F57B  EA                       nop
 4355  F8F57C  EA                       nop
 4356  F8F57D  EA                       nop
 4357  F8F57E                           INDEX16
 4358  F8F57E  C2 10                    rep     #PXFLAG
 4359                                   .LONGI  on
 4360                                   .MNLIST
 4361  F8F580  A4 39                    ldy     ibufcnt4        ; count of bytes in input buffer
 4362  F8F582  A6 33                    ldx     ibufhead4       ; pointer to head of input buffer
 4363  F8F584  AD 20 FC         ?loop:  lda     !UART_RXTX      ; get top fifo data or THR
 4364  F8F587  C4 3F                    cpy     icntmax4        ; check input buff. for remote pause condition
 4365  F8F589  90 14                    bcc     ?str            ; below guard limit: store data
 4366  F8F58B  EB                       xba                     ; B = received data
 4367  F8F58C  A9 02                    lda     #00000010B      ; hardware handshake...
 4368  F8F58E  1C 24 FC                 trb     !UART_MCR       ; ...set RTS=1
 4369  F8F591  A9 80                    lda     #$80            ; set remote pause flag
 4370  F8F593  04 2D                    tsb     sppause4        ; bit 7=1 -> remote pause on
 4371  F8F595  EB                       xba                     ; A = received data
 4372  F8F596  C0 00 80         ?chk:   cpy     #SIBUFSIZ4      ; left room in input buffer?
 4373  F8F599  90 04                    bcc     ?str            ; yes, store received byte
 4374  F8F59B  A9 C0                    lda     #$C0            ; set bit 7: rx error, bit 6: rx overrun
 4375  F8F59D  80 21                    bra     ?sst            ; discard received data & exit
 4376  F8F59F  9F 00 80 06      ?str:   sta     >SIBUFADDR4,x   ; now store received data
 4377  F8F5A3  C8                       iny                     ; update bytes count
 4378  F8F5A4  E8                       inx                     ; update rx head pointer
 4379  F8F5A5                           ACC16
 4380  F8F5A5  C2 20                    rep     #PMFLAG
 4381                                   .LONGA  on
 4382                                   .MNLIST
 4383  F8F5A7  8A                       txa
 4384  F8F5A8  29 FF 7F                 and     #(SIBUFSIZ4-1)  ; circular queue
 4385  F8F5AB  AA                       tax
 4386  F8F5AC                           ACC08
 4387  F8F5AC  E2 20                    sep     #PMFLAG
 4388                                   .LONGA  off
 4389                                   .MNLIST
 4390  F8F5AE  24 43                    bit     uartiir
 4391  F8F5B0  50 10                    bvc     ?done
 4392  F8F5B2  AD 25 FC                 lda     !UART_LSR       ; get line status
  Tue Jul 17 11:11:08 2018                                                                                               Page   32




 4393  F8F5B5  85 42                    sta     uartlsr
 4394  F8F5B7  4A                       lsr     a               ; CF = 1 if available a new rx byte
 4395  F8F5B8  29 0F                    and     #$0F            ; mask on rx errors
 4396  F8F5BA  90 06                    bcc     ?done           ; no data available, re-enable rx int. & exit
 4397  F8F5BC  F0 C6                    beq     ?loop
 4398  F8F5BE  09 80                    ora     #$80
 4399  F8F5C0  85 2F            ?sst:   sta     spstat4
 4400  F8F5C2  86 33            ?done:  stx     ibufhead4       ; save rx head pointer
 4401  F8F5C4  84 39                    sty     ibufcnt4        ; save bytes count
 4402  F8F5C6                           INDEX08
 4403  F8F5C6  E2 10                    sep     #PXFLAG
 4404                                   .LONGI  off
 4405                                   .MNLIST
 4406  F8F5C8  60                       rts
 4407                           
 4408                           .COMMENT @
 4409                           uartrx:
 4410                                   ;lda    #$01            ; disable RX interrupt
 4411                                   ;trb    UART_IER
 4412                                   INDEX16
 4413                                   ldy     ibufcnt4        ; count of bytes in input buffer
 4414                                   ldx     ibufhead4       ; pointer to head of input buffer
 4415                           rxloop: lda     !UART_LSR       ; get line status
 4416                                   sta     uartlsr
 4417                                   lsr     a               ; CF = 1 if available a new rx byte
 4418                                   and     #$0F            ; mask on rx errors
 4419                           uartrx1:
 4420                                   bcc     ?done           ; no data available, re-enable rx int. & exit
 4421                                   xba                     ; save error code
 4422                                   
 4423                                   nop
 4424                                   nop
 4425                                   nop
 4426                                   nop
 4427                                   
 4428                                   lda     !UART_RXTX      ; get top fifo data or THR
 4429                                   xba
 4430                           ?tst:   beq     ?rx             ; no rx error pending
 4431                                   ora     #$80            ; set rx error bit
 4432                                   bra     ?sst            ; set status reg. & discard received data
 4433                           ?rx:    xba                     ; A = received data
 4434                                   cpy     icntmax4        ; check input buff. for remote pause condition
 4435                                   bcc     ?str            ; below guard limit: store data
 4436                                   xba                     ; B = received data
 4437                                   lda     #00000010B      ; hardware handshake...
 4438                                   trb     !UART_MCR       ; ...set RTS=1
 4439                                   lda     #$80            ; set remote pause flag
 4440                                   tsb     sppause4        ; bit 7=1 -> remote pause on
 4441                                   xba                     ; A = received data
 4442                           ?chk:   cpy     #SIBUFSIZ4      ; left room in input buffer?
 4443                                   bcc     ?str            ; yes, store received byte
 4444                                   lda     #$C0            ; set bit 7: rx error, bit 6: rx overrun
 4445                           ?sst:   sta     spstat4         ; set status register
 4446                                   bra     ?done           ; discard received data & exit
 4447                           ?str:   sta     >SIBUFADDR4,x   ; now store received data
 4448                                   iny                     ; update bytes count
 4449                                   inx                     ; update rx head pointer
  Tue Jul 17 11:11:08 2018                                                                                               Page   33




 4450                                   ACC16
 4451                                   txa
 4452                                   and     #(SIBUFSIZ4-1)  ; circular queue
 4453                                   tax
 4454                                   ACC08
 4455                                   bra     rxloop          ; check again if rx data available
 4456                           ?done:  stx     ibufhead4       ; save rx head pointer
 4457                                   sty     ibufcnt4        ; save bytes count
 4458                           ?done1: INDEX08
 4459                                   ;lda    #$01            ; re-enable rx interrupt
 4460                                   ;tsb    UART_IER
 4461                                   rts
 4462                           @
 4463                           
 4464                           .COMMENT @
 4465                           uart:
 4466                                   lda     !UART_IIR
 4467                                   sta     uartiir
 4468                                   lsr     a               ; if <0> = 1 no interrupt
 4469                                   bcc     $+3             ; interrupt pending
 4470                                   rts
 4471                                   and     #0000011B       ; mask on priority code
 4472                                   asl     a
 4473                                   tax
 4474                                   jmp     (?uarttbl,x)
 4475                           
 4476                           ?uarttbl:
 4477                                   .DW     ?msr, ?tx, ?rx, ?lsr
 4478                           
 4479                           
 4480                                   ; int. 3: line status register (LSR)
 4481                                   ;
 4482                           ?lsr:   ;jsr    uartrx
 4483                                   lda     !UART_LSR       ; read LSR and clear interrupt
 4484                                   sta     uartlsr
 4485                                   ;rts
 4486                                   bra     uart            ; check again interrupt
 4487                                   
 4488                           ?msr:   jsr     uartmsr         ; MSR: modem status register
 4489                                   ;rts
 4490                                   bra     uart            ; check again iterrupt
 4491                                   
 4492                           ?tx:    jsr     uarttx          ; TX FIFO is empty
 4493                                   ;rts
 4494                                   bra     uart            ; check again interrupt
 4495                           
 4496                           ?rx:    jsr     uartrx          ; data available in RX FIFO
 4497                                   ;rts
 4498                                   bra     uart            ; check again interrupt
 4499                           
 4500                           
 4501                           uartmsr:
 4502                                   lda     !UART_MSR
 4503                                   tax
 4504                                   asl     a
 4505                                   asl     a               ; <7>: /DSR, <6>: /CTS
 4506                                   eor     #$C0
  Tue Jul 17 11:11:08 2018                                                                                               Page   34




 4507                                   sta     splin4          ; update line status
 4508                                   tay
 4509                                   bit     spmode4
 4510                                   bpl     ?end            ; no handshake
 4511                                   bvc     ?end            ; software handshake: no /CTS and /DSR check    
 4512                                   tya
 4513                                   bpl     ?cts            ; /DSR is low
 4514                                   lda     #$A0
 4515                                   tsb     spstat4         ; remote terminal disconnected
 4516                           ?cts:   bvc     ?end            ; handshake software: no check /CTS
 4517                                   txa
 4518                                   lsr     a               ; check /CTS transition
 4519                                   bcc     ?end            ; no /CTS transition
 4520                                   ldx     #$40            ; local pause flag
 4521                                   tya
 4522                                   asl     a
 4523                                   bpl     ?clp            ; transition high->low
 4524                                   txa
 4525                                   tsb     sppause4        ; /CTS high set local pause
 4526                                   rts
 4527                           ?clp:   txa
 4528                                   trb     sppause4        ; /CTS low clear local pause
 4529                           ?end:   rts
 4530                           
 4531                           uarttx:
 4532                                   ;;lda   !UART_IIR
 4533                           
 4534                                   lda     !UART_LSR
 4535                                   and     #$40
 4536                                   ;;cmp   #$60
 4537                                   bne     ?cklp
 4538                                   lda     !UART_IIR
 4539                                   rts
 4540                                   ;lda    #$20
 4541                                   ;bit    !UART_LSR
 4542                                   ;bne    ?cklp
 4543                                   ;rts
 4544                                   
 4545                                   bra     ?cklp
 4546                                   ldx     spout4          ; pending an XON/XOFF sending?
 4547                                   beq     ?cklp           ; no... check local pause flag
 4548                                   
 4549                                   ; if send an XON then we will re-enable tx interrupt
 4550                                   ; else we will disable tx interrupt
 4551                                   ;
 4552                                   lda     #00000010B      ; IER<1>: tx interrupt
 4553                                   cpx     #SPXON
 4554                                   bne     ?di
 4555                                   tsb     !UART_IER       ; enable tx interrupt
 4556                                   bra     ?htx1
 4557                           ?di:    trb     !UART_IER       ; disable tx interrupt
 4558                           ?htx1:  stx     .ABS.UART_RXTX  ; send XON/XOFF
 4559                                   stz     spout4          ; clear XON/XOFF flag
 4560                                   lda     #$80            ; remote pause flag
 4561                                   cpx     #SPXOFF
 4562                                   beq     ?srp            ; sent an XOFF: set remote pause flag           
 4563                                   trb     sppause4        ; sent an XON: clear remote pause flag
  Tue Jul 17 11:11:08 2018                                                                                               Page   35




 4564                                   rts                     ; done
 4565                           ?srp:   tsb     sppause4        ; set remote pause flag
 4566                                   rts
 4567                           ?cklp:  bit     sppause4        ; local pause is set ?
 4568                                   bvs     ?off            ; yes, no tx possible at this time
 4569                                   INDEX16
 4570                                   ldx     obufhead4       ; pointer to head of out buffer
 4571                                   ldy     obufcnt4        ; count of bytes in output buffer
 4572                                   bne     ?snd            ; output buffer is not empty
 4573                           ?off:   lda     #00000010B      ; disable TX interrupt for avoid cont. int.
 4574                                   trb     !UART_IER
 4575                                   bra     ?done
 4576                           ?snd:   
 4577                                   lda     #00000010B      ; disable TX interrupt for avoid cont. int.
 4578                                   trb     !UART_IER
 4579                                   
 4580                                   lda     #1              ; fill fifo
 4581                                   sta     spout4
 4582                                   lda     #$20
 4583                                   bit     spmode4
 4584                                   bne     ?txl
 4585                                   lda     #1
 4586                                   sta     spout4
 4587                           ?txl:
 4588                                   lda     >SOBUFADDR4,x   ; get data from output buffer
 4589                                   sta     !UART_RXTX      ; send data to FIFO
 4590                                   inx                     ; update head pointer
 4591                                   ACC16
 4592                                   txa
 4593                                   and     #(SOBUFSIZ4-1)  ; circular queue
 4594                                   tax
 4595                                   ACC08
 4596                                   dey
 4597                                   beq     ?upd
 4598                                   dec     spout4
 4599                                   bne     ?txl
 4600                           ?upd:   stz     spout4
 4601                                   stx     obufhead4
 4602                                   sty     obufcnt4
 4603                           ?done:  CPU08
 4604                                   lda     !UART_IIR
 4605                                   rts
 4606                           
 4607                           uartrx:
 4608                                   ;lda    spstat4
 4609                                   ;bmi    ?rts
 4610                           
 4611                                   lda     #$01
 4612                                   trb     UART_IER
 4613                                   INDEX16
 4614                                   ldy     ibufcnt4
 4615                                   ldx     ibuftail4
 4616                           ?lp1:   lda     !UART_LSR
 4617                                   sta     uartlsr
 4618                                   lsr     a
 4619                                   bcc     ?done
 4620                                   
  Tue Jul 17 11:11:08 2018                                                                                               Page   36




 4621                                   ;bcs    ?loop
 4622                                   ;and    #$0F
 4623                                   ;beq    ?done1
 4624                                   ;ora    #$80            ; set rx error bit
 4625                                   ;sta    spstat4
 4626                                   ;bra    ?done1
 4627                           
 4628                           ?loop:  and     #$0F            ; mask on errors        
 4629                                   xba
 4630                                   lda     !UART_RXTX      ; get top fifo data
 4631                                   xba
 4632                                   beq     ?rx             ; no rx error pending
 4633                                   ora     #$80            ; set rx error bit
 4634                                   bra     ?sst            ; set status reg. & discard received data
 4635                           ?rx:    xba                     ; A = received data
 4636                                   bit     spmode4         ; test for active handshake
 4637                                   bpl     ?chk            ; no handshake: goto to check input queue
 4638                                   bvs     ?tst            ; hardware handshake (check queue overflow)
 4639                                   cmp     #SPXON          ; received an XON control byte?
 4640                                   bne     ?xoff           ; no, check if received an XOFF
 4641                                   lda     #$40            ; clear local pause flag
 4642                                   trb     sppause4        ; bit<6> = 0 -> local pause off (resume tx)
 4643                                   bra     ?cnt            ; discard received data
 4644                           ?xoff:  cmp     #SPXOFF         ; received an XOFF control byte?
 4645                                   bne     ?tst            ; no, so check queue overflow
 4646                                   lda     #$40            ; set local pause flag
 4647                                   tsb     sppause4        ; bit<6> = 1 -> local pause on (will stop tx)
 4648                                   bra     ?cnt            ; discard received data
 4649                           ?tst:   cpy     icntmax4        ; check input buff. for remote pause condition
 4650                                   bcc     ?str            ; below guard limit: store data
 4651                                   bit     sppause4        ; remote pause is already on ?
 4652                                   bmi     ?chk            ; yes, so check input buffer
 4653                                   xba                     ; B = received data
 4654                                   bit     spmode4         ; test handshake type
 4655                                   bvs     ?rtsh           ; bit 6=1 -> hardware handshake so set RTS=1
 4656                                   lda     #SPXOFF         ; send an XOFF to remote terminal
 4657                                   sta     spout4          ; XOFF sending deffered until THR is empty
 4658                                   lda     #00000010B      ; IER<1>: tx interrupt
 4659                                   tsb     !UART_IER       ; enable tx interrupt
 4660                                   bra     ?xba            ; check input buffer            
 4661                           ?rtsh:  lda     #00000010B      ; hardware handshake...
 4662                                   trb     !UART_MCR       ; ...set RTS=1
 4663                                   lda     #$80            ; set remote pause
 4664                                   tsb     sppause4        ; bit 7=1 -> remote pause on
 4665                           ?xba:   xba                     ; A = received data
 4666                           ?chk:   cpy     #SIBUFSIZ4      ; left room in input buffer?
 4667                                   bcc     ?str            ; yes, store received byte
 4668                                   lda     #$C0            ; set bit 7: rx error, bit 6: rx overflow
 4669                           ?sst:   sta     spstat4         ; set status register
 4670                                   bra     ?done           ; discard received data & exit
 4671                           ?str:   sta     >SIBUFADDR4,x   ; now store received data
 4672                                   iny                     ; update bytes count
 4673                                   inx                     ; update rx tail pointer
 4674                                   ACC16
 4675                                   txa
 4676                                   and     #(SIBUFSIZ4-1)  ; circular queue
 4677                                   tax
  Tue Jul 17 11:11:08 2018                                                                                               Page   37




 4678                                   ACC08
 4679                           ?cnt:   ;lda    !UART_LSR       ; any rx data pending?
 4680                                   ;sta    uartlsr
 4681                                   ;lsr    a
 4682                                   ;bcs    ?loop           ; yes, get again from top fifo
 4683                                   bra     ?lp1
 4684                           ?done:  stx     ibuftail4       ; save rx tail pointer
 4685                                   sty     ibufcnt4        ; save bytes count
 4686                           ?done1: INDEX08
 4687                           ?rts:   
 4688                                   lda     #$01
 4689                                   tsb     UART_IER
 4690                                   rts
 4691                           @
 4692                           
 4693  F8F5C9                   int5sr:
 4694  F8F5C9                   int6sr:
 4695  F8F5C9  60                       rts
 4696                           
 4697                           ; INT from RTC
 4698  F8F5CA                   int7sr:
 4699  F8F5CA  A2 0A                    ldx     #RTCCTRLA       ; setta banco 1 RTC
 4700  F8F5CC  8E 4C FD                 stx     RTCALE
 4701  F8F5CF  AD 4D FD                 lda     RTCDATA         ; salva flag banco
 4702  F8F5D2  48                       pha
 4703  F8F5D3  09 10                    ora     #$10            ; setta banco 1
 4704  F8F5D5  8D 4D FD                 sta     RTCDATA
 4705  F8F5D8  A2 4E                    ldx     #RTCSMI2        ; recupera eventuale ALE
 4706  F8F5DA  8E 4C FD                 stx     RTCALE
 4707  F8F5DD  AD 4D FD                 lda     RTCDATA
 4708  F8F5E0  48                       pha                     ; ALE da ripristinare
 4709  F8F5E1  A2 0C                    ldx     #RTCSTATUS
 4710  F8F5E3  8E 4C FD                 stx     RTCALE
 4711  F8F5E6  AD 4D FD                 lda     RTCDATA         ; azzera flag
 4712  F8F5E9  30 03                    bmi     ?01
 4713  F8F5EB  4C 74 F6                 jmp     ?20             ; NO IRQ da RTC
 4714  F8F5EE  89 20            ?01:    bit     #$20            ; flag AF (alarm)
 4715  F8F5F0  F0 5E                    beq     ?10             ; no alarm
 4716  F8F5F2  A2 4A                    ldx     #RTCEXTCTRLA    ; check INCR bit 6
 4717  F8F5F4  8E 4C FD                 stx     RTCALE
 4718  F8F5F7  2C 4D FD         ?02:    bit     RTCDATA
 4719  F8F5FA  70 FB                    bvs     ?02
 4720  F8F5FC  A2 06                    ldx     #RTCDAY         ; day of week
 4721  F8F5FE  8E 4C FD                 stx     RTCALE
 4722  F8F601  AD 4D FD                 lda     RTCDATA
 4723  F8F604  C9 01                    cmp     #1              ; sunday?
 4724  F8F606  D0 48                    bne     ?10             ; no
 4725  F8F608  E8                       inx
 4726  F8F609  8E 4C FD                 stx     RTCALE
 4727  F8F60C  AD 4D FD                 lda     RTCDATA         ; day of month (date)
 4728  F8F60F  C9 19                    cmp     #25             ; last sunday of month?
 4729  F8F611  90 3D                    bcc     ?10             ; no
 4730  F8F613  E8                       inx
 4731  F8F614  8E 4C FD                 stx     RTCALE          ; month
 4732  F8F617  AD 4D FD                 lda     RTCDATA
 4733  F8F61A  C9 03                    cmp     #3              ; march?
 4734  F8F61C  D0 12                    bne     ?04             ; no
  Tue Jul 17 11:11:08 2018                                                                                               Page   38




 4735  F8F61E  A2 04                    ldx     #RTCHOURS       ; increment hours
 4736  F8F620  8E 4C FD                 stx     RTCALE
 4737  F8F623  EE 4D FD                 inc     RTCDATA
 4738  F8F626  A2 0F                    ldx     #RTCRAM0F
 4739  F8F628  8E 4C FD                 stx     RTCALE
 4740  F8F62B  9C 4D FD                 stz     RTCDATA         ; reset flag for next time      
 4741  F8F62E  80 20                    bra     ?10
 4742  F8F630  C9 0A            ?04:    cmp     #10             ; october?
 4743  F8F632  D0 1C                    bne     ?10             ; no
 4744  F8F634  A2 0F                    ldx     #RTCRAM0F
 4745  F8F636  8E 4C FD                 stx     RTCALE
 4746  F8F639  AD 4D FD                 lda     RTCDATA         ; already updated?
 4747  F8F63C  10 05                    bpl     ?06             ; no
 4748  F8F63E  9C 4D FD                 stz     RTCDATA         ; yes...so reset flag
 4749  F8F641  80 0D                    bra     ?10
 4750  F8F643  A9 FF            ?06:    lda     #$FF
 4751  F8F645  8D 4D FD                 sta     RTCDATA         ; set updated flag
 4752  F8F648  A2 04                    ldx     #RTCHOURS       ; decrement hours
 4753  F8F64A  8E 4C FD                 stx     RTCALE
 4754  F8F64D  CE 4D FD                 dec     RTCDATA
 4755  F8F650  A2 4A            ?10:    ldx     #RTCEXTCTRLA    ; check others interrupt's
 4756  F8F652  8E 4C FD                 stx     RTCALE
 4757  F8F655  AD 4D FD                 lda     RTCDATA
 4758  F8F658  89 01                    bit     #$01            ; KF ?
 4759  F8F65A  08                       php     
 4760  F8F65B  A9 07                    lda     #$07            ; cancella altri IRQ
 4761  F8F65D  1C 4D FD                 trb     RTCDATA
 4762  F8F660  28                       plp
 4763  F8F661  F0 11                    beq     ?20             ; NO KF
 4764  F8F663  A9 01                    lda     #$01            ; TEST KS START
 4765  F8F665  24 0D                    bit     RTCFlag
 4766  F8F667  D0 04                    bne     ?11             ; KS OFF
 4767  F8F669  04 0D                    tsb     RTCFlag         ; segnala KS OFF
 4768  F8F66B  80 07                    bra     ?20
 4769  F8F66D  A9 08            ?11:    lda     #$08            ; PAB = 1, PWR OFF
 4770                                   ;tsb    RTCDATA
 4771  F8F66F  1C 4D FD                 trb     RTCDATA
 4772  F8F672  A9 01                    lda     #$01            ; CLEAR KS START
 4773                                   ;trb    SysRTC          
 4774  F8F674  7A               ?20:    ply                     ; ALE da ripristinare
 4775  F8F675  A2 0A                    ldx     #RTCCTRLA       ; setta banco originale RTC
 4776  F8F677  8E 4C FD                 stx     RTCALE
 4777  F8F67A  68                       pla                     ; banco originale
 4778  F8F67B  8D 4D FD                 sta     RTCDATA         ; salva flag banco
 4779  F8F67E  8C 4C FD                 sty     RTCALE          ; ripristina ALE
 4780  F8F681  60                       rts
 4781  F8F682                           
 4782                           
 4783                                   .CODE
 4784                           
 4785                                   .EXTERN SysStart
 4786                                   .GLOBAL intsr
 4787                           
 4788                           ;
 4789                           ;       FWE     XFE     R/W     BANK $F0
 4790                           ;       0        X       X       RAM
 4791                           ;       1       0        X       FLASH
  Tue Jul 17 11:11:08 2018                                                                                               Page   39




 4792                           ;       1       1       1       EEROM8U
 4793                           ;       1       1       0        RAM
 4794                           ;
 4795                           ; codice di startup
 4796  F8FE00                   _RSTEntry:
 4797                           
 4798                                   ; at start: XFE=0, FWE=0, HIM=0
 4799  F8FE00  78                       sei
 4800  F8FE01  D8                       cld
 4801                                   ;sta    !CRHIMOFF       ; forza start da flash
 4802  F8FE02  18                       clc
 4803  F8FE03  FB                       xce                     ; CPU in modo nativo
 4804  F8FE04  A0 00                    ldy     #0
 4805  F8FE06                           CPU16
 4806  F8FE06  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 4807                                   .LONGA  on
 4808                                   .LONGI  on
 4809                                   .MNLIST
 4810  F8FE08  A2 FF DF                 ldx     #STACK_ADDR     ; init stack
 4811  F8FE0B  9A                       txs
 4812  F8FE0C  98                       tya                     ; DP = 0 (page 0)
 4813  F8FE0D  5B                       tcd
 4814  F8FE0E  BB                       tyx
 4815  F8FE0F                           CPU08
 4816  F8FE0F  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 4817                                   .LONGA  off
 4818                                   .LONGI  off
 4819                                   .MNLIST
 4820  F8FE11  4B                       phk
 4821  F8FE12  AB                       plb                     ; DBR = PBR = 0
 4822                           
 4823  F8FE13  AD 00 FC                 lda     !CRBIT0         ; test boot
 4824  F8FE16  F0 46                    beq     ?09             ; firmware from FLASH
 4825                           
 4826                                   ; check EEROM emulator board
 4827  F8FE18  8C 62 FC         ?00:    sty     .ABS.VIA4+VIADDRB
 4828  F8FE1B  CC 62 FC                 cpy     .ABS.VIA4+VIADDRB
 4829  F8FE1E  D0 3E                    bne     ?09             ; fail -- goto old way
 4830  F8FE20  C8                       iny
 4831  F8FE21  D0 F5                    bne     ?00
 4832  F8FE23                           
 4833                                   ; ok, seem present
 4834  F8FE23  88                       dey
 4835  F8FE24  8C 62 FC                 sty     .ABS.VIA4+VIADDRB       ; port B out
 4836                           
 4837                                   ; transfer emulator data to $F0 bank
 4838  F8FE27  A9 F0                    lda     #$F0
 4839  F8FE29  85 02                    sta     <2
 4840  F8FE2B  64 00                    stz     <0
 4841  F8FE2D  64 01                    stz     <1
 4842  F8FE2F  9C 60 FC                 stz     !VIA4+VIAPRB
 4843  F8FE32  8D 0D FC                 sta     !CREMEON
 4844  F8FE35                           INDEX16
 4845  F8FE35  C2 10                    rep     #PXFLAG
 4846                                   .LONGI  on
 4847                                   .MNLIST
 4848  F8FE37  A0 00 00         ?lp1:   ldy     #0
  Tue Jul 17 11:11:08 2018                                                                                               Page   40




 4849  F8FE3A  BB                       tyx
 4850  F8FE3B  BF 00 18 01      ?lp2:   lda     >EMURAM,x
 4851  F8FE3F  97 00                    sta     [0],y
 4852  F8FE41  C8                       iny
 4853  F8FE42  E8                       inx
 4854  F8FE43  E0 00 08                 cpx     #$0800
 4855  F8FE46  90 F3                    bcc     ?lp2
 4856  F8FE48                           ACC16CLC
 4857  F8FE48  C2 21                    rep     #(PMFLAG.OR.PCFLAG)
 4858                                   .LONGA  on
 4859                                   .MNLIST
 4860  F8FE4A  8A                       txa
 4861  F8FE4B  65 00                    adc     <0
 4862  F8FE4D  85 00                    sta     <0
 4863  F8FE4F                           ACC08
 4864  F8FE4F  E2 20                    sep     #PMFLAG
 4865                                   .LONGA  off
 4866                                   .MNLIST
 4867  F8FE51  90 02                    bcc     ?nxt
 4868  F8FE53  E6 02                    inc     <2
 4869  F8FE55  EE 60 FC         ?nxt:   inc     !VIA4+VIAPRB
 4870  F8FE58  D0 DD                    bne     ?lp1
 4871  F8FE5A                           CPU08
 4872  F8FE5A  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 4873                                   .LONGA  off
 4874                                   .LONGI  off
 4875                                   .MNLIST
 4876  F8FE5C  80 08                    bra     ?10
 4877                           
 4878                                   ;sta    !CREMEOFF
 4879                                   ;ldy    #0
 4880                                   ;CPU16
 4881                                   ;tyx
 4882                                   ;lda    #$FFFF
 4883                                   ;mvn    #$E8, #$F8
 4884                                   ;mvn    #$E9, #$F9
 4885                                   ;mvn    #$EA, #$FA
 4886                                   ;mvn    #$EB, #$FB
 4887                                   ;mvn    #$EC, #$FC
 4888                                   ;mvn    #$ED, #$FD
 4889                                   ;mvn    #$EE, #$FE
 4890                                   ;mvn    #$EF, #$FF
 4891                                   ;CPU08
 4892                                   ;bra    ?11
 4893                           
 4894                                   ; original boot sequence
 4895  F8FE5E  8D 07 FC         ?09:    sta     !CRFWEON        ; enable FLASH/EMU IN BANK $F0
 4896                                   ;lda    !CRBIT0         ; test boot
 4897  F8FE61  F0 03                    beq     ?10             ; firmware from flash
 4898  F8FE63  8D 09 FC                 sta     !CRXFEON        ; enable EEROM8U
 4899  F8FE66  A0 00            ?10:    ldy     #0
 4900  F8FE68                           CPU16
 4901  F8FE68  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 4902                                   .LONGA  on
 4903                                   .LONGI  on
 4904                                   .MNLIST
 4905  F8FE6A  BB                       tyx
  Tue Jul 17 11:11:08 2018                                                                                               Page   41




 4906  F8FE6B  A9 FF FF                 lda     #$FFFF
 4907  F8FE6E  54 F8 F0                 mvn     #$F0, #$F8
 4908  F8FE71  54 F9 F1                 mvn     #$F1, #$F9
 4909  F8FE74  54 FA F2                 mvn     #$F2, #$FA
 4910  F8FE77  54 FB F3                 mvn     #$F3, #$FB
 4911  F8FE7A  54 FC F4                 mvn     #$F4, #$FC
 4912  F8FE7D  54 FD F5                 mvn     #$F5, #$FD
 4913  F8FE80  54 FE F6                 mvn     #$F6, #$FE
 4914  F8FE83  54 FF F7                 mvn     #$F7, #$FF
 4915  F8FE86                           CPU08
 4916  F8FE86  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 4917                                   .LONGA  off
 4918                                   .LONGI  off
 4919                                   .MNLIST
 4920  F8FE88  4B               ?11:    phk
 4921  F8FE89  AB                       plb                     ; DBR = PBR = 0
 4922  F8FE8A  8D 08 FC                 sta     CRXFEOFF        ; disabilita flash F00000 - F7FFFF
 4923  F8FE8D  8D 06 FC                 sta     CRFWEOFF
 4924  F8FE90  5C F0 FF F8              jml     _SysStart       ; long jmp - bootstrap (banco $F8)
 4925                           
 4926  F8FE94                   _Unexpected:
 4927  F8FE94  40                       rti
 4928  F8FE95                           
 4929                           ; software interrupt generated by 'cop' istruction
 4930                           ;
 4931                           ; stack frame
 4932                           ;       ---------
 4933                           ;       |  PBR  |       0F
 4934                           ;       ---------
 4935                           ;       |  PCH  |       0E
 4936                           ;       ---------       
 4937                           ;       |  PCL  |       0D
 4938                           ;       ---------
 4939                           ;       |   P   |       0C
 4940                           ;       ---------
 4941                           ;       |   B   |       0B
 4942                           ;       ---------
 4943                           ;       |   A   |       0A
 4944                           ;       ---------
 4945                           ;       |  XH   |       09
 4946                           ;       ---------
 4947                           ;       |  XL   |       08
 4948                           ;       ---------
 4949                           ;       |  YH   |       07
 4950                           ;       ---------
 4951                           ;       |  YL   |       06
 4952                           ;       ---------
 4953                           ;       |  DPH  |       05
 4954                           ;       ---------
 4955                           ;       |  DPL  |       04
 4956                           ;       ---------
 4957                           ;       |  DBR  |       03
 4958                           ;       ---------
 4959                           ;       | CNTH  |       02
 4960                           ;       ---------          --> CNT parameters bytes count 
 4961                           ;       | CNTL  |       01
 4962                           ;       ---------
  Tue Jul 17 11:11:08 2018                                                                                               Page   42




 4963                           ;
 4964                           ; equates for access stack offset data
 4965          000001           STKCNT          .SET    $01
 4966          000006           STKYR           .SET    $06
 4967          000008           STKXR           .SET    $08
 4968          00000A           STKCR           .SET    $0A
 4969          00000B           STKBR           .SET    $0B
 4970          00000C           STKSR           .SET    $0C
 4971          00000D           STKPCL          .SET    $0D
 4972          00000F           STKPBR          .SET    $0F
 4973          00000F           STKNVAR         .SET    $0F
 4974                           
 4975                           ;USRCOP         .SET    $C0
 4976                           
 4977                           ;EINVAL         .EQU    $01
 4978                           
 4979  F8FE95                   _COPEntry:
 4980  F8FE95                           CPU16                   ; A/MEM/X/Y -> 16 bit
 4981  F8FE95  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 4982                                   .LONGA  on
 4983                                   .LONGI  on
 4984                                   .MNLIST
 4985  F8FE97  48                       pha                     ; save C in stack
 4986  F8FE98  DA                       phx                     ; save X(16) in stack
 4987  F8FE99  5A                       phy                     ; save Y(16) in stack
 4988  F8FE9A  0B                       phd                     ; save DPR in stack
 4989  F8FE9B  8B                       phb                     ; save DBR in stack
 4990  F8FE9C  A9 00 00                 lda     #0
 4991  F8FE9F  AA                       tax                     ; X = 0
 4992  F8FEA0  48                       pha                     ; params byte count in the stack ( = 0) 
 4993  F8FEA1  5B                       tcd                     ; set DPR = $0000
 4994  F8FEA2  4B                       phk                     ; set DBR = PBR = $00
 4995  F8FEA3  AB                       plb
 4996  F8FEA4  A3 0D                    lda     STKPCL,s        ; load PC saved in stack
 4997  F8FEA6  3A                       dec     a               ; pointer to signature byte
 4998  F8FEA7  85 51                    sta     COPPtr          ; save long pointer
 4999  F8FEA9                           CPU08                   ; A/MEM/X/Y -> 8 bit
 5000  F8FEA9  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 5001                                   .LONGA  off
 5002                                   .LONGI  off
 5003                                   .MNLIST
 5004  F8FEAB  8A                       txa
 5005  F8FEAC  EB                       xba                     ; B = 0
 5006  F8FEAD  A3 0F                    lda     STKPBR,s        ; PBR bank where COP was executed
 5007  F8FEAF  85 53                    sta     COPPtr+2
 5008  F8FEB1  A3 0C                    lda     STKSR,s         ; saved P in stack
 5009  F8FEB3  AA                       tax
 5010  F8FEB4  29 FE                    and     #~PCFLAG        ; clear carry in saved P
 5011  F8FEB6  83 0C                    sta     STKSR,s
 5012  F8FEB8  89 04                    bit     #PIFLAG         ; check if IRQ was enabled
 5013  F8FEBA  D0 01                    bne     ?04
 5014  F8FEBC  58                       cli                     ; enable IRQ
 5015  F8FEBD  DA               ?04:    phx                     ; saved P in stack
 5016  F8FEBE  A7 51                    lda     [COPPtr]        ; fetch signature byte
 5017  F8FEC0  85 54                    sta     COPIdx
 5018  F8FEC2                           CPU16                   ; now C = $00XX
 5019  F8FEC2  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
  Tue Jul 17 11:11:08 2018                                                                                               Page   43




 5020                                   .LONGA  on
 5021                                   .LONGI  on
 5022                                   .MNLIST
 5023  F8FEC4  0A                       asl     a               ; index * 4     
 5024  F8FEC5  0A                       asl     a
 5025  F8FEC6  AA                       tax
 5026  F8FEC7  E0 00 02                 cpx     #$0200
 5027  F8FECA  90 0B                    bcc     ?05             ; range $00..$7F
 5028  F8FECC  BF 00 FA F8              lda     >SYSTBLE_ADDR,x ; address of cop vector range $80..$FF
 5029  F8FED0  A8                       tay
 5030  F8FED1  BF 02 FA F8              lda     >SYSTBLE_ADDR+2,x ; A = bank of cop vector, B = valid/params
 5031  F8FED5  80 06                    bra     ?06
 5032  F8FED7  BC 00 FA         ?05:    ldy     !SYSTBLE_ADDR,x ; address of cop vector range $00..$7F
 5033  F8FEDA  BD 02 FA                 lda     !SYSTBLE_ADDR+2,x ; A = bank of cop vector, B = valid/params
 5034  F8FEDD  8C ED FE         ?06:    sty     ?08+1
 5035  F8FEE0                           CPU08
 5036  F8FEE0  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 5037                                   .LONGA  off
 5038                                   .LONGI  off
 5039                                   .MNLIST
 5040  F8FEE2  30 38                    bmi     ?30             ; B<7> = 1 -> invalid function
 5041  F8FEE4  8D EF FE                 sta     !?08+3
 5042  F8FEE7  EB                       xba                     ; A = bytes number of params
 5043  F8FEE8  83 02                    sta     STKCNT+1,s      ; take in account the 'phx' in ?04 !!
 5044  F8FEEA  68                       pla                     ; saved P in stack
 5045  F8FEEB  4A                       lsr     a               ; pass carry to function
 5046  F8FEEC  22 00 00 00      ?08:    jsl     $000000
 5047  F8FEF0  90 0C                    bcc     ?16             ; no error
 5048  F8FEF2  83 06                    sta     STKYR,s         ; return error in Y
 5049  F8FEF4  A9 00                    lda     #0
 5050  F8FEF6  83 07                    sta     STKYR+1,s
 5051  F8FEF8  A3 0C                    lda     STKSR,s         ; saved P in stack
 5052  F8FEFA  09 01                    ora     #PCFLAG         ; set carry in saved P
 5053  F8FEFC  83 0C                    sta     STKSR,s
 5054                           ?16:    ; epilogue code 
 5055  F8FEFE                           CPU16
 5056  F8FEFE  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 5057                                   .LONGA  on
 5058                                   .LONGI  on
 5059                                   .MNLIST
 5060  F8FF00  A3 01                    lda     STKCNT,s        ; number of params bytes in the stack
 5061  F8FF02  F0 11                    beq     ?20             ; no params -- skip stack cleaning
 5062  F8FF04  18                       clc
 5063  F8FF05  3B                       tsc                     ; C = stack pointer
 5064  F8FF06  69 0F 00                 adc     #STKNVAR        ; add size of stack vars
 5065  F8FF09  AA                       tax                     ; source pointer for data move  
 5066  F8FF0A  63 01                    adc     STKCNT,s        ; add params bytes count
 5067  F8FF0C  A8                       tay                     ; dest pointer for data move
 5068  F8FF0D  A9 0E 00                 lda     #STKNVAR-1      ; move bytes count
 5069  F8FF10  44 00 00                 mvp     #0, #0          ; cleanup stack
 5070  F8FF13  98                       tya                     ; new stack pointer
 5071  F8FF14  1B                       tcs
 5072  F8FF15  68               ?20:    pla                     ; skip STKCNT
 5073  F8FF16  AB                       plb                     ; restore DBR
 5074  F8FF17  2B                       pld                     ; restore DPR
 5075  F8FF18  7A                       ply                     ; restore Y
 5076  F8FF19  FA                       plx                     ; restore X
  Tue Jul 17 11:11:08 2018                                                                                               Page   44




 5077  F8FF1A  68                       pla                     ; restore C
 5078  F8FF1B  40                       rti                     ; restore P and return
 5079                           
 5080  F8FF1C  FA               ?30:    plx     
 5081  F8FF1D  4C FE FE                 jmp     ?16
 5082                           
 5083  F8FF20                   _BRKEntry:
 5084  F8FF20                           CPU16                   ; salva registri 16 bit
 5085  F8FF20  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 5086                                   .LONGA  on
 5087                                   .LONGI  on
 5088                                   .MNLIST
 5089  F8FF22  48                       pha                     ; salva A
 5090  F8FF23  DA                       phx                     ; salva X
 5091  F8FF24  5A                       phy                     ; salva Y
 5092  F8FF25  0B                       phd
 5093  F8FF26  8B                       phb                     ; salva DBR
 5094  F8FF27  4B                       phk                     ; DBR = 0 = PBR(K)
 5095  F8FF28  AB                       plb                     ; DATA BANK 0
 5096  F8FF29                           CPU08
 5097  F8FF29  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 5098                                   .LONGA  off
 5099                                   .LONGI  off
 5100                                   .MNLIST
 5101  F8FF2B  5C 06 00 FF              jml     BRKMON
 5102  F8FF2F                           
 5103                           ; gestione interrupt non mascherabile linea NMI (RTI restore P and register size)
 5104  F8FF2F                   _NMIEntry:
 5105                           
 5106                                   .EXTERN shutdown
 5107                           
 5108  F8FF2F                           CPU16                   ; salva registri 16 bit
 5109  F8FF2F  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 5110                                   .LONGA  on
 5111                                   .LONGI  on
 5112                                   .MNLIST
 5113  F8FF31  48                       pha                     ; salva A
 5114  F8FF32  DA                       phx                     ; salva X
 5115  F8FF33  5A                       phy                     ; salva Y
 5116  F8FF34  0B                       phd
 5117  F8FF35  8B                       phb                     ; salva DBR
 5118  F8FF36  4B                       phk                     ; DBR = 0 = PBR(K)
 5119  F8FF37  AB                       plb                     ; DATA BANK 0
 5120  F8FF38  A9 00 00                 lda     #0              ; pagina 0
 5121  F8FF3B  5B                       tcd
 5122  F8FF3C                           CPU08                   ; imposta registri 8 bit
 5123  F8FF3C  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 5124                                   .LONGA  off
 5125                                   .LONGI  off
 5126                                   .MNLIST
 5127                           
 5128  F8FF3E  AD 1D FD                 lda     !VIA1+VIAIFR    ; flag IFR VIA 1
 5129  F8FF41  10 49                    bpl     ?100            ; no irq da VIA 1
 5130  F8FF43  4A                       lsr     a               ; test CA2 (NMI KEYB)
 5131  F8FF44  90 2C                    bcc     ?50             ; no CA2
 5132  F8FF46  AE 42 FD                 ldx     KBFR+2
 5133  F8FF49  E0 83                    cpx     #KB_CTRLBREAK
  Tue Jul 17 11:11:08 2018                                                                                               Page   45




 5134  F8FF4B  D0 08                    bne     ?02
 5135  F8FF4D  A8                       tay
 5136  F8FF4E  A9 80                    lda     #$80
 5137  F8FF50  04 4B                    tsb     CtrlBrk
 5138  F8FF52  98                       tya
 5139  F8FF53  80 15                    bra     ?40
 5140  F8FF55  E0 84            ?02:    cpx     #KB_ALTSYSREQ
 5141  F8FF57  D0 11                    bne     ?06
 5142  F8FF59  A2 01                    ldx     #CA2IFRB
 5143  F8FF5B  8E 1D FD                 stx     VIA1+VIAIFR
 5144  F8FF5E  8E 45 FD                 stx     KBCLRNMI        ; azzera linea INT
 5145  F8FF61  A8                       tay
 5146  F8FF62  A9 40                    lda     #$40
 5147  F8FF64  04 4B                    tsb     CtrlBrk 
 5148  F8FF66  5C 09 00 FF              jml     ALTSYSMON
 5149  F8FF6A                   ?06:
 5150  F8FF6A  A2 01            ?40:    ldx     #CA2IFRB
 5151  F8FF6C  8E 1D FD                 stx     VIA1+VIAIFR
 5152  F8FF6F  8E 45 FD                 stx     KBCLRNMI        ; azzera linea INT
 5153  F8FF72  4A               ?50:    lsr     a
 5154  F8FF73  4A                       lsr     a
 5155  F8FF74  4A                       lsr     a
 5156  F8FF75  90 15                    bcc     ?100
 5157  F8FF77  A2 08                    ldx     #CB2IFRB        ; trigger
 5158  F8FF79  8E 1D FD                 stx     VIA1+VIAIFR     ; clear irq flag
 5159  F8FF7C  A9 01                    lda     #$01
 5160  F8FF7E  24 4B                    bit     CtrlBrk
 5161  F8FF80  D0 0A                    bne     ?100
 5162  F8FF82  04 4B                    tsb     CtrlBrk
 5163                           
 5164  F8FF84                           
 5165                           ?51:    ;lda    VIA1+VIAPRB
 5166                                   ;cmp    VIA1+VIAPRB
 5167                                   ;bne    ?51
 5168                                   ;and    #$10
 5169                                   ;beq    ?51
 5170                           
 5171                                   ; OFF command
 5172                                   ;ldx    #RTCEXTCTRLA
 5173                                   ;stx    RTCALE
 5174                                   ;lda    #$08            ; POWERON -> HIGH       
 5175                                   ;tsb    RTCDATA
 5176  F8FF84                           
 5177  F8FF84  22 C3 20 F8              jsl     shutdown
 5178  F8FF88  A9 01                    lda     #$01
 5179  F8FF8A  14 4B                    trb     CtrlBrk
 5180  F8FF8C                           
 5181                           
 5182  F8FF8C                   ?100:   
 5183  F8FF8C                           CPU16                   ; ripristina registri 16 bit
 5184  F8FF8C  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 5185                                   .LONGA  on
 5186                                   .LONGI  on
 5187                                   .MNLIST
 5188  F8FF8E  AB                       plb                     ; ripristina DBR
 5189  F8FF8F  2B                       pld
 5190  F8FF90  7A                       ply                     ; ripristina Y
  Tue Jul 17 11:11:08 2018                                                                                               Page   46




 5191  F8FF91  FA                       plx                     ; ripristina X
 5192  F8FF92  68                       pla                     ; ripristina A
 5193  F8FF93  40                       rti
 5194  F8FF94                           LONG_OFF
 5195                                   .LONGA  off
 5196                                   .LONGI  off
 5197                                   .MNLIST
 5198                           
 5199                           ; gestione interrupt linea IRQ (RTI restore P and register size)
 5200  F8FF94                   _IRQEntry:
 5201  F8FF94                           CPU16                   ; salva registri 16 bit
 5202  F8FF94  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 5203                                   .LONGA  on
 5204                                   .LONGI  on
 5205                                   .MNLIST
 5206  F8FF96  48                       pha                     ; salva A
 5207  F8FF97  DA                       phx                     ; salva X
 5208  F8FF98  5A                       phy                     ; salva Y
 5209  F8FF99  0B                       phd                     ; salva DP
 5210  F8FF9A  8B                       phb                     ; salva DBR
 5211  F8FF9B  4B                       phk                     ; DBR = 0 = PBR(K)
 5212  F8FF9C  AB                       plb                     ; DATA BANK 0
 5213  F8FF9D  A9 00 00                 lda     #0
 5214  F8FFA0  5B                       tcd                     ; imposta pagina 0
 5215  F8FFA1                           CPU08                   ; imposta registri 8 bit
 5216  F8FFA1  E2 30                    sep     #(PMFLAG.OR.PXFLAG)
 5217                                   .LONGA  off
 5218                                   .LONGI  off
 5219                                   .MNLIST
 5220  F8FFA3  AE 47 FD                 ldx     IRQVECTR        ; legge vettore IRQ (x2)
 5221  F8FFA6  FC 00 F0                 jsr     (intsr,x)       ; esegue subroutine IntSr
 5222  F8FFA9                           CPU16                   ; ripristina registri 16 bit
 5223  F8FFA9  C2 30                    rep     #(PMFLAG.OR.PXFLAG)
 5224                                   .LONGA  on
 5225                                   .LONGI  on
 5226                                   .MNLIST
 5227  F8FFAB  AB                       plb                     ; ripristina DBR
 5228  F8FFAC  2B                       pld                     ; ripristina DP
 5229  F8FFAD  7A                       ply                     ; ripristina Y
 5230  F8FFAE  FA                       plx                     ; ripristina X
 5231  F8FFAF  68                       pla                     ; ripristina A
 5232  F8FFB0  40                       rti
 5233  F8FFB1                           LONG_OFF
 5234                                   .LONGA  off
 5235                                   .LONGI  off
 5236                                   .MNLIST
 5237  F8FFB1                           
 5238                           ;----------------------------------------------------------
 5239                           ; ---- VETTORI CPU
 5240                           ;----------------------------------------------------------
 5241  F8FFB1                           
 5242                                   .SYSVECTRS
 5243  F8FFE0                           
 5244                                   ; vettori modo nativo
 5245  F8FFE0  0000                     .DW     0                ; FFE0
 5246  F8FFE2  0000                     .DW     0                ; FFE2
 5247  F8FFE4  95FE                     .DW     _COPEntry       ; FFE4 -> COP
  Tue Jul 17 11:11:08 2018                                                                                               Page   47




 5248  F8FFE6  20FF                     .DW     _BRKEntry       ; FFE6 -> BRK
 5249  F8FFE8  94FE                     .DW     _Unexpected     ; FFE8 -> ABORT (non usato)
 5250  F8FFEA  2FFF                     .DW     _NMIEntry       ; FFEA -> NMI
 5251  F8FFEC  94FE                     .DW     _Unexpected     ; FFEC -> riservato
 5252  F8FFEE  94FF                     .DW     _IRQEntry       ; FFEE -> IRQ
 5253                           
 5254                           ; nel banco $F8
 5255  F8FFF0                   _SysStart:
 5256  F8FFF0  4C 86 12                 jmp     !SysStart
 5257  F8FFF3  00                       .DB     $00
 5258  F8FFF4                           
 5259                                   ; vettori modo emulazione
 5260  F8FFF4  95FE                     .DW     _COPEntry       ; FFF4 -> COP
 5261  F8FFF6  94FE                     .DW     _Unexpected     ; FFF6 -> riservato
 5262  F8FFF8  94FE                     .DW     _Unexpected     ; FFF8 -> ABORT (non usato)
 5263  F8FFFA  2FFF                     .DW     _NMIEntry       ; FFFA -> NMI
 5264  F8FFFC  00FE                     .DW     _RSTEntry       ; FFFC -> RESET
 5265  F8FFFE  94FF                     .DW     _IRQEntry       ; FFFE -> IRQ
 5266                           
 5267  F90000                           
 5268                                   .END _RSTEntry


             Lines Assembled : 4746                  Errors : 0