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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0169.PLD)

  1  || FILE:   #0169.PLD
  2  || PROJ:   20170602        
  3  || PART:   G16V8-#0169
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   I/O DECODER
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:A2, 2:A3, 3:A4, 4:A5, 5:A6, 6:A7, 7:IO, 8:PHI2, 9:RW, 11:PHI0,
 14  || OUTPUT 
 15  |  12:VIA, 13:TLC, 14:ACIA, 15:RD, 16:WE, 17:URD, 18:UWR, 19:EN
 16  |
 17  ||
 18  |  ACTIVE-LOW: VIA, TLC, ACIA, RD, WE, URD
 19  |
 20  |  PROPERTY: "SIMPLE"
 21  |
 22  |  SIGNATURE: "0169    "
 23  |
 24  || VIA  = FC10 - FC1F
 25  |  VIA  = (IO' & A7' & A6' & A5' & A4)
 26  || TLC  = FC20 - FC27
 27  |  TLC  = (IO' & A7' & A6' & A5  & A4' & A3')
 28  || ACIA = FC28 - FC2B
 29  |  ACIA = (IO' & A7' & A6' & A5  & A4' & A3  & A2')
 30  || UM245R = FC2C - FC2F
 31  |  UM   = (IO' & A7' & A6' & A5  & A4' & A3  & A2)
 32  || READ/WRITE UM245R PORT
 33  |  URD = (UM & PHI2 & RW)
 34  |  UWR = (UM & PHI2 & RW')
 35  || RD/WE
 36  |  RD = (PHI2 & RW)
 37  |  WE = (PHI0 & RW')
 38  || DATA BUS ENABLE SIGNAL
 39  |  EN = (PHI2 # PHI0)



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  1/17/18  8:31 am  (Wednesday)
I203  Memory usage 79K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0169.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

VIA               56   A4  A5' A6' A7' IO' 

TLC               48   A3' A4' A5  A6' A7' IO' 

ACIA              40   A2' A3  A4' A5  A6' A7' IO' 

URD               16   A2  A3  A4' A5  A6' A7' IO' PHI2  RW  

UWR                8   A2  A3  A4' A5  A6' A7' IO' PHI2  RW' 

RD                32   PHI2  RW  

WE                24   RW' PHI0  

EN                 0   PHI2  
                   1   PHI0  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A2              2        -    -    -        High    (Clock)
  2.     A3              0        -    -    -        High     
  3.     A4              4        -    -    -        High     
  4.     A5              8        -    -    -        High     
  5.     A6             12        -    -    -        High     
  6.     A7             16        -    -    -        High     
  7.     IO             20        -    -    -        High     
  8.     PHI2           24        -    -    -        High     
  9.     RW             28        -    -    -        High     
 11.     PHI0           30        -    -    -        High    (Enable)
 12.     VIA            27       56    8    1        Low      
 13.     TLC            23       48    8    1        Low      
 14.     ACIA           19       40    8    1        Low      
 15.     RD              1       32    8    1        Low      
 16.     WE              1       24    8    1        Low      
 17.     URD            15       16    8    1        Low      
 18.     UWR            10        8    8    1        High     
 19.     EN              6        0    8    2        High     
                                    ---- ----
                                      64    9  (14%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L0032 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 *
L0256 01 01 10 11 01 11 10 11 10 11 10 11 01 11 10 11 *
L0512 01 01 10 11 01 11 10 11 10 11 10 11 01 11 01 11 *
L0768 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 01 *
L1024 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 *
L1280 01 10 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
L1536 10 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
L1792 11 11 01 11 10 11 10 11 10 11 10 11 11 11 11 11 *
L2048 11 00 00 00 00 11 00 00 00 11 00 01 00 11 01 10 *
L2080 00 11 10 01 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C2AAF*

I202  1/17/18  8:32 am  (Wednesday)
I203  Memory usage 6K
I204  Elapsed time 1 second