Blame | Last modification | View Log | Download | RSS feed
|| FILE: #0168.PLD|| PROJ: 20170501|| FD-02 FDC/ATA/DMA BOARD|||| PART: G26CV12-#0168|||| DEV : GAL26CV12|||| DESC: ATA0 CONTROL||||GAL26CV12||| INPUT| 1:A0, 2:A1, 3:A2, 4:A3, 5:A4, 6:A5, 8:A6, 9:RW, 10:PHI2,| 11:IO, 12:DMA, 13:PHI0, 14:IOR, 15:IOW, 28:MW0,|| OUTPUT| 16:WRH, 17:WRL, 18:WRD, 19:RDH, 20:WE, 22:RDD, 23:GA,| 24:RDL, 25:RD, 26:CS0, 27:CS1|| ACTIVE-LOW: CS0, CS1, WRH, WRL, WRD, RDH, RDL, RDD, RD, WE, GA||| SIGNATURE: "0168 "||| --------------------------------------------------------|| common signals when dma disabled (DMA = 1 => cpu access)||| ATA = DMA & IO' & A6' & A5 & A4' || ata0 => FDA0-FDAF|| ATA = DMA & IO' & A6' & A5 & A4 || ata1 => FDB0-FDBF| S01 = ATA & A3' & A2' & A1' & A0 || FDB1| S02 = ATA & A3' & A2' & A1 || FDB2-FDB3| S04 = ATA & A3' & A2 || FDB4-FDB7| S08 = ATA & A3 & A2' & A1' & A0' || FDB1| S0A = ATA & A3 & A2' & A1 & A0' || FDBA| S0B = ATA & A3 & A2' & A1 & A0 || FDBB| S0E = ATA & A3 & A2 & A1 & A0' || FDBE| SATA = (S01 # S02 # S04 # S0E) || valid ata registers| CRD = SATA & RW & PHI2 || cpu read ata| CWR0 = SATA & RW' & PHI2 & MW0 || cpu write ata (02)| CWR1 = SATA & RW' & PHI0 & MW0' || cpu write ata (00)| CWE = (CWR0 # CWR1) || cpu write ata|||| signals when dma0 access ata| DRD = DMA' & IOR' || dma read ata port 0| DWR = DMA' & IOW' || dma write ata port 0|||| output signals| WRL = S0A & RW' & PHI0 || cpu write low latch| WRH = S0B & RW' & PHI0 || cpu write high latch| RDL = S0A & RW & PHI2 || cpu read low latch| RDH = S0B & RW & PHI2 || cpu read high latch| WRD = S08 & RW' & PHI2 || cpu dummy write latch| RDD = S08 & RW & PHI2 || cpu dummy read latch| RD = CRD # DRD| WE = CWE # DWR| GA = (SATA # S0A # S0A) || enable internal data bus| CS0 = (S01 # S02 # S04 # S08) & PHI2| CS1 = S0E & PHI2