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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0166.PLD)

  1  || FILE:   #0166.PLD
  2  || PROJ:   20170501
  3  ||         FD-02 FDC/ATA/DMA BOARD
  4  || 
  5  || PART:   G22V10-#0050
  6  ||
  7  || DEV :   GAL22V10
  8  ||
  9  ||         DESC:   RAM ACCESS CONTROL
 10  ||
 11  |
 12  |GAL22V10
 13  |
 14  || input signal description
 15  || GEN  = gate enable
 16  || /DMA = dma enable
 17  || DIR  = dma data bus direction (1 => read, 0 => write)
 18  || /S1M = enable 1Mb ram bank (otherwise 128k)
 19  || ATA  = dma ata port select (0 => port 0, 1 => port 1)
 20  || /FDC = enable dma for fdc operation (otherwise ata)
 21  || /ALT = enable dma1 to use 1Mb ram bank (otherwise use 128Kb)
 22  ||  
 23  || INPUT
 24  |  1:MA0, 2:CX2, 3:GEN, 4:OE0, 5:OE1, 6:DMA, 7:RW, 8:DIR, 
 25  |  9:S1M, 10:ATA, 11:FDC, 13:ALT,
 26  || OUTPUT 
 27  |  14:CEL, 15:CEH, 16:CER, 17:ENL, 18:ENH, 19:BE0,
 28  |  20:BE1, 21:MDIR, 22:AEN, 23:A16E
 29  |
 30  | ACTIVE-LOW: CEL, CEH, CER, ENL, ENH, BE0, BE1, A16E
 31  |
 32  |
 33  | SIGNATURE: "0166    "
 34  |
 35  || --------------------------------------------------------
 36  || common signals when dma disabled (DMA = 1 => cpu access)
 37  ||
 38  |  RAM0  = CX2' & DMA & OE0                || cpu access ram (dma0 = off)
 39  |  RAM1  = CX2' & DMA & OE1                || cpu access ram (dma1 = off)
 40  |  MLC0  = RAM0 & S1M' & MA0'              || cpu access 1Mb even ram
 41  |  MLC1  = RAM1 & S1M' & MA0'              || cpu access 1Mb even ram
 42  |  MHC0  = RAM0 & S1M' & MA0               || cpu access 1Mb odd  ram
 43  |  MHC1  = RAM1 & S1M' & MA0               || cpu access 1Mb odd  ram
 44  |  MLCA  = MLC0 # MLC1                     || cpu access 1Mb even ram
 45  |  MHCA  = MHC0 # MHC1                     || cpu access 1Mb odd  ram
 46  |  MLCS  = MLCA & GEN                      || cpu select 1Mb even ram
 47  |  MHCS  = MHCA & GEN                      || cpu select 1Mb odd  ram
 48  |  MMC0  = RAM0 & S1M                      || cpu access 128Kb ram
 49  |  MMC1  = RAM1 & S1M                      || cpu access 128Kb ram
 50  |  MMCS  = (MMC0 # MMC1) & GEN             || cpu select 128Kb ram
 51  ||
 52  |  CDIR  = RW & DMA & OE0 & OE1            || cpu bus direction to 1Mb ram
 53  ||
 54  || common signals when dma enabled (DMA = 0)
 55  |  D0ON  = DMA' & OE0' & OE1  & FDC        || dma0 master


 56  |  D1ON  = DMA' & OE0  & OE1' & FDC'   || dma1 master
 57  |  D1MB  = D1ON & ALT'                     || dma1 access 1Mb ram
 58  |  D1MBL = D1MB & MA0'                     || dma1 access 1Mb even ram
 59  |  D1MBH = D1MB & MA0                      || dma1 access 1Mb odd  ram
 60  |  D128K = D1ON & ALT                      || dma1 access 128kb ram
 61  ||
 62  |  D0DIR = DIR  & DMA' & FDC               || dma0 bus direction to 1Mb ram
 63  |  D1DIR = DIR' & DMA' & FDC'              || dma1 bus direction to 1Mb ram   
 64  ||
 65  || output signals
 66  |  CEL   = MLCS # D0ON # D1MBL             || select even ram 1Mb
 67  |  CEH   = MHCS # D0ON # D1MBH             || select odd  ram 1Mb
 68  |  CER   = MMCS # D128K                    || select ram 128Kb
 69  |  ENL   = MLCA # D1MBL                    || data bus to 1Mb even ram
 70  |  ENH   = MHCA    # D1MBH                 || data bus to 1Mb even ram
 71  |  BE0   = D0ON & ATA'                     || ata0 data bus to 1Mb ram
 72  |  BE1   = D0ON & ATA                      || ata1 data bus to 1Mb ram
 73  |  AEN   = DMA'                            || cpu address enable
 74  |  A16E  = D1ON                            || enable extern A16 line for dma1
 75  |  MDIR  = CDIR # D0DIR # D1DIR            || bus direction to 1Mb ram



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/29/17  6:18 am  (Saturday)
I203  Memory usage 96K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0166.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

CEL              123   MA0' CX2' GEN  OE0  DMA  S1M' 
                 124   MA0' CX2' GEN  OE1  DMA  S1M' 
                 125   MA0' OE0  OE1' DMA' FDC' ALT' 
                 126   OE0' OE1  DMA' FDC  

CEH              112   MA0  CX2' GEN  OE0  DMA  S1M' 
                 113   MA0  CX2' GEN  OE1  DMA  S1M' 
                 114   MA0  OE0  OE1' DMA' FDC' ALT' 
                 115   OE0' OE1  DMA' FDC  

ENL               84   MA0' OE0  OE1' DMA' FDC' ALT' 
                  85   MA0' CX2' OE0  DMA  S1M' 
                  86   MA0' CX2' OE1  DMA  S1M' 

ENH               67   MA0  OE0  OE1' DMA' FDC' ALT' 
                  68   MA0  CX2' OE0  DMA  S1M' 
                  69   MA0  CX2' OE1  DMA  S1M' 

CER               99   CX2' GEN  OE0  DMA  S1M  
                 100   CX2' GEN  OE1  DMA  S1M  
                 101   OE0  OE1' DMA' FDC' ALT  

BE0               50   OE0' OE1  DMA' ATA' FDC  

BE1               35   OE0' OE1  DMA' ATA  FDC  

AEN               11   DMA' 

A16E               2   OE0  OE1' DMA' FDC' 

MDIR              22   OE0  OE1  DMA  RW  
                  23   DMA' DIR' FDC' 
                  24   DMA' DIR  FDC  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     MA0             0        -    -    -        High    (Clock)
  2.     CX2             4        -    -    -        High     
  3.     GEN             8        -    -    -        High     
  4.     OE0            12        -    -    -        High     
  5.     OE1            16        -    -    -        High     
  6.     DMA            20        -    -    -        High     
  7.     RW             24        -    -    -        High     
  8.     DIR            28        -    -    -        High     
  9.     S1M            32        -    -    -        High     
 10.     ATA            36        -    -    -        High     
 11.     FDC            40        -    -    -        High     
 13.     ALT            42        -    -    -        High     
 14.     CEL            39      122    9    4        Low     (Three-state)
 15.     CEH            35      111   11    4        Low     (Three-state)
 16.     CER            31       98   13    3        Low     (Three-state)
 17.     ENL            27       83   15    3        Low     (Three-state)
 18.     ENH            23       66   17    3        Low     (Three-state)
 19.     BE0            19       49   17    1        Low     (Three-state)
 20.     BE1            15       34   15    1        Low     (Three-state)
 21.     MDIR           10       21   13    3        High    (Three-state)
 22.     AEN             6       10   11    1        High    (Three-state)
 23.     A16E            3        1    9    1        Low     (Three-state)
 25.     -               -        0    1    0                 
 26.     -               -      131    1    0                 
                                    ---- ----
                                     132   24  (18%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       PAL22V10
*
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 01 11 01 11 01 11 01 11 11 11 11 11 11 11 11 11 *
L1012 11 11 11 11 11 11 11 11 11 11 10 11 11 11 10 11 11 11 11 11 10 11 *
L1056 11 11 11 11 11 11 11 11 11 11 10 11 11 11 01 11 11 11 11 11 01 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 01 11 01 11 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 10 11 01 11 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 01 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
L2992 01 11 10 11 11 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L3036 01 11 10 11 11 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 10 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
L3740 10 11 10 11 11 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L3784 10 11 10 11 11 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 10 11 01 11 01 11 11 11 01 11 11 11 11 11 01 11 11 11 11 11 *
L4400 11 11 10 11 01 11 11 11 01 11 01 11 11 11 11 11 01 11 11 11 11 11 *
L4444 11 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 01 *
L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4928 01 11 10 11 01 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L4972 01 11 10 11 01 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L5016 01 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
L5060 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 11 11 01 11 *
L5368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5412 10 11 10 11 01 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L5456 10 11 10 11 01 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L5500 10 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
L5544 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 11 11 01 11 *
L5808 01 11 11 01 01 01 01 01 01 01 *
CB4F2*

I202  7/29/17  6:18 am  (Saturday)
I203  Memory usage 8K
I204  Elapsed time 1 second