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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0165B.PLD)

  1  || FILE:   #0165.PLD
  2  || PROJ:   20170501
  3  ||         FD-02 FDC/ATA/DMA BOARD
  4  || 
  5  || PART:   G26CV12-#0165
  6  ||
  7  || DEV :   GAL26CV12
  8  ||
  9  ||         DESC:   DECODER I/O
 10  ||
 11  |
 12  |GAL26CV12
 13  |
 14  || GEN  = gate enable
 15  || /MGE = ram gate enable (/OE0 nor /OE 1)
 16  || INPUT
 17  |  1:A1, 2:-, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2, 
 18  | 11:CX2, 12:MGE, 13:PHI0, 14:DMA, 28:GEN,
 19  || OUTPUT 
 20  |  15:CE0, 16:CE1, 17:AT0, 18:AT1, 19:CE2, 20:DBE, 22:DDE, 23:CE3,
 21  |  24:MRD, 25:MWE, 26:IOR, 27:IOW
 22  |
 23  | ACTIVE-LOW: CE0, CE1, AT0, AT1, CE2, DBE, DDE, MRD, MWE, IOR, IOW
 24  |
 25  |
 26  | SIGNATURE: "0165B   "
 27  |
 28  || --------------------------------------------------------
 29  || common signals when dma disblad (DMA = 1 => cpu access)
 30  ||
 31  |  SCX2  = CX2' & DMA                      || ram select when cpu access
 32  |  FDD0  = IO' & A6  & A5' & A4    || select FDD0-FDDF
 33  |  FDC   = FDD0 & A3 & DMA         || fdc  select FDD8-FDDF
 34  |  DM0   = IO' & A6' & A5' & A4' & DMA     || dma0 select FD80-FD8F
 35  |  DM1   = IO' & A6' & A5' & A4  & DMA     || dma1 select FD90-FD9F
 36  |  ATA0  = IO' & A6' & A5  & A4' & DMA     || ata0 select FDA0-FDAF
 37  |  ATA1  = IO' & A6' & A5  & A4  & DMA     || ata1 select FDB0-FDBF
 38  ||  VIA   = IO' & A6  & A5' & A4'  || via  select FDC0-FDCF (always)
 39  ||  USB   = FDD0 & A3' & A2' & A1' || usb  select FDD0-FDD1 (always)
 40  ||
 41  |  FDCR  = FDC & RW  & GEN & PHI2  || cpu read  fdc  02 sync
 42  |  FDCW  = FDC & RW' & PHI2                || cpu write fdc  02 sync
 43  |  DM0R  = DM0 & RW  & PHI2                || cpu read  dma0 02 sync
 44  |  DM0W  = DM0 & RW' & PHI2                || cpu write dma0 00 sync
 45  |  DM1R  = DM1 & RW  & PHI2                || cpu read  dma1 02 sync
 46  |  DM1W  = DM1 & RW' & PHI2                || cpu write dma1 00 sync
 47  |  IORD  = FDCR # DM0R # DM1R              || cpu read  fdc, dma0, dma1
 48  |  IOWE  = FDCW # DM0W # DM1W              || cpu write fdc, dma0, dma1
 49  ||
 50  |  MEMR  = SCX2 & MGE' & RW  & PHI2        || cpu read ram
 51  |  MEMW  = SCX2 & MGE' & RW' & PHI0        || cpu write ram (00 sync)
 52  ||
 53  || global data bus enable for cpu access
 54  ||  DBEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 # VIA # USB
 55  |  DBEE = SCX2 # IO'


 56     
 57  ||
 58  || local shared dma data bus enable for cpu access
 59  |  DDEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1   
 60  ||
 61  || output signals
 62  |  CE0   = DM0                             || dma0 FD80-FD8F
 63  |  CE1   = DM1                             || dma1 FD90-FD9F
 64  |  AT0   = ATA0                            || ata0 FDA0-FDAF
 65  |  AT1   = ATA1                            || ata1 FDA0-FDAF
 66  |  CE2   = FDC                             || fdc  FDD8-FDDF
 67  |  CE3   = FDC                             || fdc  FDD8-FDDF (positive)
 68  |  IOR   = DMA ?? IORD                     || i/o read  strobe 3-states
 69  |  IOW   = DMA ?? IOWE                     || i/o write strobe 3-states
 70  |  MWE   = DMA ?? MEMW                     || write ram strobe 3-states
 71  |  MRD   = DMA ?? MEMR                     || read  ram strobe 3-states
 72  ||  DBE   = DBEE & GEN                     || global data bus enable
 73  ||  DDE   = DDEE & GEN                     || local  data bus enable
 74  |  DBE   = DBEE                    || global data bus enable
 75  |  DDE   = DDEE                    || local  data bus enable



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  2/17/18  12:31 pm  (Saturday)
I203  Memory usage 99K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0165B.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

CE0              113   A4' A5' A6' IO' DMA  

DDE               49   A3  A4  A5' A6  IO' DMA  
                  50   A4' A5' A6' IO' DMA  
                  51   A4' A5  A6' IO' DMA  
                  52   A4  A5' A6' IO' DMA  
                  53   A4  A5  A6' IO' DMA  
                  54   CX2' DMA  

CE1              104   A4  A5' A6' IO' DMA  

AT0               95   A4' A5  A6' IO' DMA  

AT1               86   A4  A5  A6' IO' DMA  

CE2               75   A3  A4  A5' A6  IO' DMA  

CE3               38   A3  A4  A5' A6  IO' DMA  

IOR               10   DMA  
                  11   A3  A4  A5' A6  IO' RW  PHI2  DMA  GEN  
                  12   A4' A5' A6' IO' RW  PHI2  DMA  
                  13   A4  A5' A6' IO' RW  PHI2  DMA  

IOW                1   DMA  
                   2   A3  A4  A5' A6  IO' RW' PHI2  DMA  
                   3   A4' A5' A6' IO' RW' PHI2  DMA  
                   4   A4  A5' A6' IO' RW' PHI2  DMA  

MWE               19   DMA  
                  20   RW' CX2' MGE' PHI0  DMA  

MRD               28   DMA  
                  29   RW  PHI2  CX2' MGE' DMA  

DBE               62   CX2' DMA  
                  63   IO' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A1              0        -    -    -        High    (Clock)
  2.     -               4        -    -    -                 
  3.     A3              8        -    -    -        High     
  4.     A4             12        -    -    -        High     
  5.     A5             16        -    -    -        High     
  6.     A6             20        -    -    -        High     
  8.     IO             24        -    -    -        High     
  9.     RW             28        -    -    -        High     
 10.     PHI2           32        -    -    -        High     
 11.     CX2            36        -    -    -        High     
 12.     MGE            40        -    -    -        High     
 13.     PHI0           44        -    -    -        High     
 14.     DMA            48        -    -    -        High     
 15.     CE0            51      112    9    1        Low     (Three-state)
 16.     CE1            47      103    9    1        Low     (Three-state)
 17.     AT0            43       94    9    1        Low     (Three-state)
 18.     AT1            39       85    9    1        Low     (Three-state)
 19.     CE2            35       74   11    1        Low     (Three-state)
 20.     DBE            31       61   13    2        Low     (Three-state)
 22.     DDE            27       48   13    6        Low     (Three-state)
 23.     CE3            22       37   11    1        High    (Three-state)
 24.     MRD            19       28    9    2        Low     (Three-state)
 25.     MWE            15       19    9    2        Low     (Three-state)
 26.     IOR            11       10    9    4        Low     (Three-state)
 27.     IOW             7        1    9    4        Low     (Three-state)
 28.     GEN             2        -    -    -        High     
 29.     -               -        0    1    0                 
 30.     -               -      121    1    0                 
                                    ---- ----
                                     122   26  (21%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL26CV12
*
QP28* QF6432* QV1024*
F0*
L0052 1111111111111111111111111111111111111111111111110111*
L0104 1111111101110111101101111011101101111111111111110111*
L0156 1111111111111011101110111011101101111111111111110111*
L0208 1111111111110111101110111011101101111111111111110111*
L0520 1111111111111111111111111111111111111111111111110111*
L0572 1101111101110111101101111011011101111111111111110111*
L0624 1111111111111011101110111011011101111111111111110111*
L0676 1111111111110111101110111011011101111111111111110111*
L0988 1111111111111111111111111111111111111111111111110111*
L1040 1111111111111111111111111111101111111011101101110111*
L1456 1111111111111111111111111111111111111111111111110111*
L1508 1111111111111111111111111111011101111011101111110111*
L1924 1111111111111111111111111111111111111111111111111111*
L1976 1111111101110111101101111011111111111111111111110111*
L2496 1111111111111111111111111111111111111111111111111111*
L2548 1111111101110111101101111011111111111111111111110111*
L2600 1111111111111011101110111011111111111111111111110111*
L2652 1111111111111011011110111011111111111111111111110111*
L2704 1111111111110111101110111011111111111111111111110111*
L2756 1111111111110111011110111011111111111111111111110111*
L2808 1111111111111111111111111111111111111011111111110111*
L3172 1111111111111111111111111111111111111111111111111111*
L3224 1111111111111111111111111111111111111011111111110111*
L3276 1111111111111111111111111011111111111111111111111111*
L3848 1111111111111111111111111111111111111111111111111111*
L3900 1111111101110111101101111011111111111111111111110111*
L4420 1111111111111111111111111111111111111111111111111111*
L4472 1111111111110111011110111011111111111111111111110111*
L4888 1111111111111111111111111111111111111111111111111111*
L4940 1111111111111011011110111011111111111111111111110111*
L5356 1111111111111111111111111111111111111111111111111111*
L5408 1111111111110111101110111011111111111111111111110111*
L5824 1111111111111111111111111111111111111111111111111111*
L5876 1111111111111011101110111011111111111111111111110111*
L6344 0101010111010101010101010011000000110001001101100011*
L6396 010101000010001000000010000000100000*
CD9AA*

I202  2/17/18  12:31 pm  (Saturday)
I203  Memory usage 9K
I204  Elapsed time 1 second