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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#9005.PLD)

  1  || FILE:   #9005.PLD
  2  || PROJ:   20130517        
  3  || PART:   G20V8-#9005
  4  ||
  5  || DEV :   GAL20V8
  6  ||
  7  ||         DESC:   I/O DECODER & CONTROL
  8  ||
  9  |
 10  |GAL20V8A
 11  |
 12  || INPUT
 13  |  1:A1, 2:A2, 3:A3, 4:A4, 5:A5, 6:A6, 7:A7, 8:IO0, 9:RW, 10:PHI2,
 14  |  11:EN, 13:RDYN, 14:RAMN, 23:-, 
 15  || OUTPUT 
 16  |  22:DBE, 21:VDC, 20:PIA, 19:WFF, 18:CRD, 17:CWE, 16:RD, 15:WIO
 17  |
 18  | SIGNATURE: "9005    "
 19  |
 20  |  ACTIVE-LOW: DBE, VDC, PIA, WFF, CRD, CWE, RD, WIO
 21  |
 22  |  PROPERTY: "SIMPLE"
 23  |
 24  || --------------------------------------------------------
 25  || IO SELECT => FF70-FF77 (65C02) - FC70-FC77 (65C816)
 26  |  IOS  = (IO0' & A7' & A6 & A5 & A4 & A3')
 27  || R6545/HD6445 => FF70-FF71 / FC70-FC71
 28  |  CRTC = (IOS & A2' & A1')
 29  || REGISTRO WRITE ONLY => FF72
 30  |  WREG = (IOS & A2' & A1 & RW')
 31  || PIA 65C21 => FF74-FF77 / FC74-FC77
 32  |  PIAS = (IOS & A2)
 33  || RD => segnale OE per RAM
 34  |  RD = (RW & PHI2)
 35  || CRD, CWE => segnali read,write per HD6545 (qualificati con EN)
 36  |  CRD = (CRTC & RW & EN)
 37  |  CWE = (CRTC & RW' & EN)
 38  || ABILITAZIONE CRTC e PIA
 39  |  PIA = PIAS
 40  |  VDC = CRTC
 41  || CLOCK per registro FF
 42  |  WFF = (WREG & RDYN)
 43  || SEGNALE WAIT I/O
 44  |  WIO = (CRTC # WREG)
 45  || SEGNALE ABILITAZIONE 74x245
 46  |  DBEIO = ((CRTC & EN) # (WREG & (EN # RDYN)) # (PIAS & PHI2))
 47  |  DBEM  = RAMN'
 48  |  DBE = (DBEIO # DBEM)



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  5/31/13  11:13 am  (Friday)
I203  Memory usage 84K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#9005.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

RD                48   RW  PHI2  

CRD               32   A1' A2' A3' A4  A5  A6  A7' IO0' RW  EN  

CWE               40   A1' A2' A3' A4  A5  A6  A7' IO0' RW' EN  

PIA               16   A2  A3' A4  A5  A6  A7' IO0' 

VDC                8   A1' A2' A3' A4  A5  A6  A7' IO0' 

WIO               56   A1  A2' A3' A4  A5  A6  A7' IO0' RW' 
                  57   A1' A2' A3' A4  A5  A6  A7' IO0' 

WFF               24   A1  A2' A3' A4  A5  A6  A7' IO0' RW' RDYN  

DBE                0   A1  A2' A3' A4  A5  A6  A7' IO0' RW' EN  
                   1   A1  A2' A3' A4  A5  A6  A7' IO0' RW' RDYN  
                   2   A1' A2' A3' A4  A5  A6  A7' IO0' EN  
                   3   A2  A3' A4  A5  A6  A7' IO0' PHI2  
                   4   RAMN' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A1              2        -    -    -        High    (Clock)
  2.     A2              0        -    -    -        High     
  3.     A3              4        -    -    -        High     
  4.     A4              8        -    -    -        High     
  5.     A5             12        -    -    -        High     
  6.     A6             16        -    -    -        High     
  7.     A7             20        -    -    -        High     
  8.     IO0            24        -    -    -        High     
  9.     RW             28        -    -    -        High     
 10.     PHI2           32        -    -    -        High     
 11.     EN             36        -    -    -        High     
 13.     RDYN           38        -    -    -        High    (Enable)
 14.     RAMN           34        -    -    -        High     
 15.     WIO            31       56    8    2        Low      
 16.     RD             27       48    8    1        Low      
 17.     CWE            23       40    8    1        Low      
 18.     CRD             -       32    8    1        Low      
 19.     WFF             -       24    8    1        Low      
 20.     PIA            19       16    8    1        Low      
 21.     VDC            15        8    8    1        Low      
 22.     DBE            11        0    8    5        Low      
 23.     -               6        -    -    -                 
                                    ---- ----
                                      64   13  (20%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL20V8
*
QP24* QF2706* QV1024*
F0*
L0000 10 01 10 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 01 11 *
L0040 10 01 10 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 01 *
L0080 10 10 10 11 01 11 01 11 01 11 10 11 10 11 11 11 11 11 01 11 *
L0120 01 11 10 11 01 11 01 11 01 11 10 11 10 11 11 11 01 11 11 11 *
L0160 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 *
L0320 10 10 10 11 01 11 01 11 01 11 10 11 10 11 11 11 11 11 11 11 *
L0640 01 11 10 11 01 11 01 11 01 11 10 11 10 11 11 11 11 11 11 11 *
L0960 10 01 10 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 01 *
L1280 10 10 10 11 01 11 01 11 01 11 10 11 10 11 01 11 11 11 01 11 *
L1600 10 10 10 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 01 11 *
L1920 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 11 *
L2240 10 01 10 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
L2280 10 10 10 11 01 11 01 11 01 11 10 11 10 11 11 11 11 11 11 11 *
L2560 00 00 00 00 00 11 10 01 00 11 00 00 00 11 00 00 00 11 01 01 *
L2600 00 10 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 00 00 00 *
L2640 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2680 11 11 11 11 11 11 11 11 11 11 11 11 10 *
C44B6*

I202  5/31/13  11:13 am  (Friday)
I203  Memory usage 7K
I204  Elapsed time 1 second