Subversion Repositories MB01 Project

OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#9003.PLD)

  1  || FILE:   #9003.PLD
  2  || PROJ:   20130517        
  3  || PART:   G16V8-#9003
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   VIDEO CONTROL
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:CLK, 2:HSI, 3:VSI, 4:CEI, 5:DEI, 6:VIN, 7:RV, 8:CT5, 9:HP, 12:VP, 
 14  || OUTPUT 
 15  |  19:HS, 18:VS, 17:DE, 16:V0, 15:CSY, 14:-, 13:-
 16  |
 17  | SIGNATURE: "9003    "
 18  |
 19  |  PROPERTY: "REGISTERED"
 20  |
 21  || --------------------------------------------------------
 22  |  VX0 = (CEI' & VIN' & RV  & CT5') 
 23  |  VX1 = (CEI' & VIN' & RV  & CT5)  
 24  |  VX2 = (CEI' & VIN  & RV' & CT5)  
 25  |  VX3 = (CEI  & VIN' & RV' & CT5)  
 26  |  VX4 = (CEI  & VIN  & RV  & CT5)  
 27  |  VX5 = (CEI  & RV'  & CT5') 
 28  |  VX6 = (VIN  & RV'  & CT5') 
 29  |  V0D = (VX0 # VX1 # VX2 # VX3 # VX4 # VX5 # VX6)  
 30  || POLARITA' SYNC
 31  |  HSD = (HSI ## HP)
 32  |  VSD = (VSI ## VP)
 33  |  CSD = (HSI ## VSI)
 34  || LOAD DATA
 35  |  HS  = CLK // HSD
 36  |  VS  = CLK // VSD
 37  |  DE  = CLK // DEI
 38  |  V0  = CLK // V0D
 39  |  CSY = CLK // CSD



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  5/30/13  7:20 pm  (Thursday)
I203  Memory usage 84K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#9003.PLA)

I289  Registered GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

HS                 0   HSI' HP  
                   1   HSI  HP' 

VS                 8   VSI' VP  
                   9   VSI  VP' 

DE                16   DEI  

V0                24   CEI' VIN' RV  CT5' 
                  25   CEI' VIN' RV  CT5  
                  26   CEI' VIN  RV' CT5  
                  27   CEI  VIN' RV' CT5  
                  28   CEI  VIN  RV  CT5  
                  29   CEI  RV' CT5' 
                  30   VIN  RV' CT5' 

CSY               32   HSI' VSI  
                  33   HSI  VSI' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     CLK             0        -    -    -        High    (Clock)
  2.     HSI             0        -    -    -        High     
  3.     VSI             4        -    -    -        High     
  4.     CEI             8        -    -    -        High     
  5.     DEI            12        -    -    -        High     
  6.     VIN            16        -    -    -        High     
  7.     RV             20        -    -    -        High     
  8.     CT5            24        -    -    -        High     
  9.     HP             28        -    -    -        High     
 12.     VP             30       56    8    0        High    (Three-state)
 13.     -              26       48    8    0                (Three-state)
 14.     -              22       40    8    0                (Three-state)
 15.     CSY            18       32    8    2        High    (Registered)
 16.     V0             14       24    8    7        High    (Registered)
 17.     DE             10       16    8    1        High    (Registered)
 18.     VS              6        8    8    2        High    (Registered)
 19.     HS              2        0    8    2        High    (Registered)
                                    ---- ----
                                      64   14  (22%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 10 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L0032 01 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L0256 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 01 *
L0288 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 10 *
L0512 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 *
L0768 11 11 11 11 10 11 11 11 10 11 01 11 10 11 11 11 *
L0800 11 11 11 11 10 11 11 11 10 11 01 11 01 11 11 11 *
L0832 11 11 11 11 10 11 11 11 01 11 10 11 01 11 11 11 *
L0864 11 11 11 11 01 11 11 11 10 11 10 11 01 11 11 11 *
L0896 11 11 11 11 01 11 11 11 01 11 01 11 01 11 11 11 *
L0928 11 11 11 11 01 11 11 11 11 11 10 11 10 11 11 11 *
L0960 11 11 11 11 11 11 11 11 01 11 10 11 10 11 11 11 *
L1024 10 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1056 01 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2048 11 11 11 11 00 11 10 01 00 11 00 00 00 11 00 00 *
L2080 00 11 00 11 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 01 11 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 01 *
C40FF*

I202  5/30/13  7:20 pm  (Thursday)
I203  Memory usage 6K
I204  Elapsed time 1 second