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||      FILE:   #0000.PLD
||      PROJ:   20120607        
||      PART:   G26CV12-#0000
||
||      DEV :   PALCE26V12
||
||      DESC:   CONTROLLER DMA/FDC
||
|
|P26V12
|
|| INPUT
|  1:PHI2, 2:RW, 3:PHI0, 4:CX2, 5:DMA, 6:FDC, 8:WD, 9:WF, 10:MW0, 
| 11:AEN, 12:OE, 13:EN, 14:RDY, 28:-,
|| OUTPUT 
|  15:DBE, 16:CS0, 17:CS1, 18:CS2, 19:IOR, 20:IOW, 22:MRD, 23:MWE,
|  24:CS3, 25:J, 26:PHI2N, 27:K
|
| ACTIVE-LOW: DBE, CS0, CS1, IOR, IOW, MRD, MWE, CS3, J, PHI2N 
|
|
| SIGNATURE: "0000    "
|
|| --------------------------------------------------------
|| SEGNALI COMANDO FLIP-FLOP WAIT
|  PHI2N = PHI2
|| ABILITAZIONE WAIT
|  WTX  = ((DMA' & WD') # (FDC' & WF'))
|| COMANDO J,K
|  DATA = (RDY # WTX')
|  J    = DATA
|  K    = DATA
||
|| --------------------------------------------------------
|| CHIP SELECT RAM, DMA & FDC VALIDI SOLO SE AEN = 0
|  DMAA = (DMA' & AEN')
|  FDCA = (FDC' & AEN')
|  CX2A = (CX2' & AEN')
|  CS0  = DMAA
|  CS1  = FDCA
|  CS2  = FDCA
||
|| --------------------------------------------------------
|| SEGNALI UM8388 RD, WR (FDC)
|| RD, WR SINCRONIZZATI CON PHI2 (WF = 1)
|  UMR1 = (FDCA & WF  & RW  & PHI2)
|  UMW1 = (FDCA & WF  & RW' & PHI2)
|| RD, WR SINCRONIZZATI CON EN (WF = 0)
|  UMR2 = (FDCA & WF' & RW  & EN)
|  UMW2 = (FDCA & WF' & RW' & EN)
|  UMRD   = (UMR1 # UMR2)
|  UMWE   = (UMW1 # UMW2)
||
|| --------------------------------------------------------
|| SEGNALI 82C37 RD, WR (DMA)
|| RD, WR SINCRONIZZATI CON PHI2 (WD = 1)
|  DMR1 = (DMAA & WD  & RW  & PHI2)
|  DMW1 = (DMAA & WD  & RW' & PHI2)
|| RD, WR SINCRONIZZATI CON EN (WD = 0)
|  DMR2 = (DMAA & WD' & RW  & EN)
|  DMW2 = (DMAA & WD' & RW' & EN)
|  DMRD   = (DMR1 # DMR2)
|  DMWE   = (DMW1 # DMW2)
||
|| --------------------------------------------------------
|| SEGNALI RD,WR,MRD,MWR 3 STATI PER DMA
|| XAE attiva uscita 3-stati se LOW
|  IORD = (DMRD # UMRD)
|  IOWR = (DMWE # UMWE)
|  MEMRD = (CX2' & RW  & PHI2 & OE)
|  MEMWRA = (CX2' & RW' & PHI2 & MW0  & OE)
|  MEMWRB = (CX2' & RW' & PHI0 & MW0' & OE)
|  MEMWR = (MEMWRA # MEMWRB)
|  IOR = AEN' ?? IORD
|  IOW = AEN' ?? IOWR
|  MRD = AEN' ?? MEMRD
|  MWE = AEN' ?? MEMWR
|| --------------------------------------------------------
|| SELEZIONE SHARED RAM
|| DMA ATTIVO - RAM SEMPRE SELEZIONATA
|  CEA = (OE')
|| DMA INATTIVO
|  CEB = (CX2' & OE & PHI2)
|  CS3 = (CEA # CEB)
||
|| --------------------------------------------------------
|| ABILITAZIONE BUFFER DATI BUS DMA
|  FDCZ1 = (FDCA & WF & PHI2)
|  FDCZ2 = (FDCA & WF' & EN)
|  DMAZ1 = (DMAA & WD & PHI2)
|  DMAZ2 = (DMAA & WD' & EN)
|  DBE = (FDCZ1 # FDCZ2 # DMAZ1 # DMAZ2 # (CX2A & PHI2))