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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0050.PLD)

  1  || FILE:   #0050.PLD
  2  || PROJ:   20120601        
  3  || PART:   G22V10-#0050
  4  ||
  5  || DEV :   GAL22V10
  6  ||
  7  ||         DESC:   MASTER CLOCK
  8  ||
  9  |
 10  |GAL22V10
 11  |
 12  || INPUT
 13  |  1:CLK, 2:PD, 3:F2, 4:S0, 5:VPA, 6:VDA, 7:RES, 8:P2IN, 9:P1IN, 10:P0IN,
 14  |  11:P4IN, 13:RDY,
 15  || OUTPUT 
 16  |  14:P2O, 15:Q0, 16:Q1, 17:Q2, 18:VMA, 19:ALE, 20:GOE, 
 17  |  21:PHI1, 22:PHI0, 23:P4O
 18  |
 19  | ACTIVE-LOW: VMA
 20  |
 21  | SIGNATURE: "0050    "
 22  |
 23  || P2O -> CLOCK 02 CPU
 24  || CONNETTERE P0IN CON PHI0
 25  || CONNETTERE P1IN CON PHI1
 26  || CONNETTERE P4IN CON P4O
 27  ||
 28  || Q0 = 8M, Q1 = 4M, Q2 = 2M  
 29  |  Q[2..0] = CLK // Q[2..0] + 1 
 30  |  A = Q2 & F2'            || 2MHz
 31  |  B = Q1 & F2             || 4MHz
 32  |  PHI0 = (A # B)  || FASE 0
 33  |  P4O = P0IN              || FASE 0 RITARDATA
 34  || P0IN -> FASE 0 RITARDO T  (PD = 1)
 35  || P4IN -> FASE 0 RITARDO 2T (PD = 0)
 36  |  P2O = ((P0IN & PD) # (P4IN & PD'))
 37  |  PHI1 = P2IN'            || FASE 1 RITARDATA RISPETTO A PHI2
 38  |  VMA  = ((VDA & RES) # (VPA & RES))
 39  |  ALE    = (RDY & P0IN' & P2IN')
 40  |  DBEA   = (RDY & P2IN' & S0)
 41  |  DBEB   = (RDY & P1IN  & S0')
 42  |  GOE    = (DBEA # DBEB)



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/5/12  7:07 pm  (Thursday)
I203  Memory usage 81K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0050.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

Q2                84   Q0  Q1  Q2' 
                  85   Q0' Q2  
                  86   Q1' Q2  

Q1                99   Q0' Q1  
                 100   Q0  Q1' 

Q0               112   Q0' 

PHI0              11   F2' Q2  
                  12   F2  Q1  

P4O                2   P0IN  

P2O              123   PD' P4IN  
                 124   PD  P0IN  

PHI1              22   P2IN' 

VMA               67   VPA  RES  
                  68   VDA  RES  

ALE               50   P2IN' P0IN' RDY  

GOE               35   S0' P1IN  RDY  
                  36   S0  P2IN' RDY  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     CLK             0        -    -    -        High    (Clock)
  2.     PD              4        -    -    -        High     
  3.     F2              8        -    -    -        High     
  4.     S0             12        -    -    -        High     
  5.     VPA            16        -    -    -        High     
  6.     VDA            20        -    -    -        High     
  7.     RES            24        -    -    -        High     
  8.     P2IN           28        -    -    -        High     
  9.     P1IN           32        -    -    -        High     
 10.     P0IN           36        -    -    -        High     
 11.     P4IN           40        -    -    -        High     
 13.     RDY            42        -    -    -        High     
 14.     P2O            38      122    9    2        High    (Three-state)
 15.     Q0             35      111   11    1        High    (Registered)
 16.     Q1             31       98   13    2        High    (Registered)
 17.     Q2             27       83   15    3        High    (Registered)
 18.     VMA            23       66   17    2        Low     (Three-state)
 19.     ALE            18       49   17    1        High    (Three-state)
 20.     GOE            14       34   15    2        High    (Three-state)
 21.     PHI1           10       21   13    1        High    (Three-state)
 22.     PHI0            6       10   11    2        High    (Three-state)
 23.     P4O             2        1    9    1        High    (Three-state)
 25.     -               -        0    1    0                 
 26.     -               -      131    1    0                 
                                    ---- ----
                                     132   17  (13%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       PAL22V10
*
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 10 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 *
L0528 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 01 11 11 11 11 01 *
L1584 11 11 11 11 11 11 01 11 11 11 11 11 11 11 10 11 11 11 11 11 11 01 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 10 11 11 01 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 11 11 11 11 11 11 01 11 11 11 01 11 11 11 11 11 11 11 11 11 *
L2992 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 11 11 11 11 11 11 11 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 10 11 11 11 11 *
L3740 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 01 11 11 11 11 *
L3784 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 11 11 11 11 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 11 11 11 *
L4400 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 11 11 11 *
L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4928 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 *
L5368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5412 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L5456 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L5808 11 11 11 11 11 01 10 10 10 11 *
C8E7A*

I202  7/5/12  7:08 pm  (Thursday)
I203  Memory usage 7K
I204  Elapsed time 1 second