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Tue Jul 17 11:11:08 2018 Page 12500 A.D. 65816 Macro Assembler #26960 - Version 5.02g-----------------------------------------------------Input Filename : src\F8\start.asmOutput Filename : obj\F8\start.objListing Has Been Relocated2596 .LIST on25972598 F8FE00 .INCLUDE inc\dirp00.inc2599 ;----------------------------------------------------------2600 ; DIRP00.ASM2601 ; PROGETTO: B16012602 ;2603 ; Variabili in Direct Page $002604 ;----------------------------------------------------------26052606 ; sezione COMMON -- questo permette di includere il file in piu' file26072608 .LIST on26092610 DIRP00: .SECTION page0, ref_only, common ;Direct-Page 0026112612 000000 .ABSOLUTE ;; inizia sempre da $002613 000000 .ORG 0x002614 0000002615 000000 0000 JiffyClk .DW ; contatore 10ms 32 bit2616 000002 0000 .DW2617 000004 SysTmr .DS SYSTMRCNT ; system timer 0 (10ms)2618 000008 SysTMF .DS SYSTMRCNT ; flag timer (80 -> start)2619 00000C 00 Bnk0Flag .DB ; <7>: flag test RAM banco 0 ok2620 ; <6>: flag warm reset2621 00000D 00 RTCFlag .DB26222623 00000E diskstat .DS 2 ; flag device on ata bus #0 & #12624 ; <7>: device ready2625 ; <6>: compact flash device (C.F.)2626 ; <5>: device identification ok2627 ; <4>: MBR loaded2628 ; <3>: valid signature in MBR2629 ; <2>: first partition found&active2630 ; <1>:2631 ; <0>: valid partition flag26322633 ; <7>: device ready2634 ; <6>: USB device2635 ; <5>: compact flash device (C.F.)2636 ; <4>: device identification ok2637 ; <3>: MBR loaded2638 ; <2>: first partition found&active2639 ; <1>: always 12640 ; <0>: valid partition flag2641 000010Tue Jul 17 11:11:08 2018 Page 226422643 00000E atadev .EQU diskstat26442645 000010 usbdev .DS 2 ; flag flash disk on usb bus #02646 ; <7>: device plugged and ready2647 ; <6>: always 12648 ; <5>: device identification ok2649 ; <4>: MBR loaded2650 ; <3>: valid signature in MBR2651 ; <2>: first partition found&active2652 ; <1>:2653 ; <0>: valid partition flag26542655 000012 diskmax .DS 16 ; disk max. sector's2656 000012 atasec .EQU diskmax2657 00001A usbsec .EQU diskmax+8265826592660 000022 atambr .DS 8 ; data for first partition found in mbr2661 ; first 3 bytes for start sector of partition2662 ; last byte for partition type2663 00002A usbmbr .DS 826642665 000032 ataprt .DS 8 ; total sec's of first partition2666 00003A usbprt .DS 8 ; total sec's of first partition266726682669 000042 00 usb0ch .DB ; usb0 (ch375/ch376) flag2670 ; <7>: module on2671 ; <6>: ch376 flag2672 ; <5:0>: chip version26732674 000043 00 usb0st .DB ; usb0 status2675 ; <7>: usb0 host mode ok2676 ; <6>: flash disk attached flag2677 ; <5>: usb device attached26782679 000044 00 fdcdrv .DB ; phisycal drive status (drive #0)2680 ; <7>: disk format established in bit 0&12681 ; <6>: double step seek done2682 ; <5>: trust format bit's (set after ok r/w)2683 ; <4>: write protect bit (if disk in drive)2684 ; <3>: don't care2685 ; <2>: don't care2686 ; <1>: HD disk if set else DD disk2687 ; <0>: CBM format if set else IBM format26882689 000045 00 vdrive .DB ; virtual drive status (ram disk, drive #1)2690 ; <7>: disk format established in bit 0&12691 ; <6>: change disk simulation (after format)2692 ; <5>: don't care2693 ; <4>: write protect bit (under sw control)2694 ; <3>: don't care2695 ; <2>: don't care2696 ; <1>: HD disk if set else DD disk2697 ; <0>: CBM format if set else IBM format2698Tue Jul 17 11:11:08 2018 Page 32699 000046 00 fdcctl .DB ; fdc controller status2700 ; <7>: drive is attached2701 ; <6>: drive need recalibration (restore)2702 ; <5>: FDC controller ok2703 ; <4>: motor on2704 ; <3>: dma is active2705 ; <2>: dma chip ok (post routine)2706 ; <1>: clock rate (1=HD,0=DD)2707 ; <0>: disk ready27082709 000047 00 fdctrk .DB ; fd: current seek track2710 000048 00 fdcerr .DB ; fd: last error code2711 000049 00 ataerr .DB ; ata: last error code2712 00004A 00 ataxer .DB ; ata: last extended error code27132714 00004B 00 CtrlBrk .DB ; flag CTRL+BREAK (NMI)27152716 00004C 0000 MemTop .DW ; top memoria RAM2717 00004E 00 .DB ; banco top mem27182719 00004F 00 DflTxtIn .DB ; device di default text input2720 000050 00 DflTxtOut .DB ; device di default text output27212722 000051 COPPtr LP ; long pointer for COP decoding2723 000054 00 COPIdx .DB ; COP signature/index27242725 000055 00 BiosEnt .DB ; flag accesso a bios setup27262727 ; variabili utilizzate da ACIA2728 000056 spwrk .DS $3027292730 ; bios mem2731 000086 0000 nsize .DW ; dimensione blocco da allocare2732 ;bsize .DW ; dimensione vera blocco free2733 000088 0000 splitsz .DW ; dimensione blocco splittato2734 00008A 0000 bfree .DW ; puntatore blocco free2735 00008C 0000 hdrptr .DW ; puntatore header heap27362737 00008E 0000 pbrklv .DW ; current break level of current process2738 000090 0000 pbrkmin .DW ; minimum breal level of current process2739 000092 0000 pbrkmax .DW ; maximum breal level of current process2740 0000942741 ; bios temp. work area2742 000094 bwrktmp .DS $2827432744 0000BC 00 coptmp .DB ; temp. used while cop27452746 0000BD 00 tstser .DB ; check ser/usb test board post2747 ; <7>: VIA2 ok2748 ; <6>: PICRAM ok2749 ; <1>: UART 16C550 ok2750 ; <0>: R65C51 ok275127522753 ;crc16 .DW27542755 0000BD .RELATIVETue Jul 17 11:11:08 2018 Page 427562757 .ENDS27582759 [01] .IFDEF _ACIA_INC_2760 F8FE00 .INCLUDE INC\SP.INC2761 ;;2762 ;; Copyright (c) 2016 Marco Granati <mg@unet.bz>2763 ;;2764 ;; Permission to use, copy, modify, and distribute this software for any2765 ;; purpose with or without fee is hereby granted, provided that the above2766 ;; copyright notice and this permission notice appear in all copies.2767 ;;2768 ;; THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES2769 ;; WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF2770 ;; MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR2771 ;; ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES2772 ;; WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN2773 ;; ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF2774 ;; OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.2775 ;;27762777 ;; name: sp.inc2778 ;; rev.: 2016/07/282779 ;; bios C816 version v1.027802781 .LIST on27822783 000001 SOH .EQU $012784 000002 STX .EQU $022785 000003 ETX .EQU $032786 000004 EOT .EQU $042787 000005 ENQ .EQU $052788 000006 ACK .EQU $062789 000010 DLE .EQU $102790 000016 SYN .EQU $1627912792 002000 SOBUFSIZ .EQU $2000 ; dimensione coda TX1/TX2 ACIA (8K)2793 ;SOBUFSIZ .EQU $0100 ; dimensione coda TX1/TX2 ACIA (8K)2794 004000 SIBUFSIZ .EQU $4000 ; dimensione coda RX1/RX2 ACIA (16K)2795 ;SIBUFSIZ .EQU $0100 ; dimensione coda RX1/RX2 ACIA (16K)27962797 000080 NGUARD1 .EQU $80 ; numero bytes di guardia buffer RX XON/XOFF2798 000040 NGUARD2 .EQU $40 ; numero bytes di guardia buffer RX handshake2799 ;NGUARD1 .EQU $40 ; numero bytes di guardia buffer RX XON/XOFF2800 ;NGUARD2 .EQU $20 ; numero bytes di guardia buffer RX handshake2801 001000 NFREE1 .EQU $1000 ; minimo posto in coda RX per cancellare pausa remota2802 000800 NFREE2 .EQU $08002803 ;NGUARD3 .EQU $F02804 ;NGUARD4 .EQU $F828052806 ;---------------------------------------------------------------------------2807 ; direct page var's for serial ports handling2808 ;---------------------------------------------------------------------------28092810 DPSP: .SECTION page0, common, ref_only, offset spwrk ;ACIA D.P.28112812 000056 _DPSP_START .DS 0Tue Jul 17 11:11:08 2018 Page 528132814 ; WARNING: not change order and type of the following variables28152816 ; acia 1 var's2817 000056 00 splin .DB ; interrupt status register2818 000057 00 spcsr .DB ; control status register2819 000058 00 spfr .DB ; format register2820 000059 00 spout .DB ; XON/XOFF send flag28212822 ; acia 2 var's2823 00005A 00 splin2 .DB ; interrupt status register2824 00005B 00 spcsr2 .DB ; control status register2825 00005C 00 spfr2 .DB ; format register2826 00005D 00 spout2 .DB ; XON/XOFF send flag28272828 ; serial port's mode & status2829 00005E 00 spmode .DB ; <7>: 0=no handshake, 1=handshake2830 ; <6>: 0=software/1=hardware handshake2831 ; <5>: not used2832 ; <4>: baud rate: 0=19200, 1=384002833 ; <3>: 0=odd parity, 1=even parity2834 ; <2>: 0=no parity, 1=parity as specified2835 ; by bit <3>2836 ; <1>: interface type: 0=RS232, 1=RS4852837 ; <0>: RS232: uplink flow control (RTS/DCD)2838 ; RS485: 120 ohm termination on2839 ; if bit 7=1 and bit 1=1, bit 6 is forced to 02840 00005F2841 00005F 00 spstat .DB ; serial port status2842 ; <7>: rx error (data discarded)2843 ; <6>: rx buffer overflow2844 ; <5>: remote disconnession (DSR line = 1)2845 ; <4>: output buffer overflow2846 ; <3>: not used2847 ; <2>: framing error2848 ; <1>: parity error2849 ; <0>: overrun error28502851 000060 00 sppause .DB ; local/remote pause flag's2852 ; <7>: remote pause (sent an XON or set RTS=1)2853 ; <6>: local pause (received an XON or CTS=1)28542855 000061 00 sptmp .DB ; temp. byte used while get data28562857 ; serial port's mode & status2858 000062 00 spmode2 .DB ; <7>: 0=no handshake, 1=handshake2859 ; <6>: 0=software/1=hardware handshake2860 ; <5>: not used2861 ; <4>: baud rate: 0=19200, 1=384002862 ; <3>: 0=odd parity, 1=even parity2863 ; <2>: 0=no parity, 1=parity as specified2864 ; by bit <3>2865 ; <1>: interface type: 0=RS232, 1=RS4852866 ; <0>: RS232: uplink flow control (RTS/DCD)2867 ; RS485: 120 ohm termination on2868 ; if bit 7=1 and bit 1=1, bit 6 is forced to 02869 000063Tue Jul 17 11:11:08 2018 Page 62870 000063 00 spstat2 .DB ; serial port status2871 ; <7>: rx error (data discarded)2872 ; <6>: rx buffer overflow2873 ; <5>: remote disconnession (DSR line = 1)2874 ; <4>: output buffer overflow2875 ; <3>: not used2876 ; <2>: framing error2877 ; <1>: parity error2878 ; <0>: overrun error28792880 000064 00 sppause2 .DB ; local/remote pause flag's2881 ; <7>: remote pause (sent XOFF/XON or RTS=1/0)2882 ; <6>: local pause (rx XOFF/XON or CTS=0/1)28832884 000065 00 sppost .DB ; after POST must hold $C028852886 000066 0000 ibuftail .DW ; pointer to tail of input buffer2887 000068 0000 ibufhead .DW ; pointer to head of input buffer2888 00006A 0000 ibuftail2 .DW2889 00006C 0000 ibufhead2 .DW28902891 00006E 0000 obuftail .DW ; pointer to tail of output buffer2892 000070 0000 obufhead .DW ; pointer to head of output buffer2893 000072 0000 obuftail2 .DW2894 000074 0000 obufhead2 .DW28952896 000076 0000 ibufcnt .DW ; count of bytes in input buffer2897 000078 0000 obufcnt .DW ; count of bytes in output buffer2898 00007A 0000 ibufcnt2 .DW2899 00007C 0000 obufcnt2 .DW29002901 00007E 0000 icntmin .DW ; min. count for clear remote pause2902 000080 0000 icntmax .DW ; max. count for set remote pause2903 000082 0000 icntmin2 .DW2904 000084 0000 icntmax2 .DW29052906 000086 _DPSP_END .DS 02907 000030 DPSPSIZ .EQU (_DPSP_END - _DPSP_START)290829092910 .ENDS29112912 00005F ACIArxe_1 .EQU spstat2913 000063 ACIArxe_2 .EQU spstat22914 00005E ACIAhsk_1 .EQU spmode2915 000062 ACIAhsk_2 .EQU spmode22916 000060 ACIAPause_1 .EQU sppause2917 000064 ACIAPause_2 .EQU sppause22918 000057 ACIAcsr_1 .EQU spcsr2919 00005B ACIAcsr_2 .EQU spcsr22920 000058 ACIAfr_1 .EQU spfr2921 00005C ACIAfr_2 .EQU spfr22922 000060 ACIAOut_1 .EQU sppause2923 000064 ACIAOut_2 .EQU sppause22924 000076 ACIAICnt_1 .EQU ibufcnt2925 00007A ACIAICnt_2 .EQU ibufcnt22926 000068 ACIAIHead_1 .EQU ibufheadTue Jul 17 11:11:08 2018 Page 72927 00006C ACIAIHead_2 .EQU ibufhead22928 000066 ACIAITail_1 .EQU ibuftail2929 00006A ACIAITail_2 .EQU ibuftail22930 000078 ACIAOCnt_1 .EQU obufcnt2931 00007C ACIAOCnt_2 .EQU obufcnt22932 000070 ACIAOHead_1 .EQU obufhead2933 000074 ACIAOHead_2 .EQU obufhead22934 00006E ACIAOTail_1 .EQU obuftail2935 000072 ACIAOTail_2 .EQU obuftail229362937 002000 ACIAOBUFLEN .EQU SOBUFSIZ2938 004000 ACIAIBUFLEN .EQU SIBUFSIZ2939 050000 ACIAOUTBUF1 .EQU SPOUTBUFF2940 052000 ACIAOUTBUF2 .EQU SPOUTBUFF22941 054000 ACIAINBUF1 .EQU SPINBUFF2942 058000 ACIAINBUF2 .EQU SPINBUFF229432944 000061 ACIATmp .EQU sptmp29452963 .LIST on29642965 000060 KBDBUFLEN .EQU 96 ; dimensione buffer di tastiera29662967 DIRP01: .SECTION page0, ref_only, common ;Direct-Page 0129682969 000000 .ABSOLUTE ;; inizia sempre da $002970 000000 .ORG 0x0029712972 0000002973 000000 KbdBuf .DS KBDBUFLEN ; buffer della tastiera2974 000060 00 KbdITail .DB ; coda buffer tastiera2975 000061 00 KbdIHead .DB ; testa buffer tastiera2976 000062 00 KbdCnt .DB ; numero bytes nel buffer2977 000063 00 KbdShift .DB2978 000064 00 KbdFlag .DB2979 000065 00 KbdToggle .DB2980 000066 00 KbdSt .DB ; status tastiera dopo reset2981 000067 00 PS2Ctl .DB ; flag controller PS2 keyboard29822983 000068 00 LCDFlag .DB2984 000069 00 LCDTmp .DB2985 00006A 0000 LCDVal .DW29862987 00006C 00 VBBFlag .DB ; flag video board2988 00006D 00 VBBRam .DB ; flag video RAM29892990 00006E 00 ScnLinTmp .DB2991 00006F 00 ScnChBase .DB ; base video ram VDC2992 000070 00 ScnAttBase .DB ; base ram attributi VDC2993 000071 00 ScnCursMode .DB ; VDC cursore default2994 000072 00 ScnSaveAttr .DB2995 000073 00 ScnInsert .DB2996 000074 00 ScnAutoIns .DB ; bit 7 -> autoins - bit 6 -> modo input2997 000075 00 ScnScroll .DB2998 000076 00 ScnMaxRow .DB ; max. righe finestra (-1)2999 000077 00 ScnMaxCols .DB ; max. colonne finestra (-1)3000Tue Jul 17 11:11:08 2018 Page 83001 000078 ScnMapTabs1 .DS 103002 000082 ScnMapTabs2 .DS 43003 0000863004 000086 0000 ScnPtr .DW ; puntatore video ram linea corrente3005 000088 00 .DB30063007 000089 00 ScnFiltLen .DB ; lunghezza set caratteri filtro30083009 00008A 0000 ScnAtPtr .DW ; puntatore attributi ram linea corrente3010 00008C 00 .DB30113012 00008D 00 ScnTmpx .DB ; temporaneo: durante put char3013 00008E3014 00008E 00 ScnTop .DB ; riga superiore finestra3015 00008F 00 ScnLeft .DB ; colonna sinistra finestra3016 000090 00 ScnBottom .DB ; riga inferiore finestra3017 000091 00 ScnRight .DB ; colonna destra finestra3018 000092 00 ScnAttr .DB ; attributo default3019 000093 00 ScnAttr2 .DB ; attributo alternativo3020 000094 00 ScnRow .DB ; riga cursore3021 000095 00 ScnCol .DB ; colonna cursore3022 000096 00 ScnRowStart .DB ; riga di start input3023 000097 00 ScnInput .DB ; riga di fine input3024 000098 00 ScnColStart .DB ; colonna di start input3025 000099 00 ScnSaveX .DB3026 00009A 00 ScnSaveY .DB3027 00009B 00 ScnTmpL .DB3028 00009C 00 ScnTmpH .DB3029 00009D 00 ScnSaveRow .DB3030 00009E 00 ScnSaveCol .DB3031 00009F 00 ScnCurChr .DB3032 0000A0 00 ScnLstChr .DB3033 0000A1 00 ScnCR .DB3034 0000A2 0000 ScnPrm .DW ; puntatore long utilizzato da print imm3035 0000A4 00 .DB ; banco puntatore ScnPrm3036 0000A5 00 ScnMode .DB ; flag modo schermo30373038 0000A6 ScnPtr1 LP30393040 0000A9 00 ScnDefCol .DB ; default foreground color30413042 0000AA ScnPtr2 LP30433044 0000AD 00 ScnDefBkgCol .DB ; default background color3045 0000AE 00 ScnInpRow .DB ; modo input line: riga start input3046 0000AF 00 ScnInpCol .DB ; modo input line: colonna start input3047 0000B0 00 ScnLstRow .DB ; modo input line: riga stop input3048 0000B1 00 ScnLstCol .DB ; modo input line: colonna stop input3049 0000B2 00 ScnFlag .DB ; Bit 7: input line - Bit 6: input riga unica3050 0000B3 00 ScnMask .DB ; flag tasti funzione editor di linea3051 0000B4 00 ScnFilt .DB ; filtro tasti editor di linea3052 0000B5 00 ScnCntrl .DB ; flag ASCII/CONTROL3053 ;DflTxtIn .DB ; device di default text input3054 ;DflTxtOut .DB ; device di default text output3055 0000B63056 000047 SCNCLRLEN .EQU ($ - ScnLinTmp - 1)3057Tue Jul 17 11:11:08 2018 Page 93058 ;SCNCLRLEN .EQU (DflTxtOut - ScnLinTmp)30593060 ; variabili monitor3061 0000B6 00 SMAddrL .DB ; address low/high3062 0000B7 00 SMAddrH .DB3063 0000B8 00 SMAddrK .DB ; address bank3064 0000B9 00 SMFlag32 .DB ; flag parametro 32 bit3065 0000BA 00 SMTmpL .DB ; temp. low/high3066 0000BB 00 SMTmpH .DB3067 0000BC 00 SMTmpK .DB ; temp. bank3068 0000BD 00 SMTmpKK .DB ; high byte param. 32 bit3069 0000BE 00 SMSizeL .DB ; size low/high3070 0000BF 00 SMSizeH .DB3071 0000C0 00 SMSizeK .DB ; size bank3072 0000C1 00 SMXAddrL .DB ; address low/high XM3073 0000C2 00 SMXAddrH .DB3074 0000C3 00 SMXAddrK .DB ; address bank XM3075 0000C4 00 SMbndx .DB ; indice input buffer3076 0000C5 00 SMnprm .DB ; numero parametri riga di comando3077 0000C6 00 SMdumb .DB3078 0000C7 00 SMkr .DB3079 0000C8 0000 SMpc .DW3080 0000CA 00 SMsr .DB3081 0000CB 00 SMbr .DB3082 0000CC 0000 SMdp .DW3083 0000CE 0000 SMac .DW3084 0000D0 0000 SMxr .DW3085 0000D2 0000 SMyr .DW3086 0000D4 0000 SMsp .DW30873088 0000D6 00 SMAuxL .DB3089 0000D7 00 SMAuxH .DB30903091 0000D8 00 asmlong .DB ; flag for CPU in 16 mode3092 ; <7> -> A/M in 16 bit mode3093 ; <6> -> X/Y in 16 bit mode3094 0000D9 00 asmcpu .DB ; <7> -> 8 bit family3095 ; <6> -> 65C02 cmos version30963097 0000DA 00 SMctx .DB ; context (if = $00 no quit command)3098 0000DB SMrsm LP ; long pointer to resume caller context30993100 0000DE 00 rtcadr .DB ; rtc internal ram address3101 0000DF 00 rtcbnk .DB ; RTC internal bank ram3102 0000E0 00 cmdlin .DB ;3103 0000E1 00 SMesc .DB31043105 0000E2 SMXTmp: .DS 26 ; 26 bytes tmp31063107 0000E2 SMTmp2 .EQU SMXTmp3108 0000E4 SMTmp3 .EQU SMXTmp+23109 0000E6 SMdwTmp1 .EQU SMXTmp+43110 0000EA SMdwTmp2 .EQU SMXTmp+83111 0000EE SMFsrc .EQU SMXTmp+12 ; source bank for flash update3112 0000EF SMFflag .EQU SMXTmp+13 ; flag file for flash update3113 0000F0 SMXPos2 .EQU SMXTmp+143114 0000F1 SMYPos2 .EQU SMXTmp+15Tue Jul 17 11:11:08 2018 Page 103115 0000F2 SMXPos3 .EQU SMXTmp+163116 0000F3 SMYPos3 .EQU SMXTmp+173117 ;SMAuxL .EQU SMXTmp+183118 ;SMAuxH .EQU SMXTmp+193119 0000F6 SMXPos .EQU SMXTmp+203120 0000F7 SMYPos .EQU SMXTmp+213121 0000F8 SMdwTmp3 .EQU SMXTmp+2231223123 0000E2 atcmd .EQU SMXTmp ; save @ command3124 0000E3 atnum .EQU SMXTmp+1 ; @ command index3125 0000E4 atflag .EQU SMXTmp+2 ; @ L,S,V,R,W start address flag3126 0000E5 atbnk .EQU SMXTmp+3 ; @ L,S,V,R,W bank3127 0000E6 atstr .EQU SMXTmp+4 ; @ command string start (word)3128 0000E8 atstart .EQU SMXTmp+6 ; @ L,S,V,R,W start address (word)3129 0000EA atend .EQU SMXTmp+8 ; @ S,W end address (word)3130 0000EC atbuf .EQU SMXTmp+10 ; @ local buffer pointer (word)3131 0000EE atipb .EQU SMXTmp+12 ; @ bank of input buffer3132 0000EF atdir .EQU SMXTmp+13 ; @ load dir flag3133 0000F0 atptr .EQU SMXTmp+14 ; @ load dir pointer (word)3134 0000F2 atsiz .EQU SMXTmp+16 ; @ buffer size (word)3135 0000F5 atlp .EQU SMXTmp+19 ; @ long pointer3136 0000F8 atsa .EQU SMXTmp+22 ; @ sa31373138 0000E2 btmpx .EQU SMXTmp ; asc2bin conversion3139 0000E3 brtcsec .EQU SMXTmp+13140 0000E4 brtcmin .EQU SMXTmp+23141 0000E5 brtchour .EQU SMXTmp+33142 0000E6 brtcday .EQU SMXTmp+43143 0000E7 brtcmonth .EQU SMXTmp+53144 0000E8 brtcyear .EQU SMXTmp+63145 0000E9 brtcct .EQU SMXTmp+7314631473148 0000FC .RELATIVE31493150 .ENDS31513175 .LIST on31763177 05C000 SOBUFADDR3 .EQU SPOUTBUFF33178 05D000 SIBUFADDR3 .EQU SPINBUFF33179 001000 SOBUFSIZ3 .EQU $10003180 001000 SIBUFSIZ3 .EQU $100031813182 060000 SOBUFADDR4 .EQU SPOUTBUFF43183 068000 SIBUFADDR4 .EQU SPINBUFF43184 ;SOBUFSIZ4 .EQU $10003185 ;SIBUFSIZ4 .EQU $10003186 008000 SOBUFSIZ4 .EQU $80003187 008000 SIBUFSIZ4 .EQU $800031883189 000200 NGUARD31 .EQU $0200 ; numero bytes di guardia buffer RX XON/XOFF3190 000100 NGUARD32 .EQU $0100 ; numero bytes di guardia buffer RX handshake3191 000800 NFREE31 .EQU $0800 ; minimo posto in coda RX per cancellare pausa remota3192 000400 NFREE32 .EQU $040031933194 ;---------------------------------------------------------------------------Tue Jul 17 11:11:08 2018 Page 113195 ; direct page var's for test serial ports/usb handling3196 ;---------------------------------------------------------------------------31973198 DPSP2: .SECTION page0, common, ref_only ;UART D.P.31993200 000000 00 usbslv .DB ; <7>: plugged-in, <6>: plug-in pending3201 000001 00 usbum .DB ; <7>: pending message, <6>: connected3202 000002 00 usbcnt1 .DB ; timeout UM245 plug-in detection3203 000003 usbbuf .DS 83204 00000B 00 usbtim .DB3205 00000C 00 usbcnt .DB3206 00000D 00 usbmst .DB3207 00000E 0000 usbsiz .DW3208 000010 usbptr LP3209 000013 00 usbtmp .DB3210 000014 00 usbcmp .DB32113212 ; serial port 65C513213 000015 00 spmode3 .DB ; <7>: 0=no handshake, 1=handshake3214 ; <6>: 0=software/1=hardware handshake3215 ; <5>: not used3216 ; <4>: not used3217 ; <3>: 0=odd parity, 1=even parity3218 ; <2>: 0=no parity, 1=parity as specified3219 ; by bit <3>3220 ; <1:0> : baud rate3221 ; 00 = 192003222 ; 01 = 384003223 ; 10 = 576003224 ; 11 = 1152003225 0000163226 000016 00 splin3 .DB ; <7>: /CTS line level3227 ; <6>: /DSR line status3228 0000173229 000017 00 sppause3 .DB3230 000018 00 spout3 .DB3231 000019 00 spstat3 .DB ; staus3232 ; <7>: rx error (data discarded)3233 ; <6>: rx buffer overflow3234 ; <5>: remote disconnession (/DSR line = 1)3235 ; <4>: output buffer overflow3236 ; <3>: not used3237 ; <2>: framing error3238 ; <1>: parity error3239 ; <0>: overrun error32403241 00001A 00 sptmp3 .DB32423243 00001B 0000 ibuftail3 .DW3244 00001D 0000 ibufhead3 .DW3245 00001F 0000 obuftail3 .DW3246 000021 0000 obufhead3 .DW3247 000023 0000 ibufcnt3 .DW3248 000025 0000 obufcnt3 .DW3249 000027 0000 icntmin3 .DW3250 000029 0000 icntmax3 .DW3251Tue Jul 17 11:11:08 2018 Page 123252 ; serial port 16C5503253 00002B 00 spmode4 .DB ; <7>: 0=no handshake, 1=handshake3254 ; <6>: 0=software/1=hardware handshake3255 ; <5>: not used3256 ; <4>: not used3257 ; <3>: 0=odd parity, 1=even parity3258 ; <2>: 0=no parity, 1=parity as specified3259 ; by bit <3>3260 ; <1:0> : baud rate3261 ; 00 = 192003262 ; 01 = 384003263 ; 10 = 576003264 ; 11 = 1152003265 00002C3266 00002C 00 splin4 .DB ; <7>: /DSR line level3267 ; <6>: /CTS line status3268 00002D3269 00002D 00 sppause4 .DB3270 00002E 00 spout4 .DB3271 00002F 00 spstat4 .DB ; staus3272 ; <7>: rx error (data discarded)3273 ; <6>: rx buffer overflow3274 ; <5>: remote disconnession (/DSR line = 1)3275 ; <4>: output buffer overflow3276 ; <3>: break3277 ; <2>: framing error3278 ; <1>: parity error3279 ; <0>: overrun error32803281 000030 00 sptmp4 .DB32823283 000031 0000 ibuftail4 .DW3284 000033 0000 ibufhead4 .DW3285 000035 0000 obuftail4 .DW3286 000037 0000 obufhead4 .DW3287 000039 0000 ibufcnt4 .DW3288 00003B 0000 obufcnt4 .DW3289 00003D 0000 icntmin4 .DW3290 00003F 0000 icntmax4 .DW32913292 000041 00 spcnt4 .DB3293 000042 00 uartlsr .DB3294 000043 00 uartiir .DB32953296 000044 usb0name .DS 3632973298 .ENDS32993305 .LIST on33063307 .CODEF833083309 ;----------------------------------------------------------3310 ; ---- CODICE START & INTERRUPT3311 ;----------------------------------------------------------33123313 .SYSCODETue Jul 17 11:11:08 2018 Page 133314 F8F0003315 000162 _KbdCnt .EQU (DP01ADDR + KbdCnt)3316 000165 _KbdToggle .EQU (DP01ADDR + KbdToggle)3317 000166 _KbdSt .EQU (DP01ADDR + KbdSt)3318 000167 _PS2Ctl .EQU (DP01ADDR + PS2Ctl)3319 000160 _KbdITail .EQU (DP01ADDR + KbdITail)3320 000161 _KbdIHead .EQU (DP01ADDR + KbdIHead)3321 000163 _KbdShift .EQU (DP01ADDR + KbdShift)3322 000164 _KbdFlag .EQU (DP01ADDR + KbdFlag)3323 F8F0003324 F8F000 LONG_OFF3325 .LONGA off3326 .LONGI off3327 .MNLIST3328 F8F0003329 .GLOBAL _KbdCnt, _KbdToggle, _KbdSt, _PS2Ctl, _KbdITail3330 .GLOBAL _KbdIHead, _KbdShift, _KbdFlag3331 .GLOBAL TORAM33323333 F8F000 TORAM:3334 ; vettori ISR3335 F8F000 intsr:3336 F8F000 10F0 04F1 F8F1 .DW int0sr, int1sr, int2sr, int3srACF23337 F8F008 D3F3 C9F5 C9F5 .DW int4sr, int5sr, int6sr, int7srCAF533383339 F8F010 int0sr:3340 F8F010 SPISR 03341 [01] .IFZ 03342 000000 k .SET 03343 050000 SOBUFADDR .SET SPOUTBUFF3344 054000 SIBUFADDR .SET SPINBUFF3345 [01] .ELSE3346 k .SET 43347 SOBUFADDR .SET SPOUTBUFF23348 SIBUFADDR .SET SPINBUFF23349 [00] .ENDIF33503351 F8F010 AC 50 FD ldy .ABS.ACIAISR+k ; interrupt status reg. (clear bit 3,4,5)3352 F8F013 AD 51 FD lda .ABS.ACIACSR+k ; control status register3353 ;sty spisr+k ; save interrupt status reg.3354 F8F016 85 57 sta spcsr+k ; save control status reg.3355 F8F018 98 tya ; Y=status reg.3356 F8F019 4A lsr a ; test RDRF bit3357 F8F01A 90 76 bcc ?lin ; go to test control lines3358 F8F01C AE 53 FD ldx .ABS.ACIARDR+k ; fetch rx data (clear int. status bits 0,1,2)3359 F8F01F 24 5F bit spstat+k ; rx error pending?3360 F8F021 30 6F bmi ?lin ; yes, discard received data & test ctr. lines3361 F8F023 29 03 and #00000011B ; 1: overrun/frame error, 2: parity error3362 F8F025 24 57 bit spcsr+k ; test control status reg. bit 7: FE3363 F8F027 10 04 bpl ?nof ; no framing error3364 F8F029 09 04 ora #00000100B ; set framing error bit...3365 F8F02B 29 FE and #$FE ; ...and clear overrun error3366 F8F02D C9 00 ?nof: cmp #03367 F8F02F F0 04 beq ?rxok ; no rx error3368 F8F031 09 80 ora #10000000B ; set rx error bitTue Jul 17 11:11:08 2018 Page 143369 F8F033 80 45 bra ?sst ; set stus reg. & discard received data3370 F8F035 8A ?rxok: txa ; A=received data3371 F8F036 INDEX163372 .MLIST3373 F8F036 C2 10 rep #PXFLAG3374 .LONGI on3375 .MNLIST3376 F8F038 A6 76 ldx ibufcnt+k ; count of bytes stored in input buffer3377 F8F03A 24 5E bit spmode+k ; test if handshake is active3378 F8F03C 10 35 bpl ?chk ; bit 7=0 -> no handshake so check input buff.3379 F8F03E 70 14 bvs ?tst ; bit 6=1 -> hardware handshake3380 F8F040 C9 11 cmp #SPXON ; received an XON control byte?3381 F8F042 D0 06 bne ?xoff ; no, check if received an XOFF3382 F8F044 A9 40 lda #$40 ; received an XON: clear local pause flag3383 F8F046 14 60 trb sppause+k ; bit 6=0 -> local pause off (resume tx)3384 F8F048 80 46 bra ?cnt ; discard received data3385 F8F04A C9 13 ?xoff: cmp #SPXOFF ; received an XOFF control byte?3386 F8F04C D0 06 bne ?tst ; no, check condition for remote pause3387 F8F04E A9 40 lda #$40 ; set local pause flag3388 F8F050 04 60 tsb sppause+k ; bit 6=1 -> local pause on (stop tx operation)3389 F8F052 80 3C bra ?cnt ; discard received data3390 F8F054 E4 80 ?tst: cpx icntmax+k ; check input buff. for remote pause condition3391 F8F056 90 26 bcc ?str ; below guard limit: store data3392 F8F058 24 60 bit sppause+k ; remote pause is already on ?3393 F8F05A 30 17 bmi ?chk ; yes, so check input buffer3394 F8F05C EB xba ; B = received data3395 F8F05D 24 5E bit spmode+k ; test handshake type3396 F8F05F 70 06 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=13397 F8F061 A9 13 lda #SPXOFF ; send an XOFF to remote terminal3398 F8F063 85 59 sta spout+k ; XOFF sending deffered until TDRE is set3399 F8F065 80 0B bra ?xba ; check input buffer3400 F8F067 A5 58 ?rtsh: lda spfr+k ; hardware handshake...3401 F8F069 09 81 ora #10000001B ; ...set RTS=13402 F8F06B 8D 51 FD sta .ABS.ACIAFR+k ; update format register3403 F8F06E A9 80 lda #$80 ; set remote pause3404 F8F070 04 60 tsb sppause+k ; bit 7=1 -> remote pause on3405 F8F072 EB ?xba: xba ; A = received data3406 F8F073 E0 00 40 ?chk: cpx #SIBUFSIZ ; left room in input buffer?3407 F8F076 90 06 bcc ?str ; yes, store received byte3408 F8F078 A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow3409 F8F07A 85 5F ?sst: sta spstat+k ; set status register3410 F8F07C 80 12 bra ?cnt ; discard received data3411 F8F07E E8 ?str: inx ; now store received data3412 F8F07F 86 76 stx ibufcnt+k ; update bytes count3413 F8F081 A6 66 ldx ibuftail+k ; pointer to rx tail queue3414 F8F083 9F 00 40 05 sta >SIBUFADDR,x3415 F8F087 E8 inx ; update tail pointer3416 F8F088 CPU163417 .MLIST3418 F8F088 C2 30 rep #(PMFLAG.OR.PXFLAG)3419 .LONGA on3420 .LONGI on3421 .MNLIST3422 F8F08A 8A txa3423 F8F08B 29 FF 3F and #(SIBUFSIZ-1) ; circular queue3424 F8F08E 85 66 sta ibuftail+k3425 F8F090 ?cnt: CPU08 ; continue...Tue Jul 17 11:11:08 2018 Page 153426 .MLIST3427 F8F090 E2 30 sep #(PMFLAG.OR.PXFLAG)3428 .LONGA off3429 .LONGI off3430 .MNLIST3431 F8F092 A5 57 ?lin: lda spcsr+k ; get control lines status3432 F8F094 29 3B and #00111011B ; mask lines level3433 F8F096 89 08 bit #00001000B ; check DSR line level3434 F8F098 F0 02 beq ?lin2 ; DSR is low3435 F8F09A 09 40 ora #01000000B ; DSR is high3436 F8F09C 0A ?lin2: asl a ; 7:DSR, 6:CTS, 5:DCD, 2:DTR, 1:RTS3437 F8F09D 85 56 sta splin+k ; save lines level3438 ;tya3439 F8F09F 24 5E bit spmode+k ; test for active handshake3440 F8F0A1 10 24 bpl ?cnt2 ; no handshake, so ignore CTS/DCD trans.3441 F8F0A3 50 22 bvc ?cnt2 ; softw. handshake, so ignore CTS/DCD trans.3442 ;bit #00001000B ; change state on DSR line?3443 ;beq ?cts ; no, go to check CTS line3444 ;ldx #00100000B ; remote disconnession flag3445 ;lda #00001000B ; check DSR line level3446 ;bit spcsr+k3447 ;beq ?dsrl ; DSR line at low level3448 ;txa ; remote disconnession3449 ;tsb spstat+k ; set status register3450 ;bra ?cts3451 ;?dsrl: ;txa ; remote terminal ready3452 ;trb spstat+k ; set status register3453 ;?cts:3454 F8F0A5 A5 5E lda spmode+k3455 F8F0A7 4A lsr a ; check if uplink handshake (RTS/DCD control)3456 F8F0A8 98 tya ; A=interrupt status reg.3457 F8F0A9 B0 08 bcs ?dcd ; yes, so check DCD line (uplink cable)3458 F8F0AB 89 20 bit #00100000B ; change state on CTS line?3459 F8F0AD F0 19 beq ?chkt ; no, so check TDRE flag3460 F8F0AF A9 20 lda #00100000B ; check CTS line level3461 F8F0B1 80 06 bra ?lvl3462 F8F0B3 89 10 ?dcd: bit #00010000B ; change state on DCD line?3463 F8F0B5 F0 11 beq ?chkt ; no, so check TDRE flag3464 F8F0B7 A9 10 lda #00010000B ; check DCD line level3465 F8F0B9 A2 40 ?lvl: ldx #$40 ; local pause flag3466 F8F0BB 24 57 bit spcsr+k3467 F8F0BD F0 05 beq ?clp ; CTS (or DCD) = low so clear local pause3468 F8F0BF 8A txa ; CTS (or DCD) = high so set local pause3469 F8F0C0 04 60 tsb sppause+k3470 F8F0C2 80 03 bra ?cnt23471 F8F0C4 8A ?clp: txa3472 F8F0C5 14 60 trb sppause+k3473 F8F0C7 98 ?cnt2: tya3474 F8F0C8 0A ?chkt: asl a ; check TDRE bit3475 F8F0C9 10 11 bpl ?end ; TDRE=0: can't transmit at this time3476 F8F0CB A5 59 lda spout+k ; pending an XON/XOFF sending?3477 F8F0CD F0 13 beq ?cklp ; no... check local pause flag3478 F8F0CF 8D 53 FD sta .ABS.ACIATDR+k ; send XON/XOFF3479 F8F0D2 64 59 stz spout+k ; clear XON/XOFF flag3480 F8F0D4 C9 13 cmp #SPXOFF3481 F8F0D6 F0 05 beq ?srp ; sent an XOFF3482 F8F0D8 A9 80 lda #$80 ; sent an XON: clear remote pause flagTue Jul 17 11:11:08 2018 Page 163483 F8F0DA 14 60 trb sppause+k ; bit 7 = 0 -> remote pause off3484 F8F0DC 60 ?end: rts ; done3485 F8F0DD A9 80 ?srp: lda #$80 ; set remote pause flag3486 F8F0DF 04 60 tsb sppause+k3487 F8F0E1 60 rts3488 F8F0E2 24 60 ?cklp: bit sppause+k ; local pause is set ?3489 F8F0E4 70 F6 bvs ?end ; yes, no tx possible at this time3490 ;bit spcsr+k ; check if remote terminal is ready3491 ;bmi ?end ; not ready, skip tx3492 F8F0E6 INDEX163493 .MLIST3494 F8F0E6 C2 10 rep #PXFLAG3495 .LONGI on3496 .MNLIST3497 F8F0E8 A6 78 ldx obufcnt+k ; count of bytes in output buffer3498 F8F0EA F0 15 beq ?done ; output buffer is empty: nothing to send3499 F8F0EC CA dex ; update count3500 F8F0ED 86 78 stx obufcnt+k3501 F8F0EF A6 70 ldx obufhead+k ; pointer to head of out buffer3502 F8F0F1 BF 00 00 05 lda >SOBUFADDR,x ; get data from output buffer3503 F8F0F5 8D 53 FD sta .ABS.ACIATDR+k ; send data3504 F8F0F8 E8 inx ; update head pointer3505 F8F0F9 CPU163506 .MLIST3507 F8F0F9 C2 30 rep #(PMFLAG.OR.PXFLAG)3508 .LONGA on3509 .LONGI on3510 .MNLIST3511 F8F0FB 8A txa3512 F8F0FC 29 FF 1F and #(SOBUFSIZ-1) ; circular queue3513 F8F0FF 85 70 sta obufhead+k3514 F8F101 ?done: CPU083515 .MLIST3516 F8F101 E2 30 sep #(PMFLAG.OR.PXFLAG)3517 .LONGA off3518 .LONGI off3519 .MNLIST3520 F8F103 60 rts3521 F8F104 .ENDM35223523 F8F104 int1sr:3524 F8F104 SPISR 135253526 .MLIST3527 [01] .IFZ 13528 k .SET 03529 SOBUFADDR .SET SPOUTBUFF3530 SIBUFADDR .SET SPINBUFF3531 [01] .ELSE3532 000004 k .SET 43533 052000 SOBUFADDR .SET SPOUTBUFF23534 058000 SIBUFADDR .SET SPINBUFF23535 [00] .ENDIF35363537 F8F104 AC 54 FD ldy .ABS.ACIAISR+k ; interrupt status reg. (clear bit 3,4,5)3538 F8F107 AD 55 FD lda .ABS.ACIACSR+k ; control status register3539 ;sty spisr+k ; save interrupt status reg.Tue Jul 17 11:11:08 2018 Page 173540 F8F10A 85 5B sta spcsr+k ; save control status reg.3541 F8F10C 98 tya ; Y=status reg.3542 F8F10D 4A lsr a ; test RDRF bit3543 F8F10E 90 76 bcc ?lin ; go to test control lines3544 F8F110 AE 57 FD ldx .ABS.ACIARDR+k ; fetch rx data (clear int. status bits 0,1,2)3545 F8F113 24 63 bit spstat+k ; rx error pending?3546 F8F115 30 6F bmi ?lin ; yes, discard received data & test ctr. lines3547 F8F117 29 03 and #00000011B ; 1: overrun/frame error, 2: parity error3548 F8F119 24 5B bit spcsr+k ; test control status reg. bit 7: FE3549 F8F11B 10 04 bpl ?nof ; no framing error3550 F8F11D 09 04 ora #00000100B ; set framing error bit...3551 F8F11F 29 FE and #$FE ; ...and clear overrun error3552 F8F121 C9 00 ?nof: cmp #03553 F8F123 F0 04 beq ?rxok ; no rx error3554 F8F125 09 80 ora #10000000B ; set rx error bit3555 F8F127 80 45 bra ?sst ; set stus reg. & discard received data3556 F8F129 8A ?rxok: txa ; A=received data3557 F8F12A INDEX163558 .MLIST3559 F8F12A C2 10 rep #PXFLAG3560 .LONGI on3561 .MNLIST3562 F8F12C A6 7A ldx ibufcnt+k ; count of bytes stored in input buffer3563 F8F12E 24 62 bit spmode+k ; test if handshake is active3564 F8F130 10 35 bpl ?chk ; bit 7=0 -> no handshake so check input buff.3565 F8F132 70 14 bvs ?tst ; bit 6=1 -> hardware handshake3566 F8F134 C9 11 cmp #SPXON ; received an XON control byte?3567 F8F136 D0 06 bne ?xoff ; no, check if received an XOFF3568 F8F138 A9 40 lda #$40 ; received an XON: clear local pause flag3569 F8F13A 14 64 trb sppause+k ; bit 6=0 -> local pause off (resume tx)3570 F8F13C 80 46 bra ?cnt ; discard received data3571 F8F13E C9 13 ?xoff: cmp #SPXOFF ; received an XOFF control byte?3572 F8F140 D0 06 bne ?tst ; no, check condition for remote pause3573 F8F142 A9 40 lda #$40 ; set local pause flag3574 F8F144 04 64 tsb sppause+k ; bit 6=1 -> local pause on (stop tx operation)3575 F8F146 80 3C bra ?cnt ; discard received data3576 F8F148 E4 84 ?tst: cpx icntmax+k ; check input buff. for remote pause condition3577 F8F14A 90 26 bcc ?str ; below guard limit: store data3578 F8F14C 24 64 bit sppause+k ; remote pause is already on ?3579 F8F14E 30 17 bmi ?chk ; yes, so check input buffer3580 F8F150 EB xba ; B = received data3581 F8F151 24 62 bit spmode+k ; test handshake type3582 F8F153 70 06 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=13583 F8F155 A9 13 lda #SPXOFF ; send an XOFF to remote terminal3584 F8F157 85 5D sta spout+k ; XOFF sending deffered until TDRE is set3585 F8F159 80 0B bra ?xba ; check input buffer3586 F8F15B A5 5C ?rtsh: lda spfr+k ; hardware handshake...3587 F8F15D 09 81 ora #10000001B ; ...set RTS=13588 F8F15F 8D 55 FD sta .ABS.ACIAFR+k ; update format register3589 F8F162 A9 80 lda #$80 ; set remote pause3590 F8F164 04 64 tsb sppause+k ; bit 7=1 -> remote pause on3591 F8F166 EB ?xba: xba ; A = received data3592 F8F167 E0 00 40 ?chk: cpx #SIBUFSIZ ; left room in input buffer?3593 F8F16A 90 06 bcc ?str ; yes, store received byte3594 F8F16C A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow3595 F8F16E 85 63 ?sst: sta spstat+k ; set status register3596 F8F170 80 12 bra ?cnt ; discard received dataTue Jul 17 11:11:08 2018 Page 183597 F8F172 E8 ?str: inx ; now store received data3598 F8F173 86 7A stx ibufcnt+k ; update bytes count3599 F8F175 A6 6A ldx ibuftail+k ; pointer to rx tail queue3600 F8F177 9F 00 80 05 sta >SIBUFADDR,x3601 F8F17B E8 inx ; update tail pointer3602 F8F17C CPU163603 .MLIST3604 F8F17C C2 30 rep #(PMFLAG.OR.PXFLAG)3605 .LONGA on3606 .LONGI on3607 .MNLIST3608 F8F17E 8A txa3609 F8F17F 29 FF 3F and #(SIBUFSIZ-1) ; circular queue3610 F8F182 85 6A sta ibuftail+k3611 F8F184 ?cnt: CPU08 ; continue...3612 .MLIST3613 F8F184 E2 30 sep #(PMFLAG.OR.PXFLAG)3614 .LONGA off3615 .LONGI off3616 .MNLIST3617 F8F186 A5 5B ?lin: lda spcsr+k ; get control lines status3618 F8F188 29 3B and #00111011B ; mask lines level3619 F8F18A 89 08 bit #00001000B ; check DSR line level3620 F8F18C F0 02 beq ?lin2 ; DSR is low3621 F8F18E 09 40 ora #01000000B ; DSR is high3622 F8F190 0A ?lin2: asl a ; 7:DSR, 6:CTS, 5:DCD, 2:DTR, 1:RTS3623 F8F191 85 5A sta splin+k ; save lines level3624 ;tya3625 F8F193 24 62 bit spmode+k ; test for active handshake3626 F8F195 10 24 bpl ?cnt2 ; no handshake, so ignore CTS/DCD trans.3627 F8F197 50 22 bvc ?cnt2 ; softw. handshake, so ignore CTS/DCD trans.3628 ;bit #00001000B ; change state on DSR line?3629 ;beq ?cts ; no, go to check CTS line3630 ;ldx #00100000B ; remote disconnession flag3631 ;lda #00001000B ; check DSR line level3632 ;bit spcsr+k3633 ;beq ?dsrl ; DSR line at low level3634 ;txa ; remote disconnession3635 ;tsb spstat+k ; set status register3636 ;bra ?cts3637 ;?dsrl: ;txa ; remote terminal ready3638 ;trb spstat+k ; set status register3639 ;?cts:3640 F8F199 A5 62 lda spmode+k3641 F8F19B 4A lsr a ; check if uplink handshake (RTS/DCD control)3642 F8F19C 98 tya ; A=interrupt status reg.3643 F8F19D B0 08 bcs ?dcd ; yes, so check DCD line (uplink cable)3644 F8F19F 89 20 bit #00100000B ; change state on CTS line?3645 F8F1A1 F0 19 beq ?chkt ; no, so check TDRE flag3646 F8F1A3 A9 20 lda #00100000B ; check CTS line level3647 F8F1A5 80 06 bra ?lvl3648 F8F1A7 89 10 ?dcd: bit #00010000B ; change state on DCD line?3649 F8F1A9 F0 11 beq ?chkt ; no, so check TDRE flag3650 F8F1AB A9 10 lda #00010000B ; check DCD line level3651 F8F1AD A2 40 ?lvl: ldx #$40 ; local pause flag3652 F8F1AF 24 5B bit spcsr+k3653 F8F1B1 F0 05 beq ?clp ; CTS (or DCD) = low so clear local pauseTue Jul 17 11:11:08 2018 Page 193654 F8F1B3 8A txa ; CTS (or DCD) = high so set local pause3655 F8F1B4 04 64 tsb sppause+k3656 F8F1B6 80 03 bra ?cnt23657 F8F1B8 8A ?clp: txa3658 F8F1B9 14 64 trb sppause+k3659 F8F1BB 98 ?cnt2: tya3660 F8F1BC 0A ?chkt: asl a ; check TDRE bit3661 F8F1BD 10 11 bpl ?end ; TDRE=0: can't transmit at this time3662 F8F1BF A5 5D lda spout+k ; pending an XON/XOFF sending?3663 F8F1C1 F0 13 beq ?cklp ; no... check local pause flag3664 F8F1C3 8D 57 FD sta .ABS.ACIATDR+k ; send XON/XOFF3665 F8F1C6 64 5D stz spout+k ; clear XON/XOFF flag3666 F8F1C8 C9 13 cmp #SPXOFF3667 F8F1CA F0 05 beq ?srp ; sent an XOFF3668 F8F1CC A9 80 lda #$80 ; sent an XON: clear remote pause flag3669 F8F1CE 14 64 trb sppause+k ; bit 7 = 0 -> remote pause off3670 F8F1D0 60 ?end: rts ; done3671 F8F1D1 A9 80 ?srp: lda #$80 ; set remote pause flag3672 F8F1D3 04 64 tsb sppause+k3673 F8F1D5 60 rts3674 F8F1D6 24 64 ?cklp: bit sppause+k ; local pause is set ?3675 F8F1D8 70 F6 bvs ?end ; yes, no tx possible at this time3676 ;bit spcsr+k ; check if remote terminal is ready3677 ;bmi ?end ; not ready, skip tx3678 F8F1DA INDEX163679 .MLIST3680 F8F1DA C2 10 rep #PXFLAG3681 .LONGI on3682 .MNLIST3683 F8F1DC A6 7C ldx obufcnt+k ; count of bytes in output buffer3684 F8F1DE F0 15 beq ?done ; output buffer is empty: nothing to send3685 F8F1E0 CA dex ; update count3686 F8F1E1 86 7C stx obufcnt+k3687 F8F1E3 A6 74 ldx obufhead+k ; pointer to head of out buffer3688 F8F1E5 BF 00 20 05 lda >SOBUFADDR,x ; get data from output buffer3689 F8F1E9 8D 57 FD sta .ABS.ACIATDR+k ; send data3690 F8F1EC E8 inx ; update head pointer3691 F8F1ED CPU163692 .MLIST3693 F8F1ED C2 30 rep #(PMFLAG.OR.PXFLAG)3694 .LONGA on3695 .LONGI on3696 .MNLIST3697 F8F1EF 8A txa3698 F8F1F0 29 FF 1F and #(SOBUFSIZ-1) ; circular queue3699 F8F1F3 85 74 sta obufhead+k3700 F8F1F5 ?done: CPU083701 .MLIST3702 F8F1F5 E2 30 sep #(PMFLAG.OR.PXFLAG)3703 .LONGA off3704 .LONGI off3705 .MNLIST3706 F8F1F7 60 rts3707 F8F1F8 .ENDM37083709 F8F1F83710 ; gestione IRQ2 - VIA 0 (T1, CA2, CB2, CA1)Tue Jul 17 11:11:08 2018 Page 203711 F8F1F8 int2sr:3712 F8F1F8 AC 0D FD ldy VIA0+VIAIFR ; flag IFR VIA3713 F8F1FB 10 48 bpl ?50 ; no irq da VIA3714 F8F1FD 98 tya ; IFR3715 F8F1FE 0A asl a ; N = bit 6 (T1IFRB)3716 F8F1FF 10 1C bpl ?20 ; no T1 IRQ3717 ;tay3718 F8F201 ACC16 ; A,M -> 16 bit3719 .MLIST3720 F8F201 C2 20 rep #PMFLAG3721 .LONGA on3722 .MNLIST3723 F8F203 E6 00 inc JiffyClk ; incrementa contatore clock 10ms3724 F8F205 D0 02 bne ?023725 F8F207 E6 02 inc JiffyClk+23726 F8F209 ?02: ACC08 ; A,M -> 8 bit3727 F8F209 E2 20 sep #PMFLAG3728 .LONGA off3729 .MNLIST3730 F8F20B A2 03 ldx #SYSTMRCNT-1 ; System Timer (max. 2560ms)3731 F8F20D 34 08 ?04: bit SysTMF,x ; timer attivo ?3732 F8F20F 10 06 bpl ?05 ; no3733 F8F211 D6 04 dec SysTmr,x ; update timer x3734 F8F213 D0 02 bne ?053735 F8F215 74 08 stz SysTMF,x ; cancella timer3736 F8F217 CA ?05: dex3737 F8F218 10 F3 bpl ?043738 F8F21A AD 04 FD lda VIA0+VIAT1CL ; clear flag T13739 F8F21D 98 ?20: tya ; IFR3740 F8F21E 4A lsr a ; C = CA2IFRB3741 F8F21F 90 0B bcc ?30 ; no IRQ CA2 da controller tastiera3742 F8F221 20 46 F2 jsr KbInt ; gestione IRQ tastiera3743 F8F224 A9 01 lda #CA2IFRB ; azzera flag CA23744 F8F226 8D 0D FD sta VIA0+VIAIFR3745 F8F229 8D 46 FD sta KBCLRIRQ ; azzera linea INT3746 F8F22C 98 ?30: tya ; IFR3747 F8F22D 29 08 and #CB2IFRB ; CB2-TMF0 abilitato ?3748 F8F22F 2D 0E FD and VIA0+VIAIER ; e Timer motor spirato ?3749 F8F232 F0 11 beq ?40 ; no3750 F8F234 A9 10 lda #00010000B3751 F8F236 14 46 trb fdcctl ; flag motor off3752 F8F238 A9 0C lda #00001100B3753 F8F23A 8D DA FD sta !FDCDOR ; enable controller, motor off3754 F8F23D A9 08 lda #CB2IFRB ; disabilita CB2-TMF03755 F8F23F 8D 0E FD sta VIA0+VIAIER3756 F8F242 8D 0D FD sta VIA0+VIAIFR ; clear flag CB23757 F8F245 ?40:3758 F8F245 60 ?50: rts3759 F8F2463760 F8F246 KbInt:3761 F8F246 F4 00 01 pea #DP01ADDR ; DP = pagina 13762 F8F249 2B pld3763 F8F24A AE 40 FD ldx KBFR ; primo byte (flag)3764 F8F24D 10 2E bpl ?20 ; bit 7 = 0 -> codice ASCII3765 F8F24F 8A txa3766 F8F250 29 B0 and #$B0 ; maschera 4 bit alti - ignora release (6)3767 F8F252 C9 80 cmp #$80 ; codice FLAG ?Tue Jul 17 11:11:08 2018 Page 213768 F8F254 D0 10 bne ?10 ; no3769 F8F256 8A txa3770 F8F257 29 03 and #$03 ; bit 7 e 6 di KbdShift3771 F8F259 4A lsr a ; C = bit 63772 F8F25A 6A ror a ; C = bit 73773 F8F25B 6A ror a3774 F8F25C 29 C0 and #$C0 ; maschera bit 7,63775 F8F25E 85 63 sta KbdShift3776 F8F260 AD 41 FD lda KBFR+1 ; flag3777 F8F263 85 64 sta KbdFlag3778 F8F265 60 rts3779 F8F266 C9 90 ?10: cmp #$90 ; toggle bit ?3780 F8F268 D0 13 bne ?20 ; no3781 F8F26A AD 41 FD lda KBFR+1 ; toggle bit3782 F8F26D 85 65 sta KbdToggle3783 F8F26F 29 20 and #SCROLLLOCKB ; test SCROLL LOCK BIT3784 F8F271 08 php3785 F8F272 A9 80 lda #$80 ; SCOLL LOCK bit di ScnScroll3786 F8F274 28 plp3787 F8F275 F0 03 beq ?123788 F8F277 04 75 tsb ScnScroll ; disabilita scroll3789 F8F279 60 rts3790 F8F27A 14 75 ?12: trb ScnScroll ; abilita scroll3791 F8F27C 60 rts3792 F8F27D A4 62 ?20: ldy KbdCnt ; test spazio nel buffer3793 F8F27F C0 60 cpy #KBDBUFLEN3794 F8F281 B0 28 bcs ?90 ; no room - scarta tasto3795 F8F283 8A txa3796 F8F284 89 10 bit #$10 ; test 4 bit bassi toggle3797 F8F286 F0 0A beq ?30 ; no toggle3798 F8F288 A9 0F lda #$0F ; azzera 4 bit bassi di KbdToggle3799 F8F28A 14 65 trb KbdToggle3800 F8F28C 8A txa3801 F8F28D 29 0F and #$0F ; 4 bit bassi di KbdToggle3802 F8F28F 04 65 tsb KbdToggle ; imposta 4 bit bassi di KbdToggle3803 F8F291 8A txa3804 ?30: ; inserisce codice tasto nel buffer3805 F8F292 29 C0 and #$C0 ; bit 7 -> ASCII(0) oppure CONTROL(1)3806 ; bit 6 -> MAKE(0) oppure RELEASE(1)3807 F8F294 A6 60 ldx KbdITail ; indice coda buffer3808 F8F296 95 00 sta KbdBuf,x ; inserisce flag tasto3809 F8F298 E8 inx3810 F8F299 AD 41 FD lda KBFR+1 ; codice tasto3811 F8F29C 95 00 sta KbdBuf,x3812 F8F29E E8 inx3813 F8F29F C8 iny ; aggiorna contatore bytes3814 F8F2A0 C8 iny3815 F8F2A1 84 62 sty KbdCnt3816 F8F2A3 E0 60 cpx #KBDBUFLEN ; test coda piena3817 F8F2A5 90 02 bcc ?40 ; no3818 F8F2A7 A2 00 ldx #0 ; coda circolare3819 F8F2A9 86 60 ?40: stx KbdITail ; aggiorna ptr. coda buffer3820 F8F2AB 60 ?90: rts382138223823 ; ISR for VIA2/VIA33824 ; VIA3Tue Jul 17 11:11:08 2018 Page 223825 ; CB2 (neg. edge) : ch375/376 interrupt line3826 ;3827 ; VIA23828 ; CA1 (negative edge) : interrupt from pic usb host3829 ; CA2 (negative edge) : interrupt from UM245R (usb slave)3830 ; CB13831 ; CB2 (pos/neg. edge) : acia CTS sensing3832 ; T1 free-run interrupt3833 F8F2AC int3sr:3834 .EXTERN usbdskon, umgetcmd38353836 F8F2AC AD CD FD lda !VIA3+VIAIFR3837 F8F2AF 10 25 bpl ?via23838 F8F2B1 8D CD FD sta !VIA3+VIAIFR ; clear interrupt flags3839 F8F2B4 89 08 bit #CB2IFRB3840 F8F2B6 F0 1E beq ?via2 ; no usb interrupt3841 F8F2B8 A9 22 lda #CMD_GET_STATUS3842 F8F2BA 8D D1 FD sta usb0cmd3843 F8F2BD EA nop ; 2uS3844 F8F2BE EA nop3845 F8F2BF EA nop3846 F8F2C0 EA nop3847 F8F2C1 AD D0 FD lda usb0dat3848 F8F2C4 C9 16 cmp #USB_INT_DISCONNECT3849 F8F2C6 D0 06 bne ?nxt3850 F8F2C8 A9 7F lda #$7F ; clear all status bits but not bit 73851 F8F2CA 14 43 trb usb0st3852 F8F2CC 80 08 bra ?via2 ; check via23853 F8F2CE C9 15 ?nxt: cmp #USB_INT_CONNECT3854 F8F2D0 D0 04 bne ?via23855 F8F2D2 22 53 B2 F8 jsl usbdskon3856 F8F2D6 F4 00 05 ?via2: pea #DP05ADDR3857 F8F2D9 2B pld3858 F8F2DA AD 1D FC lda !VIA2+VIAIFR3859 F8F2DD 30 01 bmi ?go3860 F8F2DF 60 rts ; no interrupt from VIA33861 F8F2E0 2D 1E FC ?go: and !VIA2+VIAIER ; mask off disbled flags3862 F8F2E3 4A lsr a ; <0>: CA2 int. ?3863 F8F2E4 90 4B bcc ?ca1 ; no, test bit <1>3864 F8F2E63865 ; /RXF line from UM245R request service3866 ; if UM245 is already plugged to usb host then have data on FIFO3867 ; if UM245 was previously unplugged then it assert some pulses3868 ; on /RXF line with dummy data: FF, 1D, 3D, 3D or FF, 3D, 3D3869 ; last two bytes must be 3D 3D3870 ;3871 F8F2E6 A8 tay ; save flags3872 F8F2E7 A2 01 ldx #CA2IFRB ; clear CA2 flag3873 F8F2E9 8E 1D FC stx .ABS.VIA2+VIAIFR3874 F8F2EC 24 00 bit usbslv ; UM245 already plugged to usb host?3875 F8F2EE 30 11 bmi ?umrx ; yes so this is incoming data3876 F8F2F03877 ; sensing a plug in3878 ;3879 F8F2F0 AE 2F FC ldx .ABS.UM245R ; read UM245 port and discard data3880 F8F2F3 24 00 bit usbslv ; first transition?3881 F8F2F5 70 3A bvs ?ca1 ; noTue Jul 17 11:11:08 2018 Page 233882 F8F2F7 A2 40 ldx #$40 ; set usb host pending plug-in flag3883 F8F2F9 86 00 stx usbslv3884 F8F2FB A2 28 ldx #40 ; 600ms timeout3885 F8F2FD 86 02 stx usbcnt13886 ;tya ; restore flags3887 F8F2FF 80 30 bra ?ca1 ; go to test CA1 flag38883889 ?umrx: ; /RXF line low mean data is available from UM245 FIFO3890 ; expect 8 bytes3891 F8F301 A2 00 ldx #03892 F8F303 A9 01 ?umrxl: lda #CA2IFRB ; clear CA2 flag3893 F8F305 8D 1D FC sta !VIA2+VIAIFR3894 F8F308 AD 2F FC lda !UM245R3895 F8F30B 95 03 sta usbbuf,x3896 F8F30D E8 inx3897 F8F30E E0 08 cpx #83898 F8F310 B0 1A bcs ?umrx33899 F8F312 9C 18 FC stz VIA2+VIAT2CL3900 F8F315 9C 19 FC stz VIA2+VIAT2CH3901 F8F318 A9 01 ?umrx2: lda #CA2IFRB ; check CA2 flag3902 F8F31A 2C 1D FC bit VIA2+VIAIFR3903 F8F31D D0 E4 bne ?umrxl3904 F8F31F A9 20 lda #T2IFRB3905 F8F321 2C 1D FC bit VIA2+VIAIFR3906 F8F324 F0 F2 beq ?umrx23907 F8F326 A9 40 lda #$403908 F8F328 14 01 trb usbum3909 F8F32A 80 04 bra ?ca1r39103911 ;?umrx3: bit usbum3912 ; bmi ?setu ; already connected3913 F8F32C3914 ; check connession request3915 ; dex3916 ;?umrx4: lda usbbuf,x3917 ; cmp .ABS.?usbt,x3918 ; beq ?umrx53919 ; lda #$553920 ; sta !UM245R3921 ; bra ?ca1r3922 ;?umrx5: dex3923 ; bpl ?umrx43924 ; lda #$AA3925 ; sta !UM245R3926 ; lda #$803927 ; tsb usbum3928 ; bra ?ca1r3929 ;?setu: lda #$4039303931 F8F32C A9 40 ?umrx3: lda #$403932 F8F32E 04 01 tsb usbum ; set bit <6>: fifo data available3933 F8F330 98 ?ca1r: tya ; restore flag3934 F8F3313935 F8F331 4A ?ca1: lsr a ; <1>: CA1 int.?3936 F8F332 90 0B bcc ?cb2 ; no, test bit <3>3937 F8F3343938 ; this is pic that request a service (usb host)Tue Jul 17 11:11:08 2018 Page 243939 ;3940 F8F334 A8 tay ; save flags3941 F8F335 A9 02 lda #CA1IFRB ; clear CA1 flag3942 F8F337 8D 1D FC sta !VIA2+VIAIFR3943 F8F33A A9 80 lda #$803944 F8F33C 04 0D tsb usbmst ; set usb master flag request3945 F8F33E 98 tya ; restore flag3946 F8F33F3947 F8F33F 4A ?cb2: lsr a ; discard bit <2>3948 F8F340 4A lsr a ; <3>: CB2 int.?3949 F8F341 90 36 bcc ?cb1 ; no, test bit <4>39503951 ; /CTS line of R65C51 changed state (transition)3952 ;3953 F8F343 A8 tay ; save flags3954 F8F344 A9 08 lda #CB2IFRB ; clear CB2 flag3955 F8F346 8D 1D FC sta !VIA2+VIAIFR3956 F8F349 A9 01 lda #$013957 F8F34B 04 16 tsb splin3 ; transition on /CST line3958 F8F34D A2 40 ldx #$403959 F8F34F A9 08 lda #00001000B ; check /CTS line level: PA<3>3960 F8F351 2C 1F FC bit !VIA2+VIAPRANH3961 F8F354 F0 0A beq ?ctsl ; was a negative transition: /CTS is low39623963 ; positive edge transition on /CTS line: /CTS line is high3964 ;3965 F8F356 8A txa3966 F8F357 1C 1C FC trb !VIA2+VIAPCR ; next time sense a negative edge on /CTS line3967 F8F35A A9 80 lda #$803968 F8F35C 04 16 tsb splin3 ; now /CTS line is high3969 F8F35E 80 09 bra ?hsk ; check handshake mode for R65C51 (CF=1 here)3970 F8F3603971 ?ctsl: ; negative edge transition on /CTS line: /CTS line is low3972 ;3973 F8F360 8A txa3974 F8F361 0C 1C FC tsb !VIA2+VIAPCR ; next time sense a positive edge on /CTS line3975 F8F364 A9 80 lda #$803976 F8F366 14 16 trb splin3 ; now /CTS line is low3977 F8F368 18 clc ; CF=0: resume TX39783979 ?hsk: ; if 65C51 is in hardware handshake mode then must handle3980 ; local pause flag and TX interrupt state3981 ;3982 F8F369 24 15 bit spmode3 ; test for active handshake3983 F8F36B 10 0B bpl ?cnt ; no handshake, so ignore CTS trans.3984 F8F36D 50 09 bvc ?cnt ; softw. handshake, so ignore CTS trans.3985 F8F36F 8A txa3986 F8F370 90 04 bcc ?clp ; /CTS low clear local pause and resume TX3987 F8F372 04 17 tsb sppause3 ; /CTS high set local pause and stop TX3988 F8F374 80 02 bra ?cnt3989 F8F376 14 17 ?clp: trb sppause33990 F8F378 98 ?cnt: tya ; restore flag39913992 F8F379 4A ?cb1: lsr a ; <4>: CB1 int.?3993 F8F37A 90 03 bcc ?t1 ; no, test bit <6>3994 F8F37C AE 10 FC ldx .ABS.VIA2+VIAPRB3995 F8F37FTue Jul 17 11:11:08 2018 Page 253996 F8F37F 4A ?t1: lsr a ; discadrd bit <5>3997 F8F380 4A lsr a ; <6>: T1 int.?3998 F8F381 90 47 bcc ?end ; no39994000 ; T1 used for check UM245 /TXE line: if this line is high4001 ; for long time this mean that usb host was unplugged,4002 ; and used for check /DSR line when ACIA interrupt is disabled4003 ; T1 timeout = 15ms4004 F8F383 AD 14 FC lda !VIA2+VIAT1CL ; clear T1 flag4005 F8F386 24 00 bit usbslv ; plug-in pending?4006 F8F388 50 08 bvc ?t2 ; no4007 F8F38A C6 02 dec usbcnt1 ; update counter4008 F8F38C D0 04 bne ?t2 ; timeout not expired4009 F8F38E A9 80 lda #$804010 F8F390 85 00 sta usbslv ; assume UM245 plugged-in4011 F8F392 AD 2A FC ?t2: lda !ACIACMD4012 F8F395 4A lsr a ; check bit <0>4013 F8F396 B0 0F bcs ?usb ; ACIA interrupt is enabled4014 F8F398 AD 29 FC lda !ACIASR ; is safe to read ACIA status now4015 F8F39B 29 40 and #01000000B ; mask off all bits but /DSR4016 F8F39D F0 04 beq ?dsr ; clear /DSR flag4017 F8F39F 04 16 tsb splin3 ; set /DSR flag4018 F8F3A1 80 04 bra ?usb4019 F8F3A3 A9 40 ?dsr: lda #$404020 F8F3A5 14 16 trb splin34021 F8F3A7 24 00 ?usb: bit usbslv4022 F8F3A9 10 15 bpl ?txel ; usb unplugged: nothing to do4023 F8F3AB 2C 1F FC bit !VIA2+VIAPRANH ; check /TXE4024 F8F3AE 50 10 bvc ?txel ; /TXE is low: clear timeout4025 F8F3B0 A5 0B lda usbtim ; timeout started?4026 F8F3B2 D0 06 bne ?dec ; yes, update counter4027 F8F3B4 A9 2C lda #44 ; set 660ms (44 x 15) timeout4028 F8F3B6 85 0B sta usbtim4029 F8F3B8 80 10 bra ?end4030 F8F3BA C6 0B ?dec: dec usbtim ; update counter4031 F8F3BC D0 0C bne ?end ; no timeout4032 F8F3BE 64 00 stz usbslv ; assume cable unplugged4033 F8F3C0 64 0B ?txel: stz usbtim ; clear any pending timeout4034 F8F3C24035 ;?umrx: ldx usbcnt4036 ;?lp1: lda !VIA2+VIAPRA ; check /RXF line4037 ; cmp !VIA2+VIAPRA4038 ; bne ?lp14039 ; tay4040 ; asl a4041 ; bcs ?xx4042 ; lda !UM245R ; read um245 port4043 ; sta !$8000,x4044 ; tya4045 ; sta !$8100,x4046 ; inx4047 ;?xx: stx usbcnt40484049 F8F3C2 24 01 bit usbum4050 F8F3C4 50 04 bvc ?end4051 F8F3C6 22 5E 0E F8 jsl umgetcmd4052 F8F3CA ?end:Tue Jul 17 11:11:08 2018 Page 264053 F8F3CA 60 rts40544055 F8F3CB 87 E9 5D 93 B7 ?usbt: .DB $87, $E9, $5D, $93, $B7, $57, $7D, $3B57 7D 3B40564057 ; serial test board interrupt from 16C550 & 65C514058 F8F3D3 int4sr:4059 F8F3D3 F4 00 05 pea #DP05ADDR4060 F8F3D6 2B pld4061 F8F3D7 AD 29 FC lda !ACIASR4062 F8F3DA 30 03 bmi ?acia4063 F8F3DC 4C B8 F4 jmp uartisr ; 16C550 interrupt?4064 F8F3DF 89 08 ?acia: bit #ACIARDRF ; rx data?4065 F8F3E1 F0 6F beq ?lin ; no, check lines4066 F8F3E3 A8 tay ; Y = status4067 F8F3E4 AE 28 FC ldx .ABS.ACIADR ; X = received data4068 F8F3E7 29 07 and #00000111B ; any rx error pending?4069 F8F3E9 F0 0B beq ?rx ; no4070 F8F3EB 0A asl a ; translate overrun (bit 3) to bit 04071 F8F3EC 89 08 bit #00001000B ; test overrun4072 F8F3EE F0 02 beq $+4 ; skip next instruction if not overrun4073 F8F3F0 09 01 ora #$01 ; overrun bit (bit<0>)4074 F8F3F2 09 80 ora #$80 ; set x error bit4075 F8F3F4 80 43 bra ?sst ; set status reg. & discard received data4076 F8F3F6 8A ?rx: txa ; A = received data4077 F8F3F7 INDEX164078 F8F3F7 C2 10 rep #PXFLAG4079 .LONGI on4080 .MNLIST4081 F8F3F9 A6 23 ldx ibufcnt3 ; count of bytes stored in input queue4082 F8F3FB 24 15 bit spmode3 ; test for active handshake4083 F8F3FD 10 33 bpl ?chk ; no handshake: goto to check input queue4084 F8F3FF 70 14 bvs ?tst ; hardware handshake (check queue overflow)4085 F8F401 C9 11 cmp #SPXON ; received an XON control byte?4086 F8F403 D0 06 bne ?xoff ; no, check if received an XOFF4087 F8F405 A9 40 lda #$40 ; clear local pause flag4088 F8F407 14 17 trb sppause3 ; bit<6> = 0 -> local pause off (resume tx)4089 F8F409 80 44 bra ?cnt ; discard received data4090 F8F40B C9 13 ?xoff: cmp #SPXOFF ; received an XOFF control byte?4091 F8F40D D0 06 bne ?tst ; no, so check queue overflow4092 F8F40F A9 40 lda #$40 ; set local pause flag4093 F8F411 04 17 tsb sppause3 ; bit<6> = 1 -> local pause on (stop tx)4094 F8F413 80 3A bra ?cnt ; discard received data4095 F8F415 E4 29 ?tst: cpx icntmax3 ; check input buff. for remote pause condition4096 F8F417 90 24 bcc ?sto ; below guard limit: store data4097 F8F419 24 17 bit sppause3 ; remote pause is already on ?4098 F8F41B 30 15 bmi ?chk ; yes, so check input buffer4099 F8F41D EB xba ; B = received data4100 F8F41E 24 15 bit spmode3 ; test handshake type4101 F8F420 70 06 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=14102 F8F422 A9 13 lda #SPXOFF ; send an XOFF to remote terminal4103 F8F424 85 18 sta spout3 ; XOFF sending deffered until TDRE is set4104 F8F426 80 09 bra ?xba ; check input buffer4105 F8F428 A9 04 ?rtsh: lda #$04 ; hardware handshake...4106 F8F42A 0C 1F FC tsb !VIA2+VIAPRANH ; ...set RTS=14107 F8F42D A9 80 lda #$80 ; set remote pause4108 F8F42F 04 17 tsb sppause3 ; bit 7=1 -> remote pause onTue Jul 17 11:11:08 2018 Page 274109 F8F431 EB ?xba: xba ; A = received data4110 F8F432 E0 00 10 ?chk: cpx #SIBUFSIZ3 ; left room in input buffer?4111 F8F435 90 06 bcc ?sto ; yes, store received byte4112 F8F437 A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow4113 F8F439 85 19 ?sst: sta spstat3 ; set status register4114 F8F43B 80 12 bra ?cnt ; discard received data4115 F8F43D E8 ?sto: inx ; now store received data4116 F8F43E 86 23 stx ibufcnt3 ; update bytes count4117 F8F440 A6 1B ldx ibuftail3 ; pointer to rx tail queue4118 F8F442 9F 00 D0 05 sta >SIBUFADDR3,x4119 F8F446 E8 inx ; update tail pointer4120 F8F447 CPU164121 F8F447 C2 30 rep #(PMFLAG.OR.PXFLAG)4122 .LONGA on4123 .LONGI on4124 .MNLIST4125 .MLIST4126 F8F449 8A txa4127 F8F44A 29 FF 0F and #(SIBUFSIZ3-1) ; circular queue4128 F8F44D 85 1B sta ibuftail34129 F8F44F ?cnt: CPU08 ; continue...4130 .MLIST4131 F8F44F E2 30 sep #(PMFLAG.OR.PXFLAG)4132 .LONGA off4133 .LONGI off4134 .MNLIST4135 F8F451 98 tya ; A = acia status4136 F8F452 A8 ?lin: tay4137 F8F453 29 40 and #01000000B ; mask off all bits but /DSR4138 F8F455 F0 04 beq ?dsr ; clear /DSR flag4139 F8F457 04 16 tsb splin3 ; set /DSR flag4140 F8F459 80 04 bra ?cnt24141 F8F45B A9 40 ?dsr: lda #$404142 F8F45D 14 16 trb splin34143 F8F45F 98 ?cnt2: tya4144 F8F460 89 10 bit #ACIATDRE ; TX reg. empty?4145 F8F462 F0 23 beq ?end ; no4146 F8F464 A6 18 ldx spout3 ; pending an XON/XOFF sending?4147 F8F466 F0 23 beq ?cklp ; no... check local pause flag4148 F8F4684149 ; if send an XON then we will re-enable tx interrupt4150 ; else we will disable tx interrupt4151 ;4152 F8F468 A9 0C lda #00001100B ; disable tx for now (is safe)4153 F8F46A 1C 2A FC trb !ACIACMD4154 F8F46D E0 11 cpx #SPXON4155 F8F46F D0 04 bne ?di4156 F8F471 A9 04 lda #00000100B ; re-enable tx interrupt4157 F8F473 80 02 bra ?cmd4158 F8F475 A9 08 ?di: lda #00001000B ; disable tx interrupt4159 F8F477 0C 2A FC ?cmd: tsb !ACIACMD4160 F8F47A 8E 28 FC stx .ABS.ACIADR ; send XON/XOFF4161 F8F47D 64 18 stz spout3 ; clear XON/XOFF flag4162 F8F47F A9 80 lda #$80 ; remote pause flag4163 F8F481 E0 13 cpx #SPXOFF4164 F8F483 F0 03 beq ?srp ; sent an XOFF: set remote pause flag4165 F8F485 14 17 trb sppause3 ; sent an XON: clear remote pause flagTue Jul 17 11:11:08 2018 Page 284166 F8F487 60 ?end: rts ; done4167 F8F488 04 17 ?srp: tsb sppause3 ; set remote pause flag4168 F8F48A 60 rts4169 F8F48B 24 17 ?cklp: bit sppause3 ; local pause is set ?4170 F8F48D 70 06 bvs ?off ; yes, no tx possible at this time4171 F8F48F INDEX164172 F8F48F C2 10 rep #PXFLAG4173 .LONGI on4174 .MNLIST4175 F8F491 A6 25 ldx obufcnt3 ; count of bytes in output buffer4176 F8F493 D0 0C bne ?snd ; output buffer inot empty: send next byte4177 F8F495 A9 0C ?off: lda #00001100B ; disable TX interrupt for avoid cont. int.4178 F8F497 1C 2A FC trb !ACIACMD4179 F8F49A A9 08 lda #00001000B4180 F8F49C 0C 2A FC tsb !ACIACMD4181 F8F49F 80 15 bra ?done4182 F8F4A1 CA ?snd: dex ; update count4183 F8F4A2 86 25 stx obufcnt34184 F8F4A4 A6 21 ldx obufhead3 ; pointer to head of out buffer4185 F8F4A6 BF 00 C0 05 lda >SOBUFADDR3,x ; get data from output buffer4186 F8F4AA 8D 28 FC sta .ABS.ACIADR ; send data4187 F8F4AD E8 inx ; update head pointer4188 F8F4AE CPU164189 F8F4AE C2 30 rep #(PMFLAG.OR.PXFLAG)4190 .LONGA on4191 .LONGI on4192 .MNLIST4193 F8F4B0 8A txa4194 F8F4B1 29 FF 0F and #(SOBUFSIZ3-1) ; circular queue4195 F8F4B4 85 21 sta obufhead34196 F8F4B6 ?done: CPU084197 F8F4B6 E2 30 sep #(PMFLAG.OR.PXFLAG)4198 .LONGA off4199 .LONGI off4200 .MNLIST4201 ;rts42024203 ; 16C550 interrupt4204 ; ISR routine (prologue and epilogue code for context switching not showed here)4205 ; handle 16C550 interrupt4206 ; WARNING: assume DBR = 0 and DP saved by interrupt handler prologue code4207 F8F4B8 uartisr:4208 F8F4B8 AD 22 FC lda !UART_IIR4209 F8F4BB 85 43 sta uartiir ; save for late check FIFO enabled4210 F8F4BD 4A lsr a ; if bit <0> = 1 no interrupt4211 F8F4BE 90 01 bcc $+3 ; interrupt pending4212 F8F4C0 60 rts4213 F8F4C1 29 03 and #0000011B ; mask on priority code4214 F8F4C3 0A asl a4215 F8F4C4 AA tax4216 ; ldy #404217 ;?00: dey4218 ; bne ?004219 ; RX timeout interrupt and RX data available interrupt use the same routine4220 F8F4C5 7C C8 F4 jmp (?uarttbl,x) ; jump to right routine42214222 F8F4C8 ?uarttbl:Tue Jul 17 11:11:08 2018 Page 294223 F8F4C8 D5F4 DAF4 DFF4 .DW ?msr, ?tx, ?rx, ?lsrD0F442244225 F8F4D0 20 5A F5 ?lsr: jsr uartilsr4226 ;rts4227 F8F4D3 80 E3 bra uartisr ; check again interrupt (was a test)4228 F8F4D54229 F8F4D5 20 E4 F4 ?msr: jsr uartmsr ; MSR: modem status register4230 ;rts4231 F8F4D8 80 DE bra uartisr ; check again iterrupt4232 F8F4DA4233 F8F4DA 20 15 F5 ?tx: jsr uarttx ; TX FIFO or THR is empty4234 ;rts4235 F8F4DD 80 D9 bra uartisr ; check again interrupt42364237 F8F4DF 20 7A F5 ?rx: jsr uartrx ; data available in RX FIFO or RHR4238 ;rts4239 F8F4E2 80 D4 bra uartisr ; check again interrupt42404241 ; this interrupt is raised when one of the modem lines change state4242 ; here just DSR and CTS are used: DSR for signaling remote disconnession,4243 ; CTS for hardware handshake (put local TX in pause)4244 F8F4E4 uartmsr:4245 F8F4E4 AD 26 FC lda !UART_MSR ; clear interrupt4246 F8F4E7 AA tax4247 F8F4E8 0A asl a4248 F8F4E9 0A asl a ; <7>: /DSR, <6>: /CTS4249 F8F4EA 49 C0 eor #$C04250 F8F4EC 85 2C sta splin4 ; update line status4251 F8F4EE 24 2B bit spmode44252 F8F4F0 10 22 bpl ?end ; no handshake: ignore line changes4253 F8F4F2 A8 tay4254 F8F4F3 10 04 bpl ?cts ; /DSR is low, check /CTS4255 F8F4F5 A9 A0 lda #$A0 ; /DSR is high4256 F8F4F7 04 2F tsb spstat4 ; remote terminal disconnected4257 F8F4F9 8A ?cts: txa4258 F8F4FA 4A lsr a ; check /CTS transition4259 F8F4FB 90 17 bcc ?end ; no /CTS transition4260 F8F4FD A2 40 ldx #$40 ; local pause flag4261 F8F4FF 98 tya4262 F8F500 0A asl a4263 F8F501 10 09 bpl ?clp ; transition /CTS high->low: clear local pause4264 F8F503 8A txa4265 F8F504 04 2D tsb sppause4 ; /CTS high -> set local pause4266 F8F506 A9 02 lda #00000010B ; disable TX interrupt4267 F8F508 1C 21 FC trb !UART_IER4268 F8F50B 60 rts4269 F8F50C 8A ?clp: txa4270 F8F50D 14 2D trb sppause4 ; /CTS low -> clear local pause4271 F8F50F A9 02 lda #00000010B ; enable TX interrupt4272 F8F511 0C 21 FC tsb !UART_IER4273 F8F514 60 ?end: rts42744275 ; this interrupt is raised either when THR is empty4276 ; or when TX FIFO is empty4277 F8F515 uarttx:4278 F8F515 A9 02 lda #00000010B ; disable TX interruptTue Jul 17 11:11:08 2018 Page 304279 F8F517 1C 21 FC trb !UART_IER4280 F8F51A 24 2D bit sppause4 ; local pause is set ?4281 F8F51C 70 39 bvs ?done ; yes, no tx possible at this time4282 F8F51E INDEX164283 F8F51E C2 10 rep #PXFLAG4284 .LONGI on4285 .MNLIST4286 F8F520 A4 3B ldy obufcnt4 ; count of bytes in output buffer4287 F8F522 F0 33 beq ?done ; nothing to send at this time4288 F8F524 A6 35 ldx obuftail4 ; pointer to tail of out buffer4289 ;lda spcnt4 ; set the bytes count4290 F8F526 A9 10 lda #16 ; set the bytes count4291 F8F528 85 30 sta sptmp44292 F8F52A BF 00 00 06 ?txl: lda >SOBUFADDR4,x ; get data from the tail of output buffer4293 F8F52E 8D 27 FC sta !UART_SCP4294 F8F531 EA nop4295 F8F532 EA nop4296 F8F533 EA nop4297 F8F534 EA nop4298 F8F535 8D 27 FC sta !UART_SCP4299 F8F538 EA nop4300 F8F539 EA nop4301 F8F53A EA nop4302 F8F53B EA nop4303 F8F53C EA nop4304 F8F53D EA nop4305 F8F53E 8F 20 FC 00 sta >UART_RXTX ; load data into FIFO/THR4306 F8F542 E8 inx ; update head pointer4307 F8F543 ACC164308 F8F543 C2 20 rep #PMFLAG4309 .LONGA on4310 .MNLIST4311 F8F545 8A txa4312 F8F546 29 FF 7F and #(SOBUFSIZ4-1) ; circular queue4313 F8F549 AA tax4314 F8F54A ACC084315 F8F54A E2 20 sep #PMFLAG4316 .LONGA off4317 .MNLIST4318 F8F54C 88 dey ; update count4319 F8F54D F0 04 beq ?upd ; nothing else to send4320 F8F54F C6 30 dec sptmp44321 F8F551 D0 D7 bne ?txl ; loop: load more bytes if FIFO enabled4322 F8F553 86 35 ?upd: stx obuftail44323 F8F555 84 3B sty obufcnt44324 F8F557 ?done: CPU08 ; NOTE: tx interrupt will be re-enabled by put routine4325 F8F557 E2 30 sep #(PMFLAG.OR.PXFLAG)4326 .LONGA off4327 .LONGI off4328 .MNLIST4329 F8F559 60 rts ; or by a negative /CTS transition43304331 ; this interrupt is raised when receive a byte with some errors4332 F8F55A uartilsr:4333 F8F55A A9 05 lda #00000101B ; disable LSR & RX interrupt4334 F8F55C 1C 21 FC trb UART_IER4335 F8F55F AD 25 FC lda !UART_LSR ; get line status and clear interruptTue Jul 17 11:11:08 2018 Page 314336 F8F562 85 42 sta uartlsr ; save for further debugging4337 F8F564 4A lsr a ; CF = 1 if available a new rx byte4338 F8F565 29 0F and #$0F ; mask on rx errors4339 ;beq uartrx14340 F8F567 09 80 ora #$80 ; set rx error bit4341 F8F569 85 2F sta spstat4 ; set status register4342 F8F56B 90 0C bcc ?done ; no new char received4343 F8F56D AD 20 FC lda !UART_RXTX ; get top fifo data or THR & discard4344 F8F570 24 43 bit uartiir4345 F8F572 50 05 bvc ?done ; no FIFO enabled4346 F8F574 A9 83 lda #10000011B ; clear RX FIFO4347 F8F576 8D 22 FC sta !UART_FCR4348 F8F579 60 ?done: rts ; after rx error, rx interrupt are disabled43494350 ; this interrupt is raised either when RHR is full or when RX FIFO reach the4351 ; programmed trigger level (in this case 8)4352 F8F57A uartrx:4353 F8F57A EA nop4354 F8F57B EA nop4355 F8F57C EA nop4356 F8F57D EA nop4357 F8F57E INDEX164358 F8F57E C2 10 rep #PXFLAG4359 .LONGI on4360 .MNLIST4361 F8F580 A4 39 ldy ibufcnt4 ; count of bytes in input buffer4362 F8F582 A6 33 ldx ibufhead4 ; pointer to head of input buffer4363 F8F584 AD 20 FC ?loop: lda !UART_RXTX ; get top fifo data or THR4364 F8F587 C4 3F cpy icntmax4 ; check input buff. for remote pause condition4365 F8F589 90 14 bcc ?str ; below guard limit: store data4366 F8F58B EB xba ; B = received data4367 F8F58C A9 02 lda #00000010B ; hardware handshake...4368 F8F58E 1C 24 FC trb !UART_MCR ; ...set RTS=14369 F8F591 A9 80 lda #$80 ; set remote pause flag4370 F8F593 04 2D tsb sppause4 ; bit 7=1 -> remote pause on4371 F8F595 EB xba ; A = received data4372 F8F596 C0 00 80 ?chk: cpy #SIBUFSIZ4 ; left room in input buffer?4373 F8F599 90 04 bcc ?str ; yes, store received byte4374 F8F59B A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overrun4375 F8F59D 80 21 bra ?sst ; discard received data & exit4376 F8F59F 9F 00 80 06 ?str: sta >SIBUFADDR4,x ; now store received data4377 F8F5A3 C8 iny ; update bytes count4378 F8F5A4 E8 inx ; update rx head pointer4379 F8F5A5 ACC164380 F8F5A5 C2 20 rep #PMFLAG4381 .LONGA on4382 .MNLIST4383 F8F5A7 8A txa4384 F8F5A8 29 FF 7F and #(SIBUFSIZ4-1) ; circular queue4385 F8F5AB AA tax4386 F8F5AC ACC084387 F8F5AC E2 20 sep #PMFLAG4388 .LONGA off4389 .MNLIST4390 F8F5AE 24 43 bit uartiir4391 F8F5B0 50 10 bvc ?done4392 F8F5B2 AD 25 FC lda !UART_LSR ; get line statusTue Jul 17 11:11:08 2018 Page 324393 F8F5B5 85 42 sta uartlsr4394 F8F5B7 4A lsr a ; CF = 1 if available a new rx byte4395 F8F5B8 29 0F and #$0F ; mask on rx errors4396 F8F5BA 90 06 bcc ?done ; no data available, re-enable rx int. & exit4397 F8F5BC F0 C6 beq ?loop4398 F8F5BE 09 80 ora #$804399 F8F5C0 85 2F ?sst: sta spstat44400 F8F5C2 86 33 ?done: stx ibufhead4 ; save rx head pointer4401 F8F5C4 84 39 sty ibufcnt4 ; save bytes count4402 F8F5C6 INDEX084403 F8F5C6 E2 10 sep #PXFLAG4404 .LONGI off4405 .MNLIST4406 F8F5C8 60 rts44074408 .COMMENT @4409 uartrx:4410 ;lda #$01 ; disable RX interrupt4411 ;trb UART_IER4412 INDEX164413 ldy ibufcnt4 ; count of bytes in input buffer4414 ldx ibufhead4 ; pointer to head of input buffer4415 rxloop: lda !UART_LSR ; get line status4416 sta uartlsr4417 lsr a ; CF = 1 if available a new rx byte4418 and #$0F ; mask on rx errors4419 uartrx1:4420 bcc ?done ; no data available, re-enable rx int. & exit4421 xba ; save error code44224423 nop4424 nop4425 nop4426 nop44274428 lda !UART_RXTX ; get top fifo data or THR4429 xba4430 ?tst: beq ?rx ; no rx error pending4431 ora #$80 ; set rx error bit4432 bra ?sst ; set status reg. & discard received data4433 ?rx: xba ; A = received data4434 cpy icntmax4 ; check input buff. for remote pause condition4435 bcc ?str ; below guard limit: store data4436 xba ; B = received data4437 lda #00000010B ; hardware handshake...4438 trb !UART_MCR ; ...set RTS=14439 lda #$80 ; set remote pause flag4440 tsb sppause4 ; bit 7=1 -> remote pause on4441 xba ; A = received data4442 ?chk: cpy #SIBUFSIZ4 ; left room in input buffer?4443 bcc ?str ; yes, store received byte4444 lda #$C0 ; set bit 7: rx error, bit 6: rx overrun4445 ?sst: sta spstat4 ; set status register4446 bra ?done ; discard received data & exit4447 ?str: sta >SIBUFADDR4,x ; now store received data4448 iny ; update bytes count4449 inx ; update rx head pointerTue Jul 17 11:11:08 2018 Page 334450 ACC164451 txa4452 and #(SIBUFSIZ4-1) ; circular queue4453 tax4454 ACC084455 bra rxloop ; check again if rx data available4456 ?done: stx ibufhead4 ; save rx head pointer4457 sty ibufcnt4 ; save bytes count4458 ?done1: INDEX084459 ;lda #$01 ; re-enable rx interrupt4460 ;tsb UART_IER4461 rts4462 @44634464 .COMMENT @4465 uart:4466 lda !UART_IIR4467 sta uartiir4468 lsr a ; if <0> = 1 no interrupt4469 bcc $+3 ; interrupt pending4470 rts4471 and #0000011B ; mask on priority code4472 asl a4473 tax4474 jmp (?uarttbl,x)44754476 ?uarttbl:4477 .DW ?msr, ?tx, ?rx, ?lsr447844794480 ; int. 3: line status register (LSR)4481 ;4482 ?lsr: ;jsr uartrx4483 lda !UART_LSR ; read LSR and clear interrupt4484 sta uartlsr4485 ;rts4486 bra uart ; check again interrupt44874488 ?msr: jsr uartmsr ; MSR: modem status register4489 ;rts4490 bra uart ; check again iterrupt44914492 ?tx: jsr uarttx ; TX FIFO is empty4493 ;rts4494 bra uart ; check again interrupt44954496 ?rx: jsr uartrx ; data available in RX FIFO4497 ;rts4498 bra uart ; check again interrupt449945004501 uartmsr:4502 lda !UART_MSR4503 tax4504 asl a4505 asl a ; <7>: /DSR, <6>: /CTS4506 eor #$C0Tue Jul 17 11:11:08 2018 Page 344507 sta splin4 ; update line status4508 tay4509 bit spmode44510 bpl ?end ; no handshake4511 bvc ?end ; software handshake: no /CTS and /DSR check4512 tya4513 bpl ?cts ; /DSR is low4514 lda #$A04515 tsb spstat4 ; remote terminal disconnected4516 ?cts: bvc ?end ; handshake software: no check /CTS4517 txa4518 lsr a ; check /CTS transition4519 bcc ?end ; no /CTS transition4520 ldx #$40 ; local pause flag4521 tya4522 asl a4523 bpl ?clp ; transition high->low4524 txa4525 tsb sppause4 ; /CTS high set local pause4526 rts4527 ?clp: txa4528 trb sppause4 ; /CTS low clear local pause4529 ?end: rts45304531 uarttx:4532 ;;lda !UART_IIR45334534 lda !UART_LSR4535 and #$404536 ;;cmp #$604537 bne ?cklp4538 lda !UART_IIR4539 rts4540 ;lda #$204541 ;bit !UART_LSR4542 ;bne ?cklp4543 ;rts45444545 bra ?cklp4546 ldx spout4 ; pending an XON/XOFF sending?4547 beq ?cklp ; no... check local pause flag45484549 ; if send an XON then we will re-enable tx interrupt4550 ; else we will disable tx interrupt4551 ;4552 lda #00000010B ; IER<1>: tx interrupt4553 cpx #SPXON4554 bne ?di4555 tsb !UART_IER ; enable tx interrupt4556 bra ?htx14557 ?di: trb !UART_IER ; disable tx interrupt4558 ?htx1: stx .ABS.UART_RXTX ; send XON/XOFF4559 stz spout4 ; clear XON/XOFF flag4560 lda #$80 ; remote pause flag4561 cpx #SPXOFF4562 beq ?srp ; sent an XOFF: set remote pause flag4563 trb sppause4 ; sent an XON: clear remote pause flagTue Jul 17 11:11:08 2018 Page 354564 rts ; done4565 ?srp: tsb sppause4 ; set remote pause flag4566 rts4567 ?cklp: bit sppause4 ; local pause is set ?4568 bvs ?off ; yes, no tx possible at this time4569 INDEX164570 ldx obufhead4 ; pointer to head of out buffer4571 ldy obufcnt4 ; count of bytes in output buffer4572 bne ?snd ; output buffer is not empty4573 ?off: lda #00000010B ; disable TX interrupt for avoid cont. int.4574 trb !UART_IER4575 bra ?done4576 ?snd:4577 lda #00000010B ; disable TX interrupt for avoid cont. int.4578 trb !UART_IER45794580 lda #1 ; fill fifo4581 sta spout44582 lda #$204583 bit spmode44584 bne ?txl4585 lda #14586 sta spout44587 ?txl:4588 lda >SOBUFADDR4,x ; get data from output buffer4589 sta !UART_RXTX ; send data to FIFO4590 inx ; update head pointer4591 ACC164592 txa4593 and #(SOBUFSIZ4-1) ; circular queue4594 tax4595 ACC084596 dey4597 beq ?upd4598 dec spout44599 bne ?txl4600 ?upd: stz spout44601 stx obufhead44602 sty obufcnt44603 ?done: CPU084604 lda !UART_IIR4605 rts46064607 uartrx:4608 ;lda spstat44609 ;bmi ?rts46104611 lda #$014612 trb UART_IER4613 INDEX164614 ldy ibufcnt44615 ldx ibuftail44616 ?lp1: lda !UART_LSR4617 sta uartlsr4618 lsr a4619 bcc ?done4620Tue Jul 17 11:11:08 2018 Page 364621 ;bcs ?loop4622 ;and #$0F4623 ;beq ?done14624 ;ora #$80 ; set rx error bit4625 ;sta spstat44626 ;bra ?done146274628 ?loop: and #$0F ; mask on errors4629 xba4630 lda !UART_RXTX ; get top fifo data4631 xba4632 beq ?rx ; no rx error pending4633 ora #$80 ; set rx error bit4634 bra ?sst ; set status reg. & discard received data4635 ?rx: xba ; A = received data4636 bit spmode4 ; test for active handshake4637 bpl ?chk ; no handshake: goto to check input queue4638 bvs ?tst ; hardware handshake (check queue overflow)4639 cmp #SPXON ; received an XON control byte?4640 bne ?xoff ; no, check if received an XOFF4641 lda #$40 ; clear local pause flag4642 trb sppause4 ; bit<6> = 0 -> local pause off (resume tx)4643 bra ?cnt ; discard received data4644 ?xoff: cmp #SPXOFF ; received an XOFF control byte?4645 bne ?tst ; no, so check queue overflow4646 lda #$40 ; set local pause flag4647 tsb sppause4 ; bit<6> = 1 -> local pause on (will stop tx)4648 bra ?cnt ; discard received data4649 ?tst: cpy icntmax4 ; check input buff. for remote pause condition4650 bcc ?str ; below guard limit: store data4651 bit sppause4 ; remote pause is already on ?4652 bmi ?chk ; yes, so check input buffer4653 xba ; B = received data4654 bit spmode4 ; test handshake type4655 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=14656 lda #SPXOFF ; send an XOFF to remote terminal4657 sta spout4 ; XOFF sending deffered until THR is empty4658 lda #00000010B ; IER<1>: tx interrupt4659 tsb !UART_IER ; enable tx interrupt4660 bra ?xba ; check input buffer4661 ?rtsh: lda #00000010B ; hardware handshake...4662 trb !UART_MCR ; ...set RTS=14663 lda #$80 ; set remote pause4664 tsb sppause4 ; bit 7=1 -> remote pause on4665 ?xba: xba ; A = received data4666 ?chk: cpy #SIBUFSIZ4 ; left room in input buffer?4667 bcc ?str ; yes, store received byte4668 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow4669 ?sst: sta spstat4 ; set status register4670 bra ?done ; discard received data & exit4671 ?str: sta >SIBUFADDR4,x ; now store received data4672 iny ; update bytes count4673 inx ; update rx tail pointer4674 ACC164675 txa4676 and #(SIBUFSIZ4-1) ; circular queue4677 taxTue Jul 17 11:11:08 2018 Page 374678 ACC084679 ?cnt: ;lda !UART_LSR ; any rx data pending?4680 ;sta uartlsr4681 ;lsr a4682 ;bcs ?loop ; yes, get again from top fifo4683 bra ?lp14684 ?done: stx ibuftail4 ; save rx tail pointer4685 sty ibufcnt4 ; save bytes count4686 ?done1: INDEX084687 ?rts:4688 lda #$014689 tsb UART_IER4690 rts4691 @46924693 F8F5C9 int5sr:4694 F8F5C9 int6sr:4695 F8F5C9 60 rts46964697 ; INT from RTC4698 F8F5CA int7sr:4699 F8F5CA A2 0A ldx #RTCCTRLA ; setta banco 1 RTC4700 F8F5CC 8E 4C FD stx RTCALE4701 F8F5CF AD 4D FD lda RTCDATA ; salva flag banco4702 F8F5D2 48 pha4703 F8F5D3 09 10 ora #$10 ; setta banco 14704 F8F5D5 8D 4D FD sta RTCDATA4705 F8F5D8 A2 4E ldx #RTCSMI2 ; recupera eventuale ALE4706 F8F5DA 8E 4C FD stx RTCALE4707 F8F5DD AD 4D FD lda RTCDATA4708 F8F5E0 48 pha ; ALE da ripristinare4709 F8F5E1 A2 0C ldx #RTCSTATUS4710 F8F5E3 8E 4C FD stx RTCALE4711 F8F5E6 AD 4D FD lda RTCDATA ; azzera flag4712 F8F5E9 30 03 bmi ?014713 F8F5EB 4C 74 F6 jmp ?20 ; NO IRQ da RTC4714 F8F5EE 89 20 ?01: bit #$20 ; flag AF (alarm)4715 F8F5F0 F0 5E beq ?10 ; no alarm4716 F8F5F2 A2 4A ldx #RTCEXTCTRLA ; check INCR bit 64717 F8F5F4 8E 4C FD stx RTCALE4718 F8F5F7 2C 4D FD ?02: bit RTCDATA4719 F8F5FA 70 FB bvs ?024720 F8F5FC A2 06 ldx #RTCDAY ; day of week4721 F8F5FE 8E 4C FD stx RTCALE4722 F8F601 AD 4D FD lda RTCDATA4723 F8F604 C9 01 cmp #1 ; sunday?4724 F8F606 D0 48 bne ?10 ; no4725 F8F608 E8 inx4726 F8F609 8E 4C FD stx RTCALE4727 F8F60C AD 4D FD lda RTCDATA ; day of month (date)4728 F8F60F C9 19 cmp #25 ; last sunday of month?4729 F8F611 90 3D bcc ?10 ; no4730 F8F613 E8 inx4731 F8F614 8E 4C FD stx RTCALE ; month4732 F8F617 AD 4D FD lda RTCDATA4733 F8F61A C9 03 cmp #3 ; march?4734 F8F61C D0 12 bne ?04 ; noTue Jul 17 11:11:08 2018 Page 384735 F8F61E A2 04 ldx #RTCHOURS ; increment hours4736 F8F620 8E 4C FD stx RTCALE4737 F8F623 EE 4D FD inc RTCDATA4738 F8F626 A2 0F ldx #RTCRAM0F4739 F8F628 8E 4C FD stx RTCALE4740 F8F62B 9C 4D FD stz RTCDATA ; reset flag for next time4741 F8F62E 80 20 bra ?104742 F8F630 C9 0A ?04: cmp #10 ; october?4743 F8F632 D0 1C bne ?10 ; no4744 F8F634 A2 0F ldx #RTCRAM0F4745 F8F636 8E 4C FD stx RTCALE4746 F8F639 AD 4D FD lda RTCDATA ; already updated?4747 F8F63C 10 05 bpl ?06 ; no4748 F8F63E 9C 4D FD stz RTCDATA ; yes...so reset flag4749 F8F641 80 0D bra ?104750 F8F643 A9 FF ?06: lda #$FF4751 F8F645 8D 4D FD sta RTCDATA ; set updated flag4752 F8F648 A2 04 ldx #RTCHOURS ; decrement hours4753 F8F64A 8E 4C FD stx RTCALE4754 F8F64D CE 4D FD dec RTCDATA4755 F8F650 A2 4A ?10: ldx #RTCEXTCTRLA ; check others interrupt's4756 F8F652 8E 4C FD stx RTCALE4757 F8F655 AD 4D FD lda RTCDATA4758 F8F658 89 01 bit #$01 ; KF ?4759 F8F65A 08 php4760 F8F65B A9 07 lda #$07 ; cancella altri IRQ4761 F8F65D 1C 4D FD trb RTCDATA4762 F8F660 28 plp4763 F8F661 F0 11 beq ?20 ; NO KF4764 F8F663 A9 01 lda #$01 ; TEST KS START4765 F8F665 24 0D bit RTCFlag4766 F8F667 D0 04 bne ?11 ; KS OFF4767 F8F669 04 0D tsb RTCFlag ; segnala KS OFF4768 F8F66B 80 07 bra ?204769 F8F66D A9 08 ?11: lda #$08 ; PAB = 1, PWR OFF4770 ;tsb RTCDATA4771 F8F66F 1C 4D FD trb RTCDATA4772 F8F672 A9 01 lda #$01 ; CLEAR KS START4773 ;trb SysRTC4774 F8F674 7A ?20: ply ; ALE da ripristinare4775 F8F675 A2 0A ldx #RTCCTRLA ; setta banco originale RTC4776 F8F677 8E 4C FD stx RTCALE4777 F8F67A 68 pla ; banco originale4778 F8F67B 8D 4D FD sta RTCDATA ; salva flag banco4779 F8F67E 8C 4C FD sty RTCALE ; ripristina ALE4780 F8F681 60 rts4781 F8F68247824783 .CODE47844785 .EXTERN SysStart4786 .GLOBAL intsr47874788 ;4789 ; FWE XFE R/W BANK $F04790 ; 0 X X RAM4791 ; 1 0 X FLASHTue Jul 17 11:11:08 2018 Page 394792 ; 1 1 1 EEROM8U4793 ; 1 1 0 RAM4794 ;4795 ; codice di startup4796 F8FE00 _RSTEntry:47974798 ; at start: XFE=0, FWE=0, HIM=04799 F8FE00 78 sei4800 F8FE01 D8 cld4801 ;sta !CRHIMOFF ; forza start da flash4802 F8FE02 18 clc4803 F8FE03 FB xce ; CPU in modo nativo4804 F8FE04 A0 00 ldy #04805 F8FE06 CPU164806 F8FE06 C2 30 rep #(PMFLAG.OR.PXFLAG)4807 .LONGA on4808 .LONGI on4809 .MNLIST4810 F8FE08 A2 FF DF ldx #STACK_ADDR ; init stack4811 F8FE0B 9A txs4812 F8FE0C 98 tya ; DP = 0 (page 0)4813 F8FE0D 5B tcd4814 F8FE0E BB tyx4815 F8FE0F CPU084816 F8FE0F E2 30 sep #(PMFLAG.OR.PXFLAG)4817 .LONGA off4818 .LONGI off4819 .MNLIST4820 F8FE11 4B phk4821 F8FE12 AB plb ; DBR = PBR = 048224823 F8FE13 AD 00 FC lda !CRBIT0 ; test boot4824 F8FE16 F0 46 beq ?09 ; firmware from FLASH48254826 ; check EEROM emulator board4827 F8FE18 8C 62 FC ?00: sty .ABS.VIA4+VIADDRB4828 F8FE1B CC 62 FC cpy .ABS.VIA4+VIADDRB4829 F8FE1E D0 3E bne ?09 ; fail -- goto old way4830 F8FE20 C8 iny4831 F8FE21 D0 F5 bne ?004832 F8FE234833 ; ok, seem present4834 F8FE23 88 dey4835 F8FE24 8C 62 FC sty .ABS.VIA4+VIADDRB ; port B out48364837 ; transfer emulator data to $F0 bank4838 F8FE27 A9 F0 lda #$F04839 F8FE29 85 02 sta <24840 F8FE2B 64 00 stz <04841 F8FE2D 64 01 stz <14842 F8FE2F 9C 60 FC stz !VIA4+VIAPRB4843 F8FE32 8D 0D FC sta !CREMEON4844 F8FE35 INDEX164845 F8FE35 C2 10 rep #PXFLAG4846 .LONGI on4847 .MNLIST4848 F8FE37 A0 00 00 ?lp1: ldy #0Tue Jul 17 11:11:08 2018 Page 404849 F8FE3A BB tyx4850 F8FE3B BF 00 18 01 ?lp2: lda >EMURAM,x4851 F8FE3F 97 00 sta [0],y4852 F8FE41 C8 iny4853 F8FE42 E8 inx4854 F8FE43 E0 00 08 cpx #$08004855 F8FE46 90 F3 bcc ?lp24856 F8FE48 ACC16CLC4857 F8FE48 C2 21 rep #(PMFLAG.OR.PCFLAG)4858 .LONGA on4859 .MNLIST4860 F8FE4A 8A txa4861 F8FE4B 65 00 adc <04862 F8FE4D 85 00 sta <04863 F8FE4F ACC084864 F8FE4F E2 20 sep #PMFLAG4865 .LONGA off4866 .MNLIST4867 F8FE51 90 02 bcc ?nxt4868 F8FE53 E6 02 inc <24869 F8FE55 EE 60 FC ?nxt: inc !VIA4+VIAPRB4870 F8FE58 D0 DD bne ?lp14871 F8FE5A CPU084872 F8FE5A E2 30 sep #(PMFLAG.OR.PXFLAG)4873 .LONGA off4874 .LONGI off4875 .MNLIST4876 F8FE5C 80 08 bra ?1048774878 ;sta !CREMEOFF4879 ;ldy #04880 ;CPU164881 ;tyx4882 ;lda #$FFFF4883 ;mvn #$E8, #$F84884 ;mvn #$E9, #$F94885 ;mvn #$EA, #$FA4886 ;mvn #$EB, #$FB4887 ;mvn #$EC, #$FC4888 ;mvn #$ED, #$FD4889 ;mvn #$EE, #$FE4890 ;mvn #$EF, #$FF4891 ;CPU084892 ;bra ?1148934894 ; original boot sequence4895 F8FE5E 8D 07 FC ?09: sta !CRFWEON ; enable FLASH/EMU IN BANK $F04896 ;lda !CRBIT0 ; test boot4897 F8FE61 F0 03 beq ?10 ; firmware from flash4898 F8FE63 8D 09 FC sta !CRXFEON ; enable EEROM8U4899 F8FE66 A0 00 ?10: ldy #04900 F8FE68 CPU164901 F8FE68 C2 30 rep #(PMFLAG.OR.PXFLAG)4902 .LONGA on4903 .LONGI on4904 .MNLIST4905 F8FE6A BB tyxTue Jul 17 11:11:08 2018 Page 414906 F8FE6B A9 FF FF lda #$FFFF4907 F8FE6E 54 F8 F0 mvn #$F0, #$F84908 F8FE71 54 F9 F1 mvn #$F1, #$F94909 F8FE74 54 FA F2 mvn #$F2, #$FA4910 F8FE77 54 FB F3 mvn #$F3, #$FB4911 F8FE7A 54 FC F4 mvn #$F4, #$FC4912 F8FE7D 54 FD F5 mvn #$F5, #$FD4913 F8FE80 54 FE F6 mvn #$F6, #$FE4914 F8FE83 54 FF F7 mvn #$F7, #$FF4915 F8FE86 CPU084916 F8FE86 E2 30 sep #(PMFLAG.OR.PXFLAG)4917 .LONGA off4918 .LONGI off4919 .MNLIST4920 F8FE88 4B ?11: phk4921 F8FE89 AB plb ; DBR = PBR = 04922 F8FE8A 8D 08 FC sta CRXFEOFF ; disabilita flash F00000 - F7FFFF4923 F8FE8D 8D 06 FC sta CRFWEOFF4924 F8FE90 5C F0 FF F8 jml _SysStart ; long jmp - bootstrap (banco $F8)49254926 F8FE94 _Unexpected:4927 F8FE94 40 rti4928 F8FE954929 ; software interrupt generated by 'cop' istruction4930 ;4931 ; stack frame4932 ; ---------4933 ; | PBR | 0F4934 ; ---------4935 ; | PCH | 0E4936 ; ---------4937 ; | PCL | 0D4938 ; ---------4939 ; | P | 0C4940 ; ---------4941 ; | B | 0B4942 ; ---------4943 ; | A | 0A4944 ; ---------4945 ; | XH | 094946 ; ---------4947 ; | XL | 084948 ; ---------4949 ; | YH | 074950 ; ---------4951 ; | YL | 064952 ; ---------4953 ; | DPH | 054954 ; ---------4955 ; | DPL | 044956 ; ---------4957 ; | DBR | 034958 ; ---------4959 ; | CNTH | 024960 ; --------- --> CNT parameters bytes count4961 ; | CNTL | 014962 ; ---------Tue Jul 17 11:11:08 2018 Page 424963 ;4964 ; equates for access stack offset data4965 000001 STKCNT .SET $014966 000006 STKYR .SET $064967 000008 STKXR .SET $084968 00000A STKCR .SET $0A4969 00000B STKBR .SET $0B4970 00000C STKSR .SET $0C4971 00000D STKPCL .SET $0D4972 00000F STKPBR .SET $0F4973 00000F STKNVAR .SET $0F49744975 ;USRCOP .SET $C049764977 ;EINVAL .EQU $0149784979 F8FE95 _COPEntry:4980 F8FE95 CPU16 ; A/MEM/X/Y -> 16 bit4981 F8FE95 C2 30 rep #(PMFLAG.OR.PXFLAG)4982 .LONGA on4983 .LONGI on4984 .MNLIST4985 F8FE97 48 pha ; save C in stack4986 F8FE98 DA phx ; save X(16) in stack4987 F8FE99 5A phy ; save Y(16) in stack4988 F8FE9A 0B phd ; save DPR in stack4989 F8FE9B 8B phb ; save DBR in stack4990 F8FE9C A9 00 00 lda #04991 F8FE9F AA tax ; X = 04992 F8FEA0 48 pha ; params byte count in the stack ( = 0)4993 F8FEA1 5B tcd ; set DPR = $00004994 F8FEA2 4B phk ; set DBR = PBR = $004995 F8FEA3 AB plb4996 F8FEA4 A3 0D lda STKPCL,s ; load PC saved in stack4997 F8FEA6 3A dec a ; pointer to signature byte4998 F8FEA7 85 51 sta COPPtr ; save long pointer4999 F8FEA9 CPU08 ; A/MEM/X/Y -> 8 bit5000 F8FEA9 E2 30 sep #(PMFLAG.OR.PXFLAG)5001 .LONGA off5002 .LONGI off5003 .MNLIST5004 F8FEAB 8A txa5005 F8FEAC EB xba ; B = 05006 F8FEAD A3 0F lda STKPBR,s ; PBR bank where COP was executed5007 F8FEAF 85 53 sta COPPtr+25008 F8FEB1 A3 0C lda STKSR,s ; saved P in stack5009 F8FEB3 AA tax5010 F8FEB4 29 FE and #~PCFLAG ; clear carry in saved P5011 F8FEB6 83 0C sta STKSR,s5012 F8FEB8 89 04 bit #PIFLAG ; check if IRQ was enabled5013 F8FEBA D0 01 bne ?045014 F8FEBC 58 cli ; enable IRQ5015 F8FEBD DA ?04: phx ; saved P in stack5016 F8FEBE A7 51 lda [COPPtr] ; fetch signature byte5017 F8FEC0 85 54 sta COPIdx5018 F8FEC2 CPU16 ; now C = $00XX5019 F8FEC2 C2 30 rep #(PMFLAG.OR.PXFLAG)Tue Jul 17 11:11:08 2018 Page 435020 .LONGA on5021 .LONGI on5022 .MNLIST5023 F8FEC4 0A asl a ; index * 45024 F8FEC5 0A asl a5025 F8FEC6 AA tax5026 F8FEC7 E0 00 02 cpx #$02005027 F8FECA 90 0B bcc ?05 ; range $00..$7F5028 F8FECC BF 00 FA F8 lda >SYSTBLE_ADDR,x ; address of cop vector range $80..$FF5029 F8FED0 A8 tay5030 F8FED1 BF 02 FA F8 lda >SYSTBLE_ADDR+2,x ; A = bank of cop vector, B = valid/params5031 F8FED5 80 06 bra ?065032 F8FED7 BC 00 FA ?05: ldy !SYSTBLE_ADDR,x ; address of cop vector range $00..$7F5033 F8FEDA BD 02 FA lda !SYSTBLE_ADDR+2,x ; A = bank of cop vector, B = valid/params5034 F8FEDD 8C ED FE ?06: sty ?08+15035 F8FEE0 CPU085036 F8FEE0 E2 30 sep #(PMFLAG.OR.PXFLAG)5037 .LONGA off5038 .LONGI off5039 .MNLIST5040 F8FEE2 30 38 bmi ?30 ; B<7> = 1 -> invalid function5041 F8FEE4 8D EF FE sta !?08+35042 F8FEE7 EB xba ; A = bytes number of params5043 F8FEE8 83 02 sta STKCNT+1,s ; take in account the 'phx' in ?04 !!5044 F8FEEA 68 pla ; saved P in stack5045 F8FEEB 4A lsr a ; pass carry to function5046 F8FEEC 22 00 00 00 ?08: jsl $0000005047 F8FEF0 90 0C bcc ?16 ; no error5048 F8FEF2 83 06 sta STKYR,s ; return error in Y5049 F8FEF4 A9 00 lda #05050 F8FEF6 83 07 sta STKYR+1,s5051 F8FEF8 A3 0C lda STKSR,s ; saved P in stack5052 F8FEFA 09 01 ora #PCFLAG ; set carry in saved P5053 F8FEFC 83 0C sta STKSR,s5054 ?16: ; epilogue code5055 F8FEFE CPU165056 F8FEFE C2 30 rep #(PMFLAG.OR.PXFLAG)5057 .LONGA on5058 .LONGI on5059 .MNLIST5060 F8FF00 A3 01 lda STKCNT,s ; number of params bytes in the stack5061 F8FF02 F0 11 beq ?20 ; no params -- skip stack cleaning5062 F8FF04 18 clc5063 F8FF05 3B tsc ; C = stack pointer5064 F8FF06 69 0F 00 adc #STKNVAR ; add size of stack vars5065 F8FF09 AA tax ; source pointer for data move5066 F8FF0A 63 01 adc STKCNT,s ; add params bytes count5067 F8FF0C A8 tay ; dest pointer for data move5068 F8FF0D A9 0E 00 lda #STKNVAR-1 ; move bytes count5069 F8FF10 44 00 00 mvp #0, #0 ; cleanup stack5070 F8FF13 98 tya ; new stack pointer5071 F8FF14 1B tcs5072 F8FF15 68 ?20: pla ; skip STKCNT5073 F8FF16 AB plb ; restore DBR5074 F8FF17 2B pld ; restore DPR5075 F8FF18 7A ply ; restore Y5076 F8FF19 FA plx ; restore XTue Jul 17 11:11:08 2018 Page 445077 F8FF1A 68 pla ; restore C5078 F8FF1B 40 rti ; restore P and return50795080 F8FF1C FA ?30: plx5081 F8FF1D 4C FE FE jmp ?1650825083 F8FF20 _BRKEntry:5084 F8FF20 CPU16 ; salva registri 16 bit5085 F8FF20 C2 30 rep #(PMFLAG.OR.PXFLAG)5086 .LONGA on5087 .LONGI on5088 .MNLIST5089 F8FF22 48 pha ; salva A5090 F8FF23 DA phx ; salva X5091 F8FF24 5A phy ; salva Y5092 F8FF25 0B phd5093 F8FF26 8B phb ; salva DBR5094 F8FF27 4B phk ; DBR = 0 = PBR(K)5095 F8FF28 AB plb ; DATA BANK 05096 F8FF29 CPU085097 F8FF29 E2 30 sep #(PMFLAG.OR.PXFLAG)5098 .LONGA off5099 .LONGI off5100 .MNLIST5101 F8FF2B 5C 06 00 FF jml BRKMON5102 F8FF2F5103 ; gestione interrupt non mascherabile linea NMI (RTI restore P and register size)5104 F8FF2F _NMIEntry:51055106 .EXTERN shutdown51075108 F8FF2F CPU16 ; salva registri 16 bit5109 F8FF2F C2 30 rep #(PMFLAG.OR.PXFLAG)5110 .LONGA on5111 .LONGI on5112 .MNLIST5113 F8FF31 48 pha ; salva A5114 F8FF32 DA phx ; salva X5115 F8FF33 5A phy ; salva Y5116 F8FF34 0B phd5117 F8FF35 8B phb ; salva DBR5118 F8FF36 4B phk ; DBR = 0 = PBR(K)5119 F8FF37 AB plb ; DATA BANK 05120 F8FF38 A9 00 00 lda #0 ; pagina 05121 F8FF3B 5B tcd5122 F8FF3C CPU08 ; imposta registri 8 bit5123 F8FF3C E2 30 sep #(PMFLAG.OR.PXFLAG)5124 .LONGA off5125 .LONGI off5126 .MNLIST51275128 F8FF3E AD 1D FD lda !VIA1+VIAIFR ; flag IFR VIA 15129 F8FF41 10 49 bpl ?100 ; no irq da VIA 15130 F8FF43 4A lsr a ; test CA2 (NMI KEYB)5131 F8FF44 90 2C bcc ?50 ; no CA25132 F8FF46 AE 42 FD ldx KBFR+25133 F8FF49 E0 83 cpx #KB_CTRLBREAKTue Jul 17 11:11:08 2018 Page 455134 F8FF4B D0 08 bne ?025135 F8FF4D A8 tay5136 F8FF4E A9 80 lda #$805137 F8FF50 04 4B tsb CtrlBrk5138 F8FF52 98 tya5139 F8FF53 80 15 bra ?405140 F8FF55 E0 84 ?02: cpx #KB_ALTSYSREQ5141 F8FF57 D0 11 bne ?065142 F8FF59 A2 01 ldx #CA2IFRB5143 F8FF5B 8E 1D FD stx VIA1+VIAIFR5144 F8FF5E 8E 45 FD stx KBCLRNMI ; azzera linea INT5145 F8FF61 A8 tay5146 F8FF62 A9 40 lda #$405147 F8FF64 04 4B tsb CtrlBrk5148 F8FF66 5C 09 00 FF jml ALTSYSMON5149 F8FF6A ?06:5150 F8FF6A A2 01 ?40: ldx #CA2IFRB5151 F8FF6C 8E 1D FD stx VIA1+VIAIFR5152 F8FF6F 8E 45 FD stx KBCLRNMI ; azzera linea INT5153 F8FF72 4A ?50: lsr a5154 F8FF73 4A lsr a5155 F8FF74 4A lsr a5156 F8FF75 90 15 bcc ?1005157 F8FF77 A2 08 ldx #CB2IFRB ; trigger5158 F8FF79 8E 1D FD stx VIA1+VIAIFR ; clear irq flag5159 F8FF7C A9 01 lda #$015160 F8FF7E 24 4B bit CtrlBrk5161 F8FF80 D0 0A bne ?1005162 F8FF82 04 4B tsb CtrlBrk51635164 F8FF845165 ?51: ;lda VIA1+VIAPRB5166 ;cmp VIA1+VIAPRB5167 ;bne ?515168 ;and #$105169 ;beq ?5151705171 ; OFF command5172 ;ldx #RTCEXTCTRLA5173 ;stx RTCALE5174 ;lda #$08 ; POWERON -> HIGH5175 ;tsb RTCDATA5176 F8FF845177 F8FF84 22 C3 20 F8 jsl shutdown5178 F8FF88 A9 01 lda #$015179 F8FF8A 14 4B trb CtrlBrk5180 F8FF8C51815182 F8FF8C ?100:5183 F8FF8C CPU16 ; ripristina registri 16 bit5184 F8FF8C C2 30 rep #(PMFLAG.OR.PXFLAG)5185 .LONGA on5186 .LONGI on5187 .MNLIST5188 F8FF8E AB plb ; ripristina DBR5189 F8FF8F 2B pld5190 F8FF90 7A ply ; ripristina YTue Jul 17 11:11:08 2018 Page 465191 F8FF91 FA plx ; ripristina X5192 F8FF92 68 pla ; ripristina A5193 F8FF93 40 rti5194 F8FF94 LONG_OFF5195 .LONGA off5196 .LONGI off5197 .MNLIST51985199 ; gestione interrupt linea IRQ (RTI restore P and register size)5200 F8FF94 _IRQEntry:5201 F8FF94 CPU16 ; salva registri 16 bit5202 F8FF94 C2 30 rep #(PMFLAG.OR.PXFLAG)5203 .LONGA on5204 .LONGI on5205 .MNLIST5206 F8FF96 48 pha ; salva A5207 F8FF97 DA phx ; salva X5208 F8FF98 5A phy ; salva Y5209 F8FF99 0B phd ; salva DP5210 F8FF9A 8B phb ; salva DBR5211 F8FF9B 4B phk ; DBR = 0 = PBR(K)5212 F8FF9C AB plb ; DATA BANK 05213 F8FF9D A9 00 00 lda #05214 F8FFA0 5B tcd ; imposta pagina 05215 F8FFA1 CPU08 ; imposta registri 8 bit5216 F8FFA1 E2 30 sep #(PMFLAG.OR.PXFLAG)5217 .LONGA off5218 .LONGI off5219 .MNLIST5220 F8FFA3 AE 47 FD ldx IRQVECTR ; legge vettore IRQ (x2)5221 F8FFA6 FC 00 F0 jsr (intsr,x) ; esegue subroutine IntSr5222 F8FFA9 CPU16 ; ripristina registri 16 bit5223 F8FFA9 C2 30 rep #(PMFLAG.OR.PXFLAG)5224 .LONGA on5225 .LONGI on5226 .MNLIST5227 F8FFAB AB plb ; ripristina DBR5228 F8FFAC 2B pld ; ripristina DP5229 F8FFAD 7A ply ; ripristina Y5230 F8FFAE FA plx ; ripristina X5231 F8FFAF 68 pla ; ripristina A5232 F8FFB0 40 rti5233 F8FFB1 LONG_OFF5234 .LONGA off5235 .LONGI off5236 .MNLIST5237 F8FFB15238 ;----------------------------------------------------------5239 ; ---- VETTORI CPU5240 ;----------------------------------------------------------5241 F8FFB15242 .SYSVECTRS5243 F8FFE05244 ; vettori modo nativo5245 F8FFE0 0000 .DW 0 ; FFE05246 F8FFE2 0000 .DW 0 ; FFE25247 F8FFE4 95FE .DW _COPEntry ; FFE4 -> COPTue Jul 17 11:11:08 2018 Page 475248 F8FFE6 20FF .DW _BRKEntry ; FFE6 -> BRK5249 F8FFE8 94FE .DW _Unexpected ; FFE8 -> ABORT (non usato)5250 F8FFEA 2FFF .DW _NMIEntry ; FFEA -> NMI5251 F8FFEC 94FE .DW _Unexpected ; FFEC -> riservato5252 F8FFEE 94FF .DW _IRQEntry ; FFEE -> IRQ52535254 ; nel banco $F85255 F8FFF0 _SysStart:5256 F8FFF0 4C 86 12 jmp !SysStart5257 F8FFF3 00 .DB $005258 F8FFF45259 ; vettori modo emulazione5260 F8FFF4 95FE .DW _COPEntry ; FFF4 -> COP5261 F8FFF6 94FE .DW _Unexpected ; FFF6 -> riservato5262 F8FFF8 94FE .DW _Unexpected ; FFF8 -> ABORT (non usato)5263 F8FFFA 2FFF .DW _NMIEntry ; FFFA -> NMI5264 F8FFFC 00FE .DW _RSTEntry ; FFFC -> RESET5265 F8FFFE 94FF .DW _IRQEntry ; FFFE -> IRQ52665267 F900005268 .END _RSTEntryLines Assembled : 4746 Errors : 0