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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0168.PLD)

  1  || FILE:   #0168.PLD
  2  || PROJ:   20170501
  3  ||         FD-02 FDC/ATA/DMA BOARD
  4  || 
  5  || PART:   G26CV12-#0168
  6  ||
  7  || DEV :   GAL26CV12
  8  ||
  9  ||         DESC:   ATA CONTROL
 10  ||
 11  |
 12  |GAL26CV12
 13  |
 14  || INPUT
 15  |  1:A0, 2:A1, 3:A2, 4:A3, 5:PHI2, 6:IO, 8:RW, 9:PHI0, 10:DMA, 
 16  | 11:GEN, 12:MW0, 13:IOR, 14:IOW, 28:INT,
 17  || OUTPUT 
 18  |  15:WRH, 16:WRL, 17:WRD, 18:RDH, 19:RDD, 20:WE, 22:GA, 23:RD,
 19  |  24:RDL, 25:CS0, 26:CS1, 27:IRQ
 20  |
 21  | ACTIVE-LOW: CS0, CS1, WRH, WRL, WRD, RDH, RDL, RDD, RD, WE, GA
 22  
 23  |
 24  |
 25  | SIGNATURE: "0168    "
 26  |
 27  || --------------------------------------------------------
 28  || common signals when dma disabled (DMA = 1 => cpu access)
 29  ||
 30  | ATA  = DMA & IO'                 || ata0 => FDA0-FDAF ata1 => FDB0-FDBF
 31  | S01  = ATA & A3' & A2' & A1' & A0        || FDB1
 32  | S02  = ATA & A3' & A2' & A1              || FDB2-FDB3
 33  | S04  = ATA & A3' & A2                    || FDB4-FDB7
 34  | S08  = ATA & A3  & A2' & A1' & A0'       || FDB8
 35  | S0A  = ATA & A3  & A2' & A1  & A0'       || FDBA
 36  | S0B  = ATA & A3  & A2' & A1  & A0        || FDBB
 37  | S0E  = ATA & A3  & A2  & A1  & A0'       || FDBE
 38  | SATA = (S01 # S02 # S04 # S08 # S0E)     || valid ata registers
 39  | SATAX = (S01 # S02 # S04 # S0E)  || valid ata registers (no data reg.)
 40  
 41  | CRD  = SATA & RW  & PHI2         || cpu read ata
 42  || CWR0 = SATA & RW' & PHI2 & MW0  || cpu write ata (02)
 43  
 44  || NOTA: questo funziona
 45  | CWR0 = SATAX & RW' & PHI2 & MW0  || cpu write ata (02)
 46  | CWR2 = S08 & RW' & PHI0 & PHI2 & MW0'    || cpu write ata (02)
 47  
 48  || PROVA:
 49  | CWR0 = SATAX & RW' & PHI2                || cpu write ata (02)
 50  | CWR2 = S08 & RW' & PHI0 & PHI2   || cpu write ata (02)
 51  
 52  | CWE  = (CWR0 # CWR2)                     || cpu write ata
 53  
 54  ||
 55  || signals when dma0 access ata


 56  | DRD  = DMA' & IOR'                   || dma read  ata port 0
 57  | DWR  = DMA' & IOW'                       || dma write ata port 0
 58  ||
 59  || output signals
 60  || WRL  = S0A & RW' & PHI0         || cpu write low  latch
 61  || WRH  = S0B & RW' & PHI0         || cpu write high latch
 62  | WRLA  = S0A & RW' & PHI2 & MW0           || cpu write low  latch
 63  | WRHA  = S0B & RW' & PHI2 & MW0           || cpu write high latch
 64  | WRLB  = S0A & RW' & PHI0 & MW0'          || cpu write low  latch
 65  | WRHB  = S0B & RW' & PHI0 & MW0'          || cpu write high latch
 66  | WRL = (WRLA # WRLB)
 67  | WRH = (WRHA # WRHB)
 68  | RDL  = S0A & RW  & PHI2          || cpu read  low  latch
 69  | RDH  = S0B & RW  & PHI2          || cpu read  high latch
 70  | WRD  = S08 & RW' & GEN           || cpu dummy write latch
 71  | RDD  = S08 & RW  & PHI2          || cpu dummy read  latch
 72  | RD   = CRD # DRD                 || cpu read  ata port
 73  | WE   = CWE # DWR                 || cpu write ata port
 74  | GA   = (S01 # S02 # S04 # S0E)   || enable internal data bus
 75  | CS0  = (S01 # S02 # S04 # S08) & GEN     || enable ata port /CS0
 76  || CS0  = ((S01 # S02 # S04) & GEN) # S08  || enable ata port /CS0
 77  
 78  | CS1  = S0E & GEN                 || enable ata port /CS1
 79  | IRQ  = INT'                              || int. inversion



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/25/17  11:04 am  (Tuesday)
I203  Memory usage 110K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0168.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

WRL              104   A0' A1  A2' A3  PHI2  IO' RW' DMA  MW0  
                 105   A0' A1  A2' A3  IO' RW' PHI0  DMA  MW0' 

WRH              113   A0  A1  A2' A3  PHI2  IO' RW' DMA  MW0  
                 114   A0  A1  A2' A3  IO' RW' PHI0  DMA  MW0' 

RDL               29   A0' A1  A2' A3  PHI2  IO' RW  DMA  

RDH               86   A0  A1  A2' A3  PHI2  IO' RW  DMA  

WRD               95   A0' A1' A2' A3  IO' RW' DMA  GEN  

RDD               75   A0' A1' A2' A3  PHI2  IO' RW  DMA  

RD                38   A0' A1' A2' A3  PHI2  IO' RW  DMA  
                  39   A0' A1  A2  A3  PHI2  IO' RW  DMA  
                  40   A0  A1' A2' A3' PHI2  IO' RW  DMA  
                  41   A1  A2' A3' PHI2  IO' RW  DMA  
                  42   A2  A3' PHI2  IO' RW  DMA  
                  43   DMA' IOR' 

WE                62   A0' A1' A2' A3  PHI2  IO' RW' PHI0  DMA  MW0' 
                  63   A0' A1' A2' A3  PHI2  IO' RW' PHI0  DMA  
                  64   A0' A1  A2  A3  PHI2  IO' RW' DMA  MW0  
                  65   A0  A1' A2' A3' PHI2  IO' RW' DMA  MW0  
                  66   A0' A1  A2  A3  PHI2  IO' RW' DMA  
                  67   A0  A1' A2' A3' PHI2  IO' RW' DMA  
                  68   A1  A2' A3' PHI2  IO' RW' DMA  MW0  
                  69   A1  A2' A3' PHI2  IO' RW' DMA  
                  70   A2  A3' PHI2  IO' RW' DMA  MW0  
                  71   A2  A3' PHI2  IO' RW' DMA  
                  72   DMA' IOW' 

GA                49   A0' A1  A2  A3  IO' DMA  
                  50   A0  A1' A2' A3' IO' DMA  
                  51   A1  A2' A3' IO' DMA  
                  52   A2  A3' IO' DMA  

CS0               20   A0' A1' A2' A3  IO' DMA  GEN  
                  21   A0  A1' A2' A3' IO' DMA  GEN  
                  22   A1  A2' A3' IO' DMA  GEN  
                  23   A2  A3' IO' DMA  GEN  

CS1               11   A0' A1  A2  A3  IO' DMA  GEN  

IRQ                2   INT' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A0              0        -    -    -        High    (Clock)
  2.     A1              4        -    -    -        High     
  3.     A2              8        -    -    -        High     
  4.     A3             12        -    -    -        High     
  5.     PHI2           16        -    -    -        High     
  6.     IO             20        -    -    -        High     
  8.     RW             24        -    -    -        High     
  9.     PHI0           28        -    -    -        High     
 10.     DMA            32        -    -    -        High     
 11.     GEN            36        -    -    -        High     
 12.     MW0            40        -    -    -        High     
 13.     IOR            44        -    -    -        High     
 14.     IOW            48        -    -    -        High     
 15.     WRH            51      112    9    2        Low     (Three-state)
 16.     WRL            47      103    9    2        Low     (Three-state)
 17.     WRD            43       94    9    1        Low     (Three-state)
 18.     RDH            39       85    9    1        Low     (Three-state)
 19.     RDD            35       74   11    1        Low     (Three-state)
 20.     WE             31       61   13   11        Low     (Three-state)
 22.     GA             27       48   13    4        Low     (Three-state)
 23.     RD             23       37   11    6        Low     (Three-state)
 24.     RDL            19       28    9    1        Low     (Three-state)
 25.     CS0            15       19    9    4        Low     (Three-state)
 26.     CS1            11       10    9    1        Low     (Three-state)
 27.     IRQ             6        1    9    1        High    (Three-state)
 28.     INT             2        -    -    -        High     
 29.     -               -        0    1    0                 
 30.     -               -      121    1    0                 
                                    ---- ----
                                     122   35  (29%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL26CV12
*
QP28* QF6432* QV1024*
F0*
L0052 1111111111111111111111111111111111111111111111111111*
L0104 1110111111111111111111111111111111111111111111111111*
L0520 1111111111111111111111111111111111111111111111111111*
L0572 1011011101110111111110111111111101110111111111111111*
L0988 1111111111111111111111111111111111111111111111111111*
L1040 1011101110110111111110111111111101110111111111111111*
L1092 0111101110111011111110111111111101110111111111111111*
L1144 1111011110111011111110111111111101110111111111111111*
L1196 1111111101111011111110111111111101110111111111111111*
L1456 1111111111111111111111111111111111111111111111111111*
L1508 1011011110110111011110110111111101111111111111111111*
L1924 1111111111111111111111111111111111111111111111111111*
L1976 1011101110110111011110110111111101111111111111111111*
L2028 1011011101110111011110110111111101111111111111111111*
L2080 0111101110111011011110110111111101111111111111111111*
L2132 1111011110111011011110110111111101111111111111111111*
L2184 1111111101111011011110110111111101111111111111111111*
L2236 1111111111111111111111111111111110111111111110111111*
L2496 1111111111111111111111111111111111111111111111111111*
L2548 1011011101110111111110111111111101111111111111111111*
L2600 0111101110111011111110111111111101111111111111111111*
L2652 1111011110111011111110111111111101111111111111111111*
L2704 1111111101111011111110111111111101111111111111111111*
L3172 1111111111111111111111111111111111111111111111111111*
L3224 1011101110110111011110111011011101111111101111111111*
L3276 1011101110110111011110111011011101111111111111111111*
L3328 1011011101110111011110111011111101111111011111111111*
L3380 0111101110111011011110111011111101111111011111111111*
L3432 1011011101110111011110111011111101111111111111111111*
L3484 0111101110111011011110111011111101111111111111111111*
L3536 1111011110111011011110111011111101111111011111111111*
L3588 1111011110111011011110111011111101111111111111111111*
L3640 1111111101111011011110111011111101111111011111111111*
L3692 1111111101111011011110111011111101111111111111111111*
L3744 1111111111111111111111111111111110111111111111111011*
L3848 1111111111111111111111111111111111111111111111111111*
L3900 1011101110110111011110110111111101111111111111111111*
L4420 1111111111111111111111111111111111111111111111111111*
L4472 0111011110110111011110110111111101111111111111111111*
L4888 1111111111111111111111111111111111111111111111111111*
L4940 1011101110110111111110111011111101110111111111111111*
L5356 1111111111111111111111111111111111111111111111111111*
L5408 1011011110110111011110111011111101111111011111111111*
L5460 1011011110110111111110111011011101111111101111111111*
L5824 1111111111111111111111111111111111111111111111111111*
L5876 0111011110110111011110111011111101111111011111111111*
L5928 0111011110110111111110111011011101111111101111111111*
L6344 1101010101010101010101010011000000110001001101100011*
L6396 100000100000001000000010000000100000*
C283E*

I202  7/25/17  11:04 am  (Tuesday)

I203  Memory usage 12K
I204  Elapsed time 1 second