Subversion Repositories MB01 Project

||      FILE:   #0168.PLD
||      PROJ:   20170501
||              FD-02 FDC/ATA/DMA BOARD
||      
||      PART:   G26CV12-#0168
||
||      DEV :   GAL26CV12
||
||      DESC:   ATA CONTROL
||
|
|GAL26CV12
|
|| INPUT
|  1:A0, 2:A1, 3:A2, 4:A3, 5:PHI2, 6:IO, 8:RW, 9:PHI0, 10:DMA, 
| 11:GEN, 12:MW0, 13:IOR, 14:IOW, 28:INT,
|| OUTPUT 
|  15:WRH, 16:WRL, 17:WRD, 18:RDH, 19:RDD, 20:WE, 22:GA, 23:RD,
|  24:RDL, 25:CS0, 26:CS1, 27:IRQ
|
| ACTIVE-LOW: CS0, CS1, WRH, WRL, WRD, RDH, RDL, RDD, RD, WE, GA

|
|
| SIGNATURE: "0168    "
|
|| --------------------------------------------------------
|| common signals when dma disabled (DMA = 1 => cpu access)
||
| ATA  = DMA & IO'                      || ata0 => FDA0-FDAF ata1 => FDB0-FDBF
| S01  = ATA & A3' & A2' & A1' & A0     || FDB1
| S02  = ATA & A3' & A2' & A1           || FDB2-FDB3
| S04  = ATA & A3' & A2                 || FDB4-FDB7
| S08  = ATA & A3  & A2' & A1' & A0'    || FDB8
| S0A  = ATA & A3  & A2' & A1  & A0'    || FDBA
| S0B  = ATA & A3  & A2' & A1  & A0     || FDBB
| S0E  = ATA & A3  & A2  & A1  & A0'    || FDBE
| SATA = (S01 # S02 # S04 # S08 # S0E)  || valid ata registers
| SATAX = (S01 # S02 # S04 # S0E)       || valid ata registers (no data reg.)

| CRD  = SATA & RW  & PHI2              || cpu read ata
|| CWR0 = SATA & RW' & PHI2 & MW0       || cpu write ata (02)
| CWR0 = SATAX & RW' & PHI2 & MW0       || cpu write ata (02)
| CWR2 = S08 & RW' & PHI0 & PHI2 & MW0' || cpu write ata (02)

|| CWR1 = SATA & RW' & PHI0 & MW0'      || cpu write ata (00)
|| CWE  = (CWR0 # CWR1)                 || cpu write ata
| CWE  = (CWR0 # CWR2)                  || cpu write ata

||
|| signals when dma0 access ata
| DRD  = DMA' & IOR'                    || dma read  ata port 0
| DWR  = DMA' & IOW'                    || dma write ata port 0
||
|| output signals
|| WRL  = S0A & RW' & PHI0              || cpu write low  latch
|| WRH  = S0B & RW' & PHI0              || cpu write high latch
| WRLA  = S0A & RW' & PHI2 & MW0                || cpu write low  latch
| WRHA  = S0B & RW' & PHI2 & MW0                || cpu write high latch
| WRLB  = S0A & RW' & PHI0 & MW0'               || cpu write low  latch
| WRHB  = S0B & RW' & PHI0 & MW0'               || cpu write high latch
| WRL = (WRLA # WRLB)
| WRH = (WRHA # WRHB)
| RDL  = S0A & RW  & PHI2               || cpu read  low  latch
| RDH  = S0B & RW  & PHI2               || cpu read  high latch
| WRD  = S08 & RW' & GEN                || cpu dummy write latch
| RDD  = S08 & RW  & PHI2               || cpu dummy read  latch
| RD   = CRD # DRD                      || cpu read  ata port
| WE   = CWE # DWR                      || cpu write ata port
| GA   = (S01 # S02 # S04 # S0E)        || enable internal data bus
| CS0  = (S01 # S02 # S04 # S08) & GEN  || enable ata port /CS0
|| CS0  = ((S01 # S02 # S04) & GEN) # S08       || enable ata port /CS0

| CS1  = S0E & GEN                      || enable ata port /CS1
| IRQ  = INT'                           || int. inversion