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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0167.PLD)

  1  || FILE:   #0167.PLD
  2  || PROJ:   20170501
  3  ||         FD-02 FDC/ATA/DMA BOARD
  4  || 
  5  || PART:   G18V10-#0167
  6  ||
  7  || DEV :   GAL18V10
  8  ||
  9  ||         DESC:   DMA CONTROL
 10  ||
 11  |
 12  |GAL18V10
 13  |
 14  || INPUT
 15  |  1:CLK, 2:AEN0, 3:HRQ0, 4:RES, 5:DMA, 6:FDC, 7:HRQ1, 8:AEN1, 9:EOP1,
 16  || OUTPUT 
 17  |  19:Q0, 18:HLD0, 17:OE0, 16:PRES, 15:TC, 14:MGE, 13:OE1, 12:HLD1, 11:Q1
 18  |
 19  | ACTIVE-LOW: OE0, OE1
 20  |
 21  | SIGNATURE: "0167    "
 22  |
 23  || --------------------------------------------------------
 24  ||
 25  |  Q[1..0] = CLK // Q[1..0] + 1            || Q0 = CLK/2, Q1 = CLK/4 
 26  |  AEN0X = AEN0 & DMA' & FDC               || dma0 enable
 27  |  AEN1X = AEN1 & DMA' & FDC'              || dma1 enable
 28  |  OE0 = AEN0X                             || dma0 bus enable
 29  |  OE1 = AEN1X                             || dma1 bus enable
 30  |  HLD0 = HRQ0 & DMA' & FDC                || dma0 hold bus
 31  |  HLD1 = HRQ1 & DMA' & FDC'               || dma1 hold bus
 32  |  TC = EOP1'                              || terminal count for fdc
 33  |  PRES = RES'                             || reset positive pulse
 34  |  MGE = AEN0X # AEN1X                     || ram gate enable for cpu access



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  4/25/17  9:11 pm  (Tuesday)
I203  Memory usage 77K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0167.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

Q1                78   Q0' Q1  
                  79   Q0  Q1' 

Q0                 2   Q0' 

OE0               20   AEN0  DMA' FDC  

MGE               49   AEN0  DMA' FDC  
                  50   DMA' FDC' AEN1  

OE1               60   DMA' FDC' AEN1  

HLD0              11   HRQ0  DMA' FDC  

HLD1              69   DMA' FDC' HRQ1  

TC                38   EOP1' 

PRES              29   RES' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     CLK             0        -    -    -        High    (Clock)
  2.     AEN0            4        -    -    -        High     
  3.     HRQ0            8        -    -    -        High     
  4.     RES            12        -    -    -        High     
  5.     DMA            16        -    -    -        High     
  6.     FDC            20        -    -    -        High     
  7.     HRQ1           24        -    -    -        High     
  8.     AEN1           28        -    -    -        High     
  9.     EOP1           34       86    9    0        High    (Registered)
 11.     Q1             33       77    9    2        High    (Registered)
 12.     HLD1           30       68    9    1        High    (Three-state)
 13.     OE1            27       59    9    1        Low     (Three-state)
 14.     MGE            22       48   11    2        High    (Three-state)
 15.     TC             18       37   11    1        High    (Three-state)
 16.     PRES           14       28    9    1        High    (Three-state)
 17.     OE0            11       19    9    1        Low     (Three-state)
 18.     HLD0            6       10    9    1        High    (Three-state)
 19.     Q0              3        1    9    1        High    (Registered)
 21.     -               -        0    1    0                 
 22.     -               -       95    1    0                 
                                    ---- ----
                                      96   11  (11%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL18V10
*
QP20* QF3540* QV1024*
F0*
L0036 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0072 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0360 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0396 11 11 11 11 01 11 11 11 10 11 01 11 11 11 11 11 11 11 *
L0684 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0720 11 11 01 11 11 11 11 11 10 11 01 11 11 11 11 11 11 11 *
L1008 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1044 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
L1332 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 *
L1728 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1764 11 11 01 11 11 11 11 11 10 11 01 11 11 11 11 11 11 11 *
L1800 11 11 11 11 11 11 11 11 10 11 10 11 11 11 01 11 11 11 *
L2124 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2160 11 11 11 11 11 11 11 11 10 11 10 11 11 11 01 11 11 11 *
L2448 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2484 11 11 11 11 11 11 11 11 10 11 10 11 01 11 11 11 11 11 *
L2772 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2808 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 *
L2844 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 *
L3456 10 11 01 11 11 11 01 11 10 11 00 11 00 00 00 11 00 01 *
L3492 00 11 01 10 00 11 01 11 00 10 00 00 00 10 00 00 00 10 *
L3528 00 00 00 10 00 00 *
C5DFC*

I202  4/25/17  9:11 pm  (Tuesday)
I203  Memory usage 5K
I204  Elapsed time 1 second