Subversion Repositories MB01 Project

||      FILE:   #0167.PLD
||      PROJ:   20170501
||              FD-02 FDC/ATA/DMA BOARD
||      
||      PART:   G18V10-#0167
||
||      DEV :   GAL18V10
||
||      DESC:   DMA CONTROL
||
|
|GAL18V10
|
|| INPUT
|  1:CLK, 2:AEN0, 3:HRQ0, 4:RES, 5:DMA, 6:FDC, 7:HRQ1, 8:AEN1, 9:EOP1,
|| OUTPUT 
|  19:Q0, 18:HLD0, 17:OE0, 16:PRES, 15:TC, 14:MGE, 13:OE1, 12:HLD1, 11:Q1
|
| ACTIVE-LOW: OE0, OE1, MGE
|
| SIGNATURE: "0167    "
|
|| --------------------------------------------------------
||
|  Q[1..0] = CLK // Q[1..0] + 1         || Q0 = CLK/2, Q1 = CLK/4 
|  AEN0X = AEN0 & DMA' & FDC            || dma0 enable
|  AEN1X = AEN1 & DMA' & FDC'           || dma1 enable
|  OE0 = AEN0X                          || dma0 bus enable
|  OE1 = AEN1X                          || dma1 bus enable
|  HLD0 = HRQ0 & DMA' & FDC             || dma0 hold bus
|  HLD1 = HRQ1 & DMA' & FDC'            || dma1 hold bus
|  TC = EOP1'                           || terminal count for fdc
|  PRES = RES'                          || reset positive pulse
||  MGE = AEN0X # AEN1X                 || ram gate enable for cpu access
|  MGE = OE0 & OE1                      || ram gate enable for cpu access