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|| FILE: #0166.PLD|| PROJ: 20170501|| FD-02 FDC/ATA/DMA BOARD|||| PART: G26CV12-#0166|||| DEV : GAL26CV12|||| DESC: RAM ACCESS CONTROL||||GAL26CV12||| INPUT| 1:CA0, 2:MA0, 3:CX2, 4:PHI2, 5:MW0, 6:DMA, 8:PHI0, 9:OE0, 10:OE1,| 11:S1M, 12:ATA0, 13:FDC, 14:ALT, 28:RW,|| OUTPUT| 15:MWE, 16:MRD, 17:CEL, 18:CEH, 19:CE1, 20:OEL, 22:OEH, 23:BE0,| 24:BE1, 25:EV, 26:ODD, 27:AEN|| ACTIVE-LOW: MWE, MRD, CEL, CEH, CE1, OEL, OEH, BE0, BE1, EV, ODD||| SIGNATURE: "0166 "||| --------------------------------------------------------|| common signals when dma disabled (DMA = 1 => cpu access)||| MMR0 = CX2' & DMA & OE0 & RW & PHI2 || cpu read ram| MMR1 = CX2' & DMA & OE1 & RW & PHI2 || cpu read ram| MMW0 = CX2' & DMA & OE0 & RW' & PHI2 & MW0 || cpu read ram (02)| MMW1 = CX2' & DMA & OE0 & RW' & PHI0 & MW0' || cpu read ram (00)| MMW2 = CX2' & DMA & OE1 & RW' & PHI2 & MW0 || cpu read ram (02)| MMW3 = CX2' & DMA & OE1 & RW' & PHI0 & MW0' || cpu read ram (00)| MMRD = MMR0 # MMR1 || cpu read ram strobe| MMWR = MMW0 # MMW1 # MMW2 # MMW3 || cpu write ram strobe||| MLC0 = CX2' & DMA & OE0 & S1M' & CA0' || cpu access 1Mb even ram| MLC1 = CX2' & DMA & OE1 & S1M' & CA0' || cpu access 1Mb even ram| MHC0 = CX2' & DMA & OE0 & S1M' & CA0 || cpu access 1Mb odd ram| MHC1 = CX2' & DMA & OE1 & S1M' & CA0 || cpu access 1Mb odd ram| MLCC = MLC0 # MLC1 || cpu access 1Mb even ram| MHCC = MHC0 # MHC1 || cpu access 1Mb odd ram| MLCCP = (MLC0 # MLC1) & PHI2 || cpu access 1Mb even ram| MHCCP = (MHC0 # MHC1) & PHI2 || cpu access 1Mb odd ram| M2C0 = CX2' & DMA & OE0 & S1M & PHI2 || cpu access 128Kb ram| M2C1 = CX2' & DMA & OE1 & S1M & PHI2 || cpu access 128Kb ram| M2CC = (M2C0 # M2C1) || cpu access 128Kb ram|||| common signals when dma enabled (DMA = 0)| M1D0 = DMA' & OE0' & FDC || dma0 access 1Mb ram| M1D1 = DMA' & OE1' & FDC' & ALT' || dma1 access 1Mb ram| M2D1 = DMA' & OE1' & FDC' & ALT || dma1 access 128kb ram|||| output signals| MWE = DMA ?? MMWR || write ram strobe 3-states| MRD = DMA ?? MMRD || read ram strobe 3-states| CEL = MLCCP # M1D0 # M1D1 || enable even ram 1Mb| CEH = MHCCP # M1D0 # M1D1 || enable odd ram 1Mb| CE1 = M2CC # M2D1 || enable ram 128Kb| OEL = MLCC || enable internal ram 1Mb data bus for cpu access| OEH = MHCC || enable internal ram 1Mb data bus for cpu access| BE0 = DMA' & OE0' & ATA0' & FDC || ata0 data bus to 1Mb ram| BE1 = DMA' & OE0' & ATA0 & FDC || ata1 data bus to 1Mb ram| EV = DMA' & OE1' & FDC' & ALT' & MA0' || fdc data bus to even 1Mb| ODD = DMA' & OE1' & FDC' & ALT' & MA0 || fdc data bus to odd 1Mb| AEN = DMA' || cpu address enable