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|| FILE: #0166.PLD|| PROJ: 20170501|| FD-02 FDC/ATA/DMA BOARD|||| PART: G22V10-#0050|||| DEV : GAL22V10|||| DESC: RAM ACCESS CONTROL||||GAL22V10||| input signal description|| GEN = gate enable|| /DMA = dma enable|| DIR = dma data bus direction (1 => read, 0 => write)|| /S1M = enable 1Mb ram bank (otherwise 128k)|| ATA = dma ata port select (0 => port 0, 1 => port 1)|| /FDC = enable dma for fdc operation (otherwise ata)|| /ALT = enable dma1 to use 1Mb ram bank (otherwise use 128Kb)|||| INPUT| 1:MA0, 2:CX2, 3:GEN, 4:OE0, 5:OE1, 6:DMA, 7:RW, 8:DIR,| 9:S1M, 10:ATA, 11:FDC, 13:ALT,|| OUTPUT| 14:CEL, 15:CEH, 16:CER, 17:ENL, 18:ENH, 19:BE0,| 20:BE1, 21:MDIR, 22:AEN, 23:A16E|| ACTIVE-LOW: CEL, CEH, CER, ENL, ENH, BE0, BE1, A16E||| SIGNATURE: "0166 "||| --------------------------------------------------------|| common signals when dma disabled (DMA = 1 => cpu access)||| RAM0 = CX2' & DMA & OE0 || cpu access ram (dma0 = off)| RAM1 = CX2' & DMA & OE1 || cpu access ram (dma1 = off)| MLC0 = RAM0 & S1M' & MA0' || cpu access 1Mb even ram| MLC1 = RAM1 & S1M' & MA0' || cpu access 1Mb even ram| MHC0 = RAM0 & S1M' & MA0 || cpu access 1Mb odd ram| MHC1 = RAM1 & S1M' & MA0 || cpu access 1Mb odd ram| MLCA = MLC0 # MLC1 || cpu access 1Mb even ram| MHCA = MHC0 # MHC1 || cpu access 1Mb odd ram| MLCS = MLCA & GEN || cpu select 1Mb even ram| MHCS = MHCA & GEN || cpu select 1Mb odd ram| MMC0 = RAM0 & S1M || cpu access 128Kb ram| MMC1 = RAM1 & S1M || cpu access 128Kb ram| MMCS = (MMC0 # MMC1) & GEN || cpu select 128Kb ram||| CDIR = RW & DMA & OE0 & OE1 || cpu bus direction to 1Mb ram|||| common signals when dma enabled (DMA = 0)| D0ON = DMA' & OE0' & OE1 & FDC || dma0 master| D1ON = DMA' & OE0 & OE1' & FDC' || dma1 master| D1MB = D1ON & ALT' || dma1 access 1Mb ram| D1MBL = D1MB & MA0' || dma1 access 1Mb even ram| D1MBH = D1MB & MA0 || dma1 access 1Mb odd ram| D128K = D1ON & ALT || dma1 access 128kb ram||| D0DIR = DIR & DMA' & FDC || dma0 bus direction to 1Mb ram| D1DIR = DIR' & DMA' & FDC' || dma1 bus direction to 1Mb ram|||| output signals| CEL = MLCS # D0ON # D1MBL || select even ram 1Mb| CEH = MHCS # D0ON # D1MBH || select odd ram 1Mb| CER = MMCS # D128K || select ram 128Kb| ENL = MLCA # D1MBL || data bus to 1Mb even ram| ENH = MHCA # D1MBH || data bus to 1Mb even ram| BE0 = D0ON & ATA' || ata0 data bus to 1Mb ram| BE1 = D0ON & ATA || ata1 data bus to 1Mb ram| AEN = DMA' || cpu address enable| A16E = D1ON || enable extern A16 line for dma1| MDIR = CDIR # D0DIR # D1DIR || bus direction to 1Mb ram