Subversion Repositories MB01 Project

||      FILE:   #0165.PLD
||      PROJ:   20170501
||              FD-02 FDC/ATA/DMA BOARD
||      
||      PART:   G26CV12-#0165
||
||      DEV :   GAL26CV12
||
||      DESC:   DECODER I/O
||
|
|GAL26CV12
|
|| INPUT
|  1:A1, 2:A2, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2, 
| 11:CX2, 12:FDC, 13:PHI0, 14:DMAE, 28:MW0,
|| OUTPUT 
|  15:CS0, 16:CS1, 17:CS2, 18:CS3, 19:CS4, 20:DBE, 22:GDD, 23:CS5,
|  24:RD, 25:WE, 26:IOR, 27:IOW
|
| ACTIVE-LOW: CS0, CS1, CS2, CS3, DBE, GDD, CS5, RD, WE, IOR, IOW
|
|
| SIGNATURE: "0165    "
|
|| --------------------------------------------------------
|| common signals when dma disbled (DMAE = 1 => cpu access)
||
|  SCX2  = CX2' & DMAE                  || ram select when cpu access
|  SFDC  = FDC' & DMAE                  || fdc  select FD58-FD5F
|  DMA0  = IO' & A6' & A5' & A4' & DMAE || dma0 select FD80-FD8F
|  DMA1  = IO' & A6' & A5' & A4  & DMAE || dma1 select FD90-FD9F
|  ATA0  = IO' & A6' & A5  & A4' & DMAE || ata0 select FDA0-FDAF
|  ATA1  = IO' & A6' & A5  & A4  & DMAE || ata1 select FDB0-FDBF
|  VIA   = IO' & A6  & A5' & A4'        || via  select FDC0-FDCF (always)
|| usb host CH376/CH375 select FDD0-FDD1 (always)
|  USB   = IO' & A6  & A5' & A4  & A3' & A2' & A1'
||
|  FDCR  = SFDC & RW  & PHI2            || cpu read  fdc  02 sync
|  FDCW0 = SFDC & RW' & PHI2 & MW0'     || cpu write fdc  02 sync
|  FDCW1 = SFDC & RW' & PHI0 & MW0      || cpu write fdc  00 sync
|  DM0R  = DMA0 & RW  & PHI2            || cpu read  dma0 02 sync
|  DM0W0 = DMA0 & RW' & PHI2 & MW0'     || cpu write dma0 02 sync
|  DM0W1 = DMA0 & RW' & PHI0 & MW0      || cpu write dma0 00 sync
|  DM1R  = DMA1 & RW  & PHI2            || cpu read  dma1 02 sync
|  DM1W0 = DMA1 & RW' & PHI2 & MW0'     || cpu write dma1 02 sync
|  DM1W1 = DMA1 & RW' & PHI0 & MW0      || cpu write dma1 00 sync
|  IORD  = FDCR # DM0R # DM1R           || cpu access to fdc, dma0, dma1
|  IOWE  = FDCW0 # FDCW1 # DM0W0 # DM0W1 # DM1W0 # DM1W1
|  USBR  = USB & RW  & PHI2             || cpu read  usb  02 sync
|  USBW0 = USB & RW' & PHI2 & MW0'      || cpu write usb  02 sync
|  USBW1 = USB & RW' & PHI0 & MW0       || cpu write usb  00 sync
||
|| global data bus enable for cpu access
|  BUSEN = SCX2 # SFDC # DMA0 # DMA1 # ATA0 # ATA1 # VIA # USB   
||
|| local shared dma data bus enable for cpu access
|  LBUSE = SCX2 # SFDC # DMA0 # DMA1 # ATA0 # ATA1   
||
|| output signals
|  CS0   = DMA0                         || dma0 FD80-FD8F
|  CS1   = DMA1                         || dma1 FD90-FD9F
|  CS2   = VIA                          || via  FDC0-FDCF
|  CS3   = SFDC                         || fdc  FD58-FD5F
|  CS4   = SFDC                         || fdc  FD58-FD5F (positive)
|  CS5   = USB                          || usb  FDD0-FDD1
|  RD    = USBR                         || usb read  strobe
|  WE    = USBW0 # USBW1                || usb write strobe
|  IOR   = DMAE ?? IORD                 || i/o read  strobe 3-states
|  IOW   = DMAE ?? IOWE                 || i/o write strobe 3-states
|  DBE   = BUSEN & PHI2                 || global data bus enable
|  GDD   = LBUSE                        || local  data bus enable