Subversion Repositories MB01 Project

||      FILE:   #0165.PLD
||      PROJ:   20170501
||              FD-02 FDC/ATA/DMA BOARD
||      
||      PART:   G26CV12-#0165
||
||      DEV :   GAL26CV12
||
||      DESC:   DECODER I/O
||
|
|GAL26CV12
|
|| GEN  = gate enable
|| /MGE = ram gate enable (/OE0 nor /OE 1)
|| INPUT
|  1:A1, 2:-, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2, 
| 11:CX2, 12:MGE, 13:PHI0, 14:DMA, 28:GEN,
|| OUTPUT 
|  15:CE0, 16:CE1, 17:AT0, 18:AT1, 19:CE2, 20:DBE, 22:DDE, 23:CE3,
|  24:MRD, 25:MWE, 26:IOR, 27:IOW
|
| ACTIVE-LOW: CE0, CE1, AT0, AT1, CE2, DBE, DDE, MRD, MWE, IOR, IOW
|
|
| SIGNATURE: "0165B   "
|
|| --------------------------------------------------------
|| common signals when dma disblad (DMA = 1 => cpu access)
||
|  SCX2  = CX2' & DMA                   || ram select when cpu access
|  FDD0  = IO' & A6  & A5' & A4         || select FDD0-FDDF
|  FDC   = FDD0 & A3 & DMA              || fdc  select FDD8-FDDF
|  DM0   = IO' & A6' & A5' & A4' & DMA  || dma0 select FD80-FD8F
|  DM1   = IO' & A6' & A5' & A4  & DMA  || dma1 select FD90-FD9F
|  ATA0  = IO' & A6' & A5  & A4' & DMA  || ata0 select FDA0-FDAF
|  ATA1  = IO' & A6' & A5  & A4  & DMA  || ata1 select FDB0-FDBF
||  VIA   = IO' & A6  & A5' & A4'       || via  select FDC0-FDCF (always)
||  USB   = FDD0 & A3' & A2' & A1'      || usb  select FDD0-FDD1 (always)
||
|  FDCR  = FDC & RW  & GEN & PHI2       || cpu read  fdc  02 sync
|  FDCW  = FDC & RW' & PHI2             || cpu write fdc  02 sync
|  DM0R  = DM0 & RW  & PHI2             || cpu read  dma0 02 sync
|  DM0W  = DM0 & RW' & PHI2             || cpu write dma0 00 sync
|  DM1R  = DM1 & RW  & PHI2             || cpu read  dma1 02 sync
|  DM1W  = DM1 & RW' & PHI2             || cpu write dma1 00 sync
|  IORD  = FDCR # DM0R # DM1R           || cpu read  fdc, dma0, dma1
|  IOWE  = FDCW # DM0W # DM1W           || cpu write fdc, dma0, dma1
||
|  MEMR  = SCX2 & MGE' & RW  & PHI2     || cpu read ram
|  MEMW  = SCX2 & MGE' & RW' & PHI0     || cpu write ram (00 sync)
||
|| global data bus enable for cpu access
||  DBEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 # VIA # USB
|  DBEE = SCX2 # IO'
   
||
|| local shared dma data bus enable for cpu access
|  DDEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1   
||
|| output signals
|  CE0   = DM0                          || dma0 FD80-FD8F
|  CE1   = DM1                          || dma1 FD90-FD9F
|  AT0   = ATA0                         || ata0 FDA0-FDAF
|  AT1   = ATA1                         || ata1 FDA0-FDAF
|  CE2   = FDC                          || fdc  FDD8-FDDF
|  CE3   = FDC                          || fdc  FDD8-FDDF (positive)
|  IOR   = DMA ?? IORD                  || i/o read  strobe 3-states
|  IOW   = DMA ?? IOWE                  || i/o write strobe 3-states
|  MWE   = DMA ?? MEMW                  || write ram strobe 3-states
|  MRD   = DMA ?? MEMR                  || read  ram strobe 3-states
||  DBE   = DBEE & GEN                  || global data bus enable
||  DDE   = DDEE & GEN                  || local  data bus enable
|  DBE   = DBEE                         || global data bus enable
|  DDE   = DDEE                         || local  data bus enable