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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0164.PLD)

  1  || FILE:   #0164.PLD
  2  || PROJ:   20170501
  3  ||         FD-02 FDC/ATA/DMA BOARD
  4  || 
  5  || PART:   G16V8-#0164
  6  ||
  7  || DEV :   GAL16V8
  8  ||
  9  ||         DESC:   USB/VIA DECODER
 10  ||
 11  |
 12  |GAL16V8A
 13  |
 14  || INPUT
 15  |  1:A1, 2:A2, 3:A3, 4:A4, 5:A5, 6:A6, 7:IO, 8:PHI2, 9:RW, 11:PHI0,
 16  | 12:MW0, 13:P1IN, 
 17  || OUTPUT 
 18  |  14:USB, 15:RD, 16:WE, 17:VIA, 18:GEN, 19:PHI1
 19  |
 20  | ACTIVE-LOW: USB, RD, WE, VIA
 21  |
 22  | PROPERTY:"SIMPLE"
 23  |
 24  | SIGNATURE: "0164    "
 25  |
 26  || --------------------------------------------------------
 27  ||
 28  |  PHI1 = PHI2'                            || inverted phase 2 (connect to 01IN)
 29  |  GATE = PHI0 # PHI2 # P1IN'              || gate enable strobe
 30  |  GEN  = GATE
 31  |  FDD0 = IO' & A6  & A5' & A4             || select FDD0-FDD0
 32  |  SUSB = FDD0 & A3' & A2' & A1'   || usb select FDD0-FDD1
 33  |  VIA  = IO' & A6  & A5' & A4'            || via select FDC0-FDCF
 34  |  USB  = SUSB & GATE                      || usb select FDD0-FDD1
 35  |  RD   = SUSB & RW  & PHI2
 36  |  UW0  = SUSB & RW' & PHI2 & MW0
 37  |  UW1  = SUSB & RW' & PHI0 & MW0'
 38  |  WE   = UW0 # UW1



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  4/25/17  8:07 pm  (Tuesday)
I203  Memory usage 80K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0164.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

PHI1               0   PHI2' 

GEN                8   PHI2  
                   9   PHI0  
                  10   P1IN' 

VIA               16   A4' A5' A6  IO' 

USB               40   A1' A2' A3' A4  A5' A6  IO' PHI2  
                  41   A1' A2' A3' A4  A5' A6  IO' PHI0  
                  42   A1' A2' A3' A4  A5' A6  IO' P1IN' 

RD                32   A1' A2' A3' A4  A5' A6  IO' PHI2  RW  

WE                24   A1' A2' A3' A4  A5' A6  IO' PHI2  RW' MW0  
                  25   A1' A2' A3' A4  A5' A6  IO' RW' PHI0  MW0' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A1              2        -    -    -        High    (Clock)
  2.     A2              0        -    -    -        High     
  3.     A3              4        -    -    -        High     
  4.     A4              8        -    -    -        High     
  5.     A5             12        -    -    -        High     
  6.     A6             16        -    -    -        High     
  7.     IO             20        -    -    -        High     
  8.     PHI2           24        -    -    -        High     
  9.     RW             28        -    -    -        High     
 11.     PHI0           30        -    -    -        High    (Enable)
 12.     MW0            26       56    8    0        High     
 13.     P1IN           22       48    8    0        High     
 14.     USB            19       40    8    3        Low      
 15.     RD              1       32    8    1        Low      
 16.     WE              1       24    8    2        Low      
 17.     VIA            15       16    8    1        Low      
 18.     GEN            10        8    8    3        High     
 19.     PHI1            6        0    8    1        High     
                                    ---- ----
                                      64   11  (17%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L0256 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L0288 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 *
L0320 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 *
L0512 11 11 11 11 10 11 10 11 01 11 10 11 11 11 11 11 *
L0768 10 10 10 11 01 11 10 11 01 11 10 11 01 01 10 11 *
L0800 10 10 10 11 01 11 10 11 01 11 10 11 11 10 10 01 *
L1024 10 10 10 11 01 11 10 11 01 11 10 11 01 11 01 11 *
L1280 10 10 10 11 01 11 10 11 01 11 10 11 01 11 11 11 *
L1312 10 10 10 11 01 11 10 11 01 11 10 11 11 11 11 01 *
L1344 10 10 10 11 01 11 10 11 01 11 10 10 11 11 11 11 *
L2048 11 00 00 11 00 11 00 00 00 11 00 01 00 11 01 10 *
L2080 00 11 01 00 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 11 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C31A3*

I202  4/25/17  8:07 pm  (Tuesday)
I203  Memory usage 6K
I204  Elapsed time 1 second