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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#9006.PLD)

  1  || FILE:   #9006.PLD
  2  || PROJ:   20130517        
  3  || PART:   G16V8-#9006
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   DPRAM CONTROL
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:A10, 2:A11, 3:A12, 4:CX1, 5:RW, 6:PHI2, 7:RES, 8:WP, 9:REN, 11:X,
 14  || OUTPUT 
 15  |  12:RAMN, 13:CE0, 14:CE1, 15:CE2, 16:Y, 17:VRMN, 18:RS, 19:INH
 16  |
 17  ||
 18  |  ACTIVE-LOW: CE0, CE1, CE2, RAMN, VRMN
 19  |
 20  |  PROPERTY: "SIMPLE"
 21  |
 22  |  SIGNATURE: "9006    "
 23  |
 24  || --------------------------------------------------------
 25  || RAM0, RAM1, RAM2
 26  |  RAM0 = (CX1' & A12' & A11')
 27  |  RAM1 = (CX1' & A12' & A11)
 28  |  RAM2 = (CX1' & A12  & A11' & A10')
 29  |  VRAM = (RAM0 # RAM1 # RAM2)
 30  |  CE0R = (RAM0 & RW  & PHI2)
 31  |  CE0W = (RAM0 & RW' & REN')
 32  |  CE1R = (RAM1 & RW  & PHI2)
 33  |  CE1W = (RAM1 & RW' & REN')
 34  |  CE2R = (RAM2 & RW  & PHI2)
 35  |  CE2W = (RAM2 & RW' & REN')
 36  |  CE0  = (CE0R # CE0W)
 37  |  CE1  = (CE1R # CE1W)
 38  |  CE2  = (CE2R # CE2W)
 39  |  INH  = (VRAM & RW' & REN')
 40  |  RAMN = ((VRAM & RW  & PHI2) # (VRAM & RW' & WP))
 41  |  Y = X
 42  |  VRMN = (VRAM & RW')
 43  |  RS = RES



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  5/30/13  6:53 pm  (Thursday)
I203  Memory usage 85K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#9006.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

CE0               48   A11' A12' CX1' RW' REN' 
                  49   A11' A12' CX1' RW  PHI2  

RAMN              56   A10' A11' A12  CX1' RW' WP  
                  57   A10' A11' A12  CX1' RW  PHI2  
                  58   A11' A12' CX1' RW' WP  
                  59   A11' A12' CX1' RW  PHI2  
                  60   A11  A12' CX1' RW' WP  
                  61   A11  A12' CX1' RW  PHI2  

INH                0   A10' A11' A12  CX1' RW' REN' 
                   1   A11' A12' CX1' RW' REN' 
                   2   A11  A12' CX1' RW' REN' 

CE1               40   A11  A12' CX1' RW' REN' 
                  41   A11  A12' CX1' RW  PHI2  

CE2               32   A10' A11' A12  CX1' RW' REN' 
                  33   A10' A11' A12  CX1' RW  PHI2  

Y                 24   X  

VRMN              16   A10' A11' A12  CX1' RW' 
                  17   A11' A12' CX1' RW' 
                  18   A11  A12' CX1' RW' 

RS                 8   RES  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A10             2        -    -    -        High    (Clock)
  2.     A11             0        -    -    -        High     
  3.     A12             4        -    -    -        High     
  4.     CX1             8        -    -    -        High     
  5.     RW             12        -    -    -        High     
  6.     PHI2           16        -    -    -        High     
  7.     RES            20        -    -    -        High     
  8.     WP             24        -    -    -        High     
  9.     REN            28        -    -    -        High     
 11.     X              30        -    -    -        High    (Enable)
 12.     RAMN           27       56    8    6        Low      
 13.     CE0            23       48    8    2        Low      
 14.     CE1            19       40    8    2        Low      
 15.     CE2             1       32    8    2        Low      
 16.     Y               0       24    8    1        High     
 17.     VRMN           15       16    8    3        Low      
 18.     RS             10        8    8    1        High     
 19.     INH             6        0    8    3        High     
                                    ---- ----
                                      64   20  (31%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 10 10 01 11 10 11 10 11 11 11 11 11 11 11 10 11 *
L0032 10 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
L0064 01 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
L0256 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 *
L0512 10 10 01 11 10 11 10 11 11 11 11 11 11 11 11 11 *
L0544 10 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 *
L0576 01 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 *
L0768 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 *
L1024 10 10 01 11 10 11 10 11 11 11 11 11 11 11 10 11 *
L1056 10 10 01 11 10 11 01 11 01 11 11 11 11 11 11 11 *
L1280 01 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
L1312 01 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
L1536 10 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
L1568 10 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
L1792 10 10 01 11 10 11 10 11 11 11 11 11 01 11 11 11 *
L1824 10 10 01 11 10 11 01 11 01 11 11 11 11 11 11 11 *
L1856 10 11 10 11 10 11 10 11 11 11 11 11 01 11 11 11 *
L1888 10 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
L1920 01 11 10 11 10 11 10 11 11 11 11 11 01 11 11 11 *
L1952 01 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
L2048 11 01 00 00 00 11 10 01 00 11 00 00 00 11 00 00 *
L2080 00 11 01 10 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C5399*

I202  5/30/13  6:53 pm  (Thursday)
I203  Memory usage 6K
I204  Elapsed time 1 second