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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0010.PLD)

  1  || FILE:   #0010.PLD
  2  || PROJ:   20120608        
  3  || PART:   G16V8-#0010
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   ACIA CONTROL
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:DTR, 2:RS, 3:TRM, 4:PHI2, 5:WS, 6:ACIA, 7:EN, 8:RDY, 9:SE, 11:-,
 14  || OUTPUT 
 15  |  12:G, 13:CS, 14:TA, 15:TB, 16:TXE, 17:J, 18:PHI2N, 19:K
 16  |
 17  ||
 18  |  ACTIVE-LOW: G, CS, J, PHI2N
 19  |
 20  |  PROPERTY: "SIMPLE"
 21  |
 22  |  SIGNATURE: "0010    "
 23  |
 24  || --------------------------------------------------------
 25  || ABILITA TX RS485
 26  |  TXE = (RS' & DTR')
 27  |  TA = TRM
 28  |  TB = TRM
 29  ||
 30  || --------------------------------------------------------
 31  || --------------------------------------------------------
 32  || SEGNALI COMANDO FLIP-FLOP WAIT
 33  |  PHI2N = PHI2
 34  || ABILITAZIONE WAIT
 35  |  WTX  = (ACIA' & WS')
 36  || COMANDO J,K
 37  |  DATA = (RDY # WTX')
 38  |  J    = DATA
 39  |  K    = DATA
 40  ||
 41  || --------------------------------------------------------
 42  |  ACIAA = (ACIA' & WS  & PHI2)            || NO WAIT
 43  |  ACIAB = (ACIA' & WS' & EN)              || WAIT
 44  |  CS = (ACIAA # ACIAB)
 45  ||
 46  || --------------------------------------------------------
 47  |  GX = (ACIA' & SE)
 48  |  GA = (ACIAA & SE')
 49  |  GB = (ACIAB & SE')
 50  |  G = (GX # GA # GB)



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/5/12  7:51 pm  (Thursday)
I203  Memory usage 80K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0010.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

TXE               24   DTR' RS' 

TA                40   TRM  

TB                32   TRM  

PHI2N              8   PHI2  

J                 16   WS  
                  17   ACIA  
                  18   RDY  

K                  0   WS  
                   1   ACIA  
                   2   RDY  

CS                48   PHI2  WS  ACIA' 
                  49   WS' ACIA' EN  

G                 56   PHI2  WS  ACIA' SE' 
                  57   WS' ACIA' EN  SE' 
                  58   ACIA' SE  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     DTR             2        -    -    -        High    (Clock)
  2.     RS              0        -    -    -        High     
  3.     TRM             4        -    -    -        High     
  4.     PHI2            8        -    -    -        High     
  5.     WS             12        -    -    -        High     
  6.     ACIA           16        -    -    -        High     
  7.     EN             20        -    -    -        High     
  8.     RDY            24        -    -    -        High     
  9.     SE             28        -    -    -        High     
 11.     -              30        -    -    -                (Enable)
 12.     G              27       56    8    3        Low      
 13.     CS             23       48    8    2        Low      
 14.     TA             18       40    8    1        High     
 15.     TB              0       32    8    1        High     
 16.     TXE             0       24    8    1        High     
 17.     J              15       16    8    3        Low      
 18.     PHI2N          11        8    8    1        Low      
 19.     K               6        0    8    3        High     
                                    ---- ----
                                      64   15  (23%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 *
L0032 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 *
L0064 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L0256 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 11 *
L0512 11 11 11 11 11 11 01 11 11 11 11 11 11 11 11 11 *
L0544 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 *
L0576 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 11 *
L0768 10 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1024 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1280 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1536 11 11 11 11 01 11 01 11 10 11 11 11 11 11 11 11 *
L1568 11 11 11 11 11 11 10 11 10 11 01 11 11 11 11 11 *
L1792 11 11 11 11 01 11 01 11 10 11 11 11 11 11 10 11 *
L1824 11 11 11 11 11 11 10 11 10 11 01 11 11 11 10 11 *
L1856 11 11 11 11 11 11 11 11 10 11 11 11 11 11 01 11 *
L2048 10 01 11 00 00 11 00 00 00 11 00 00 00 11 00 01 *
L2080 00 11 00 00 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C438B*

I202  7/5/12  7:51 pm  (Thursday)
I203  Memory usage 5K
I204  Elapsed time 1 second