Subversion Repositories MB01 Project

Rev

Blame | Last modification | View Log | Download | RSS feed 

OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0001.PLD)

  1  || FILE:   #0001.PLD
  2  || PROJ:   20120607        
  3  || PART:   G16V8-#0001
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   DMA CONTROL
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:DAEN, 2:HRQ, 3:EOP, 4:RES, 5:DME, 6:DMR, 7:FDR, 8:XTC, 9:-, 11:-, 
 14  || OUTPUT 
 15  |  12:OE, 13:DRS, 14:HLD, 15:XTCP, 16:FRS, 17:TC, 18:AEN, 19:AENN
 16  |
 17  | ACTIVE-LOW: OE, AENN
 18  |
 19  | PROPERTY:"SIMPLE"
 20  |
 21  | SIGNATURE: "0001    "
 22  |
 23  || --------------------------------------------------------
 24  || /OE  -> abilitazione output latch address 82C37
 25  || AEN  -> abilitazione buffer address CPU
 26  || HLD  -> abilitazione DMA 82C37
 27  || DAEN <- da 82C37 - abilitazione latch address
 28  || HRQ  <- da 82C37 - richiesta DMA
 29  || /DME <- abilitazione DMA da CPU
 30  || AENX, HRQX -> attivi solo se DME LOW
 31  |  AENX  = DAEN & DME'
 32  |  HRQX  = HRQ & DME'
 33  |  OE    = AENX
 34  |  HLD   = HRQX
 35  ||  AEN   = (AENX # HRQX)
 36  |  AEN   = (DME')
 37  |  AENN  = (AENX # HRQX)
 38  ||
 39  || DRS -> reset 82C37 (impulso positivo)
 40  || attivo o per reset hardware o per comando /DMR da CPU
 41  |  DRS   = ((RES') # (DMR)')
 42  || FRS -> reset hardware per UM8388 (impulso positivo)
 43  |  FRS   = ((RES') # (FDR)')
 44  ||
 45  || XTCP - inversione TC esterno da CPU
 46  |  XTCP  = XTC'
 47  || TC -> terminal count per UM8388
 48  |  TC    = EOP'



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  9/6/12  11:03 am  (Thursday)
I203  Memory usage 76K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0001.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

OE                56   DAEN  DME' 

AENN               0   DAEN  DME' 
                   1   HRQ  DME' 

HLD               40   HRQ  DME' 

AEN                8   DME' 

DRS               48   RES' 
                  49   DMR' 

FRS               24   RES' 
                  25   FDR' 

XTCP              32   XTC' 

TC                16   EOP' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     DAEN            2        -    -    -        High    (Clock)
  2.     HRQ             0        -    -    -        High     
  3.     EOP             4        -    -    -        High     
  4.     RES             8        -    -    -        High     
  5.     DME            12        -    -    -        High     
  6.     DMR            16        -    -    -        High     
  7.     FDR            20        -    -    -        High     
  8.     XTC            24        -    -    -        High     
  9.     -              28        -    -    -                 
 11.     -              30        -    -    -                (Enable)
 12.     OE             27       56    8    1        Low      
 13.     DRS            22       48    8    2        High     
 14.     HLD            18       40    8    1        High     
 15.     XTCP            0       32    8    1        High     
 16.     FRS             0       24    8    2        High     
 17.     TC             14       16    8    1        High     
 18.     AEN            10        8    8    1        High     
 19.     AENN            7        0    8    2        Low      
                                    ---- ----
                                      64   11  (17%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 01 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
L0032 01 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
L0256 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
L0512 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0768 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
L0800 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 *
L1024 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 *
L1280 01 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
L1536 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
L1568 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 *
L1792 11 01 11 11 11 11 10 11 11 11 11 11 11 11 11 11 *
L2048 01 11 11 10 00 11 00 00 00 11 00 00 00 11 00 00 *
L2080 00 11 00 01 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C3419*

I202  9/6/12  11:03 am  (Thursday)
I203  Memory usage 5K
I204  Elapsed time 1 second