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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0000PAL.PLD)

  1  || FILE:   #0000.PLD
  2  || PROJ:   20120607        
  3  || PART:   G26CV12-#0000
  4  ||
  5  || DEV :   PALCE26V12
  6  ||
  7  ||         DESC:   CONTROLLER DMA/FDC
  8  ||
  9  |
 10  |P26V12
 11  |
 12  || INPUT
 13  |  1:PHI2, 2:RW, 3:PHI0, 4:CX2, 5:DMA, 6:FDC, 8:WD, 9:WF, 10:MW0, 
 14  | 11:AEN, 12:OE, 13:EN, 14:RDY, 28:-,
 15  || OUTPUT 
 16  |  15:DBE, 16:CS0, 17:CS1, 18:CS2, 19:IOR, 20:IOW, 22:MRD, 23:MWE,
 17  |  24:CS3, 25:J, 26:PHI2N, 27:K
 18  |
 19  | ACTIVE-LOW: DBE, CS0, CS1, IOR, IOW, MRD, MWE, CS3, J, PHI2N 
 20  |
 21  |
 22  | SIGNATURE: "0000    "
 23  |
 24  || --------------------------------------------------------
 25  || SEGNALI COMANDO FLIP-FLOP WAIT
 26  |  PHI2N = PHI2
 27  || ABILITAZIONE WAIT
 28  |  WTX  = ((DMA' & WD') # (FDC' & WF'))
 29  || COMANDO J,K
 30  |  DATA = (RDY # WTX')
 31  |  J    = DATA
 32  |  K    = DATA
 33  ||
 34  || --------------------------------------------------------
 35  || CHIP SELECT RAM, DMA & FDC VALIDI SOLO SE AEN = 0
 36  |  DMAA = (DMA' & AEN')
 37  |  FDCA = (FDC' & AEN')
 38  |  CX2A = (CX2' & AEN')
 39  |  CS0  = DMAA
 40  |  CS1  = FDCA
 41  |  CS2  = FDCA
 42  ||
 43  || --------------------------------------------------------
 44  || SEGNALI UM8388 RD, WR (FDC)
 45  || RD, WR SINCRONIZZATI CON PHI2 (WF = 1)
 46  |  UMR1 = (FDCA & WF  & RW  & PHI2)
 47  |  UMW1 = (FDCA & WF  & RW' & PHI2)
 48  || RD, WR SINCRONIZZATI CON EN (WF = 0)
 49  |  UMR2 = (FDCA & WF' & RW  & EN)
 50  |  UMW2 = (FDCA & WF' & RW' & EN)
 51  |  UMRD   = (UMR1 # UMR2)
 52  |  UMWE   = (UMW1 # UMW2)
 53  ||
 54  || --------------------------------------------------------
 55  || SEGNALI 82C37 RD, WR (DMA)


 56  || RD, WR SINCRONIZZATI CON PHI2 (WD = 1)
 57  |  DMR1 = (DMAA & WD  & RW  & PHI2)
 58  |  DMW1 = (DMAA & WD  & RW' & PHI2)
 59  || RD, WR SINCRONIZZATI CON EN (WD = 0)
 60  |  DMR2 = (DMAA & WD' & RW  & EN)
 61  |  DMW2 = (DMAA & WD' & RW' & EN)
 62  |  DMRD   = (DMR1 # DMR2)
 63  |  DMWE   = (DMW1 # DMW2)
 64  ||
 65  || --------------------------------------------------------
 66  || SEGNALI RD,WR,MRD,MWR 3 STATI PER DMA
 67  || XAE attiva uscita 3-stati se LOW
 68  |  IORD = (DMRD # UMRD)
 69  |  IOWR = (DMWE # UMWE)
 70  |  MEMRD = (CX2' & RW  & PHI2 & OE)
 71  |  MEMWRA = (CX2' & RW' & PHI2 & MW0  & OE)
 72  |  MEMWRB = (CX2' & RW' & PHI0 & MW0' & OE)
 73  |  MEMWR = (MEMWRA # MEMWRB)
 74  |  IOR = AEN' ?? IORD
 75  |  IOW = AEN' ?? IOWR
 76  |  MRD = AEN' ?? MEMRD
 77  |  MWE = AEN' ?? MEMWR
 78  || --------------------------------------------------------
 79  || SELEZIONE SHARED RAM
 80  || DMA ATTIVO - RAM SEMPRE SELEZIONATA
 81  |  CEA = (OE')
 82  || DMA INATTIVO
 83  |  CEB = (CX2' & OE & PHI2)
 84  |  CS3 = (CEA # CEB)
 85  ||
 86  || --------------------------------------------------------
 87  || ABILITAZIONE BUFFER DATI BUS DMA
 88  |  FDCZ1 = (FDCA & WF & PHI2)
 89  |  FDCZ2 = (FDCA & WF' & EN)
 90  |  DMAZ1 = (DMAA & WD & PHI2)
 91  |  DMAZ2 = (DMAA & WD' & EN)
 92  |  DBE = (FDCZ1 # FDCZ2 # DMAZ1 # DMAZ2 # (CX2A & PHI2))



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  6/4/13  5:08 pm  (Tuesday)
I203  Memory usage 106K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0000PAL.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

PHI2N             11   PHI2  

J                 20   DMA  FDC  
                  21   DMA  WF  
                  22   FDC  WD  
                  23   WD  WF  
                  24   RDY  

K                  2   DMA  FDC  
                   3   DMA  WF  
                   4   FDC  WD  
                   5   WD  WF  
                   6   RDY  

CS0              132   DMA' AEN' 

CS1              121   FDC' AEN' 

CS2              108   FDC' AEN' 

IOR               92   AEN' 
                  93   PHI2  RW  DMA' WD  AEN' 
                  94   PHI2  RW  FDC' WF  AEN' 
                  95   RW  DMA' WD' AEN' EN  
                  96   RW  FDC' WF' AEN' EN  

IOW               75   AEN' 
                  76   PHI2  RW' DMA' WD  AEN' 
                  77   PHI2  RW' FDC' WF  AEN' 
                  78   RW' DMA' WD' AEN' EN  
                  79   RW' FDC' WF' AEN' EN  

MRD               58   AEN' 
                  59   PHI2  RW  CX2' OE  

MWE               43   AEN' 
                  44   PHI2  RW' CX2' MW0  OE  
                  45   RW' PHI0  CX2' MW0' OE  

CS3               31   PHI2  CX2' OE  
                  32   OE' 

DBE              141   PHI2  DMA' WD  AEN' 
                 142   PHI2  FDC' WF  AEN' 
                 143   DMA' WD' AEN' EN  
                 144   FDC' WF' AEN' EN  
                 145   PHI2  CX2' AEN' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     PHI2            0        -    -    -        High    (Clock)
  2.     RW              4        -    -    -        High     
  3.     PHI0            8        -    -    -        High     
  4.     CX2            12        -    -    -        High    (Clock)
  5.     DMA            16        -    -    -        High     
  6.     FDC            20        -    -    -        High     
  8.     WD             24        -    -    -        High     
  9.     WF             28        -    -    -        High     
 10.     MW0            32        -    -    -        High     
 11.     AEN            36        -    -    -        High     
 12.     OE             40        -    -    -        High     
 13.     EN             44        -    -    -        High     
 14.     RDY            48        -    -    -        High     
 15.     DBE            51      140    9    5        Low     (Registered)
 16.     CS0            47      131    9    1        Low     (Registered)
 17.     CS1            43      120   11    1        Low     (Registered)
 18.     CS2            38      107   13    1        High    (Registered)
 19.     IOR            35       92   15    5        Low     (Registered)
 20.     IOW            31       75   17    5        Low     (Registered)
 22.     MRD            27       58   17    2        Low     (Registered)
 23.     MWE            23       43   15    3        Low     (Registered)
 24.     CS3            19       30   13    2        Low     (Registered)
 25.     J              15       19   11    5        Low     (Registered)
 26.     PHI2N          11       10    9    1        Low     (Registered)
 27.     K               6        1    9    5        High    (Registered)
 28.     -               2        -    -    -                 
 29.     -               -        0    1    0                 
 30.     -               -      149    1    0                 
                                    ---- ----
                                     150   36  (24%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       PAL26V12
*
QP28* QF7848* QV1024*
F0*
L0052 1111111111111111111111111111111111111111111111111111*
L0104 1111111111111111011101111111111111111111111111111111*
L0156 1111111111111111011111111111011111111111111111111111*
L0208 1111111111111111111101110111111111111111111111111111*
L0260 1111111111111111111111110111011111111111111111111111*
L0312 1111111111111111111111111111111111111111111111110111*
L0520 1111111111111111111111111111111111111111111111111111*
L0572 0111111111111111111111111111111111111111111111111111*
L0988 1111111111111111111111111111111111111111111111111111*
L1040 1111111111111111011101111111111111111111111111111111*
L1092 1111111111111111011111111111011111111111111111111111*
L1144 1111111111111111111101110111111111111111111111111111*
L1196 1111111111111111111111110111011111111111111111111111*
L1248 1111111111111111111111111111111111111111111111110111*
L1560 1111111111111111111111111111111111111111111111111111*
L1612 0111111111111011111111111111111111111111011111111111*
L1664 1111111111111111111111111111111111111111101111111111*
L2236 1111111111111111111111111111111111111011111111111111*
L2288 0111101111111011111111111111111101111111011111111111*
L2340 1111101101111011111111111111111110111111011111111111*
L3016 1111111111111111111111111111111111111011111111111111*
L3068 0111011111111011111111111111111111111111011111111111*
L3900 1111111111111111111111111111111111111011111111111111*
L3952 0111101111111111101111110111111111111011111111111111*
L4004 0111101111111111111110111111011111111011111111111111*
L4056 1111101111111111101111111011111111111011111101111111*
L4108 1111101111111111111110111111101111111011111101111111*
L4784 1111111111111111111111111111111111111011111111111111*
L4836 0111011111111111101111110111111111111011111111111111*
L4888 0111011111111111111110111111011111111011111111111111*
L4940 1111011111111111101111111011111111111011111101111111*
L4992 1111011111111111111110111111101111111011111101111111*
L5564 1111111111111111111111111111111111111111111111111111*
L5616 1111111111111111111110111111111111111011111111111111*
L6240 1111111111111111111111111111111111111111111111111111*
L6292 1111111111111111111110111111111111111011111111111111*
L6812 1111111111111111111111111111111111111111111111111111*
L6864 1111111111111111101111111111111111111011111111111111*
L7280 1111111111111111111111111111111111111111111111111111*
L7332 0111111111111111101111110111111111111011111111111111*
L7384 0111111111111111111110111111011111111011111111111111*
L7436 1111111111111111101111111011111111111011111101111111*
L7488 1111111111111111111110111111101111111011111101111111*
L7540 0111111111111011111111111111111111111011111111111111*
L7800 100000001000111111111111111111111111111111111111*
C1C44*

I202  6/4/13  5:08 pm  (Tuesday)
I203  Memory usage 9K
I204  Elapsed time 1 second