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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0056.PLD)

  1  || FILE:   #0056.PLD
  2  || PROJ:   20120401        
  3  || PART:   G26CV12-#0056
  4  ||
  5  || DEV :   GAL26CV12
  6  ||
  7  ||         DESC:   DECODER SCHEDE RAM 4Mb
  8  ||
  9  |
 10  |GAL26CV12
 11  |
 12  || INPUT
 13  |  1:A19, 2:A20, 3:A21, 4:A22, 5:A23, 6:PHI0, 8:RW, 9:ME, 10:PHI2, 
 14  | 11:FE, 12:S0, 13:S1, 14:MW0, 28:LST,
 15  || OUTPUT 
 16  |  15:CS0, 16:CS1, 17:CS2, 18:CS3, 19:RD, 20:WR, 22:G, 
 17  |  23:CS4, 24:CS5, 25:CS6, 26:CS7, 27:CSF
 18  |
 19  | ACTIVE-LOW: CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7, RD, WR, G, CSF
 20  |
 21  |
 22  | SIGNATURE: "0056    "
 23  |
 24  ||
 25  || --------------------------------------------------------
 26  || S0, S1 -> SELEZIONE BLOCCO
 27  || /MW0   -> QUALIFICA WRITE CON PHI0
 28  || /FE    -> ABILITA FLASH F00000 - F7FFFF (512K)
 29  || /ME    -> ABILITA RAM
 30  || LST    -> ABILITA SLOT (CSF) PER FLASH
 31  || --------------------------------------------------------
 32  ||
 33  || BLOCCHI SELEZIONE RAM 4MB
 34  || BLK0 -> 000000 - 3FFFFF (S0 = 0, S1 = 0)
 35  |  BLK0 = (A23' & A22' & S1' & S0' & ME' & FE)
 36  || BLK1 -> 400000 - 7FFFFF (S0 = 1, S1 = 0)
 37  |  BLK1 = (A23' & A22  & S1' & S0  & ME' & FE)
 38  || BLK2 -> 800000 - BFFFFF (S0 = 0, S1 = 1)
 39  |  BLK2 = (A23  & A22' & S1  & S0' & ME' & FE)
 40  || BLK3 -> C00000 - FFFFFF (S0 = 1, S1 = 1)
 41  |  BLK3 = (A23  & A22  & S1  & S0  & ME' & FE)
 42  || BK3F -> C00000 - FFFFFF (S0 = 1, S1 = 1) FLASH (FE=0, LST=1)
 43  |  BK3F = (A23  & A22  & S1  & S0  & ME  & FE' & LST)
 44  |  SLF  = (BK3F & A21  & A20  & A19')
 45  || --------------------------------------------------------
 46  ||
 47  || SELEZIONE RAM
 48  |  SLM  = (BLK0 # BLK1 # BLK2 # BLK3)
 49  |  SEL  = (SLF # SLM)
 50  |  CS0  = (SLM & A21' & A20' & A19' & PHI2)
 51  |  CS1  = (SLM & A21' & A20' & A19  & PHI2)
 52  |  CS2  = (SLM & A21' & A20  & A19' & PHI2)
 53  |  CS3  = (SLM & A21' & A20  & A19  & PHI2)
 54  |  CS4  = (SLM & A21  & A20' & A19' & PHI2)
 55  |  CS5  = (SLM & A21  & A20' & A19  & PHI2)


 56  |  CS6  = (SLM & A21  & A20  & A19' & PHI2)
 57  |  CS7  = (SLM & A21  & A20  & A19  & PHI2)
 58  |  G    = SEL
 59  |  CSF  = (SLF & PHI2)
 60  |  RD   = (SEL & PHI2 & RW)
 61  |  WRA  = (SEL & PHI2 & RW' & MW0)
 62  |  WRB  = (SEL & PHI0 & RW' & MW0')
 63  |  WR   = (WRA # WRB) 



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  8/13/12  12:23 pm  (Monday)
I203  Memory usage 108K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0056.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

CS0              113   A19' A20' A21' A22' A23' ME' PHI2  FE  S0' S1' 
                 114   A19' A20' A21' A22' A23  ME' PHI2  FE  S0' S1  
                 115   A19' A20' A21' A22  A23' ME' PHI2  FE  S0  S1' 
                 116   A19' A20' A21' A22  A23  ME' PHI2  FE  S0  S1  

CS1              104   A19  A20' A21' A22' A23' ME' PHI2  FE  S0' S1' 
                 105   A19  A20' A21' A22' A23  ME' PHI2  FE  S0' S1  
                 106   A19  A20' A21' A22  A23' ME' PHI2  FE  S0  S1' 
                 107   A19  A20' A21' A22  A23  ME' PHI2  FE  S0  S1  

CS2               95   A19' A20  A21' A22' A23' ME' PHI2  FE  S0' S1' 
                  96   A19' A20  A21' A22' A23  ME' PHI2  FE  S0' S1  
                  97   A19' A20  A21' A22  A23' ME' PHI2  FE  S0  S1' 
                  98   A19' A20  A21' A22  A23  ME' PHI2  FE  S0  S1  

CS3               86   A19  A20  A21' A22' A23' ME' PHI2  FE  S0' S1' 
                  87   A19  A20  A21' A22' A23  ME' PHI2  FE  S0' S1  
                  88   A19  A20  A21' A22  A23' ME' PHI2  FE  S0  S1' 
                  89   A19  A20  A21' A22  A23  ME' PHI2  FE  S0  S1  

CS4               38   A19' A20' A21  A22' A23' ME' PHI2  FE  S0' S1' 
                  39   A19' A20' A21  A22' A23  ME' PHI2  FE  S0' S1  
                  40   A19' A20' A21  A22  A23' ME' PHI2  FE  S0  S1' 
                  41   A19' A20' A21  A22  A23  ME' PHI2  FE  S0  S1  

CS5               29   A19  A20' A21  A22' A23' ME' PHI2  FE  S0' S1' 
                  30   A19  A20' A21  A22' A23  ME' PHI2  FE  S0' S1  
                  31   A19  A20' A21  A22  A23' ME' PHI2  FE  S0  S1' 
                  32   A19  A20' A21  A22  A23  ME' PHI2  FE  S0  S1  

CS6               20   A19' A20  A21  A22' A23' ME' PHI2  FE  S0' S1' 
                  21   A19' A20  A21  A22' A23  ME' PHI2  FE  S0' S1  
                  22   A19' A20  A21  A22  A23' ME' PHI2  FE  S0  S1' 
                  23   A19' A20  A21  A22  A23  ME' PHI2  FE  S0  S1  

CS7               11   A19  A20  A21  A22' A23' ME' PHI2  FE  S0' S1' 
                  12   A19  A20  A21  A22' A23  ME' PHI2  FE  S0' S1  
                  13   A19  A20  A21  A22  A23' ME' PHI2  FE  S0  S1' 
                  14   A19  A20  A21  A22  A23  ME' PHI2  FE  S0  S1  

G                 49   A19' A20  A21  A22  A23  ME  FE' S0  S1  LST  
                  50   A22' A23' ME' FE  S0' S1' 
                  51   A22' A23  ME' FE  S0' S1  
                  52   A22  A23' ME' FE  S0  S1' 
                  53   A22  A23  ME' FE  S0  S1  

CSF                2   A19' A20  A21  A22  A23  ME  PHI2  FE' S0  S1  LST  

RD                75   A19' A20  A21  A22  A23  RW  ME  PHI2  FE' S0  S1  LST  
                  76   A22' A23' RW  ME' PHI2  FE  S0' S1' 
                  77   A22' A23  RW  ME' PHI2  FE  S0' S1  
                  78   A22  A23' RW  ME' PHI2  FE  S0  S1' 
                  79   A22  A23  RW  ME' PHI2  FE  S0  S1  


WR                62   A19' A20  A21  A22  A23  PHI0  RW' ME  FE' S0  S1  MW0' 
                       LST  
                  63   A19' A20  A21  A22  A23  RW' ME  PHI2  FE' S0  S1  MW0  
                       LST  
                  64   A22' A23' PHI0  RW' ME' FE  S0' S1' MW0' 
                  65   A22' A23' RW' ME' PHI2  FE  S0' S1' MW0  
                  66   A22' A23  PHI0  RW' ME' FE  S0' S1  MW0' 
                  67   A22' A23  RW' ME' PHI2  FE  S0' S1  MW0  
                  68   A22  A23' PHI0  RW' ME' FE  S0  S1' MW0' 
                  69   A22  A23' RW' ME' PHI2  FE  S0  S1' MW0  
                  70   A22  A23  PHI0  RW' ME' FE  S0  S1  MW0' 
                  71   A22  A23  RW' ME' PHI2  FE  S0  S1  MW0  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A19             0        -    -    -        High    (Clock)
  2.     A20             4        -    -    -        High     
  3.     A21             8        -    -    -        High     
  4.     A22            12        -    -    -        High     
  5.     A23            16        -    -    -        High     
  6.     PHI0           20        -    -    -        High     
  8.     RW             24        -    -    -        High     
  9.     ME             28        -    -    -        High     
 10.     PHI2           32        -    -    -        High     
 11.     FE             36        -    -    -        High     
 12.     S0             40        -    -    -        High     
 13.     S1             44        -    -    -        High     
 14.     MW0            48        -    -    -        High     
 15.     CS0            51      112    9    4        Low     (Three-state)
 16.     CS1            47      103    9    4        Low     (Three-state)
 17.     CS2            43       94    9    4        Low     (Three-state)
 18.     CS3            39       85    9    4        Low     (Three-state)
 19.     RD             35       74   11    5        Low     (Three-state)
 20.     WR             31       61   13   10        Low     (Three-state)
 22.     G              27       48   13    5        Low     (Three-state)
 23.     CS4            23       37   11    4        Low     (Three-state)
 24.     CS5            19       28    9    4        Low     (Three-state)
 25.     CS6            15       19    9    4        Low     (Three-state)
 26.     CS7            11       10    9    4        Low     (Three-state)
 27.     CSF             7        1    9    1        Low     (Three-state)
 28.     LST             2        -    -    -        High     
 29.     -               -        0    1    0                 
 30.     -               -      121    1    0                 
                                    ---- ----
                                     122   53  (43%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL26CV12
*
QP28* QF6432* QV1024*
F0*
L0052 1111111111111111111111111111111111111111111111111111*
L0104 1001011101110111011111111111011101111011011101111111*
L0520 1111111111111111111111111111111111111111111111111111*
L0572 0111011101111011101111111111101101110111101110111111*
L0624 0111011101111011011111111111101101110111101101111111*
L0676 0111011101110111101111111111101101110111011110111111*
L0728 0111011101110111011111111111101101110111011101111111*
L0988 1111111111111111111111111111111111111111111111111111*
L1040 1011011101111011101111111111101101110111101110111111*
L1092 1011011101111011011111111111101101110111101101111111*
L1144 1011011101110111101111111111101101110111011110111111*
L1196 1011011101110111011111111111101101110111011101111111*
L1456 1111111111111111111111111111111111111111111111111111*
L1508 0111101101111011101111111111101101110111101110111111*
L1560 0111101101111011011111111111101101110111101101111111*
L1612 0111101101110111101111111111101101110111011110111111*
L1664 0111101101110111011111111111101101110111011101111111*
L1924 1111111111111111111111111111111111111111111111111111*
L1976 1011101101111011101111111111101101110111101110111111*
L2028 1011101101111011011111111111101101110111101101111111*
L2080 1011101101110111101111111111101101110111011110111111*
L2132 1011101101110111011111111111101101110111011101111111*
L2496 1111111111111111111111111111111111111111111111111111*
L2548 1001011101110111011111111111011111111011011101111111*
L2600 1111111111111011101111111111101111110111101110111111*
L2652 1111111111111011011111111111101111110111101101111111*
L2704 1111111111110111101111111111101111110111011110111111*
L2756 1111111111110111011111111111101111110111011101111111*
L3172 1111111111111111111111111111111111111111111111111111*
L3224 1001011101110111011101111011011111111011011101111011*
L3276 1001011101110111011111111011011101111011011101110111*
L3328 1111111111111011101101111011101111110111101110111011*
L3380 1111111111111011101111111011101101110111101110110111*
L3432 1111111111111011011101111011101111110111101101111011*
L3484 1111111111111011011111111011101101110111101101110111*
L3536 1111111111110111101101111011101111110111011110111011*
L3588 1111111111110111101111111011101101110111011110110111*
L3640 1111111111110111011101111011101111110111011101111011*
L3692 1111111111110111011111111011101101110111011101110111*
L3848 1111111111111111111111111111111111111111111111111111*
L3900 1001011101110111011111110111011101111011011101111111*
L3952 1111111111111011101111110111101101110111101110111111*
L4004 1111111111111011011111110111101101110111101101111111*
L4056 1111111111110111101111110111101101110111011110111111*
L4108 1111111111110111011111110111101101110111011101111111*
L4420 1111111111111111111111111111111111111111111111111111*
L4472 0111011110111011101111111111101101110111101110111111*
L4524 0111011110111011011111111111101101110111101101111111*
L4576 0111011110110111101111111111101101110111011110111111*
L4628 0111011110110111011111111111101101110111011101111111*
L4888 1111111111111111111111111111111111111111111111111111*
L4940 1011011110111011101111111111101101110111101110111111*

L4992 1011011110111011011111111111101101110111101101111111*
L5044 1011011110110111101111111111101101110111011110111111*
L5096 1011011110110111011111111111101101110111011101111111*
L5356 1111111111111111111111111111111111111111111111111111*
L5408 0111101110111011101111111111101101110111101110111111*
L5460 0111101110111011011111111111101101110111101101111111*
L5512 0111101110110111101111111111101101110111011110111111*
L5564 0111101110110111011111111111101101110111011101111111*
L5824 1111111111111111111111111111111111111111111111111111*
L5876 1011101110111011101111111111101101110111101110111111*
L5928 1011101110111011011111111111101101110111101101111111*
L5980 1011101110110111101111111111101101110111011110111111*
L6032 1011101110110111011111111111101101110111011101111111*
L6344 0101010101010101010101010011000000110000001101010011*
L6396 011000100000001000000010000000100000*
C8FBB*

I202  8/13/12  12:23 pm  (Monday)
I203  Memory usage 16K
I204  Elapsed time 1 second