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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0002.PLD)

  1  || FILE:   #0002.PLD
  2  || PROJ:   20120602        
  3  || PART:   G22V10-#0002
  4  ||
  5  || DEV :   GAL22V10
  6  ||
  7  ||         DESC:   DECODER BANK/CONTROL REGISTER
  8  ||
  9  |
 10  |GAL22V10
 11  |
 12  || INPUT
 13  |  1:CLK, 2:F2, 3:A0, 4:A1, 5:A2, 6:A3, 7:A4, 8:A5, 9:A6, 10:IOS,
 14  |  11:RW, 13:PHI2,
 15  || OUTPUT 
 16  |  14:Q0, 15:Q1, 16:Q2, 17:PHI0, 18:WPR, 19:WAP, 20:WDL, 
 17  |  21:WDH, 22:CRW, 23:CRD
 18  |
 19  | ACTIVE-LOW: CRD, CRW
 20  |
 21  | SIGNATURE: "0002    "
 22  |
 23  ||
 24  || Q0 = 8M, Q1 = 4M, Q2 = 2M  
 25  |  Q[2..0] = CLK // Q[2..0] + 1 
 26  |  FA = Q2 & F2'   || 2MHz
 27  |  FB = Q1 & F2            || 4MHz
 28  |  PHI0 = (FA # FB)        || FASE 0
 29  ||
 30  || PBR => FF00 - FF0F
 31  |  WPR = (IOS' & RW' & PHI2 & A6' & A5' & A4') 
 32  || APR => FF10 - FF1F
 33  |  WAP = (IOS' & RW' & PHI2 & A6' & A5' & A4) 
 34  || DML => FF20 - FF27
 35  |  WDL = (IOS' & RW' & PHI2 & A6' & A5  & A4' & A3') 
 36  || DMH => FF28 - FF2F
 37  |  WDH = (IOS' & RW' & PHI2 & A6' & A5  & A4' & A3) 
 38  || CR  => FF30 - FF3F
 39  |  CRW = (IOS' & RW' & PHI2 & A6' & A5  & A4 & PHI0) 
 40  ||
 41  | FF00 = (IOS' & A6' & A5' & A4' & A3' & A2' & A1' & A0')
 42  | FF10 = (IOS' & A6' & A5' & A4  & A3' & A2' & A1' & A0')
 43  | FF20 = (IOS' & A6' & A5  & A4' & A3' & A2' & A1' & A0')
 44  | FF28 = (IOS' & A6' & A5  & A4' & A3  & A2' & A1' & A0')
 45  | FF30 = (IOS' & A6' & A5  & A4)
 46  | CRD  = ((FF00 # FF10 # FF20 # FF28 # FF30) & RW & PHI2)
 47   



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/5/12  7:24 pm  (Thursday)
I203  Memory usage 92K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0002.PLA)




RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

Q2                99   Q0  Q1  Q2' 
                 100   Q0' Q2  
                 101   Q1' Q2  

Q1               112   Q0' Q1  
                 113   Q0  Q1' 

Q0               123   Q0' 

PHI0              84   F2' Q2  
                  85   F2  Q1  

WPR               67   A4' A5' A6' IOS' RW' PHI2  

WAP               50   A4  A5' A6' IOS' RW' PHI2  

WDL               35   A3' A4' A5  A6' IOS' RW' PHI2  

WDH               22   A3  A4' A5  A6' IOS' RW' PHI2  

CRW               11   A4  A5  A6' IOS' RW' PHI2  PHI0  

CRD                2   A0' A1' A2' A3' A4' A5' A6' IOS' RW  PHI2  
                   3   A0' A1' A2' A3' A4' A5  A6' IOS' RW  PHI2  
                   4   A0' A1' A2' A3' A4  A5' A6' IOS' RW  PHI2  
                   5   A0' A1' A2' A3  A4' A5  A6' IOS' RW  PHI2  
                   6   A4  A5  A6' IOS' RW  PHI2  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     CLK             0        -    -    -        High    (Clock)
  2.     F2              4        -    -    -        High     
  3.     A0              8        -    -    -        High     
  4.     A1             12        -    -    -        High     
  5.     A2             16        -    -    -        High     
  6.     A3             20        -    -    -        High     
  7.     A4             24        -    -    -        High     
  8.     A5             28        -    -    -        High     
  9.     A6             32        -    -    -        High     
 10.     IOS            36        -    -    -        High     
 11.     RW             40        -    -    -        High     
 13.     PHI2           42        -    -    -        High     
 14.     Q0             39      122    9    1        High    (Registered)
 15.     Q1             35      111   11    2        High    (Registered)
 16.     Q2             31       98   13    3        High    (Registered)
 17.     PHI0           26       83   15    2        High    (Three-state)
 18.     WPR            22       66   17    1        High    (Three-state)
 19.     WAP            18       49   17    1        High    (Three-state)
 20.     WDL            14       34   15    1        High    (Three-state)
 21.     WDH            10       21   13    1        High    (Three-state)
 22.     CRW             7       10   11    1        Low     (Three-state)
 23.     CRD             3        1    9    5        Low     (Three-state)
 25.     -               -        0    1    0                 
 26.     -               -      131    1    0                 
                                    ---- ----
                                     132   18  (14%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       PAL22V10
*
QP24* QF5828* QV1024*
F0*
L0044 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0088 11 11 11 11 10 11 10 11 10 11 10 11 10 11 10 11 10 11 10 11 01 01 *
L0132 11 11 11 11 10 11 10 11 10 11 10 11 10 11 01 11 10 11 10 11 01 01 *
L0176 11 11 11 11 10 11 10 11 10 11 10 11 01 11 10 11 10 11 10 11 01 01 *
L0220 11 11 11 11 10 11 10 11 10 11 01 11 10 11 01 11 10 11 10 11 01 01 *
L0264 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 10 11 10 11 01 01 *
L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0484 11 11 11 11 11 11 11 11 11 11 11 11 01 01 01 11 10 11 10 11 10 01 *
L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0968 11 11 11 11 11 11 11 11 11 11 01 11 10 11 01 11 10 11 10 11 10 01 *
L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1540 11 11 11 11 11 11 11 11 11 11 10 11 10 11 01 11 10 11 10 11 10 01 *
L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2200 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 10 11 10 11 10 01 *
L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2948 11 11 11 11 11 11 11 11 11 11 11 11 10 11 10 11 10 11 10 11 10 01 *
L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L3696 11 11 10 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 *
L3740 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 *
L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4356 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 10 11 11 *
L4400 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 11 11 01 11 11 *
L4444 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 11 11 11 *
L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L4928 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 11 *
L4972 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 10 11 11 *
L5368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L5412 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 *
L5808 01 01 11 11 11 11 11 10 10 10 *
C92CF*

I202  7/5/12  7:24 pm  (Thursday)
I203  Memory usage 8K
I204  Elapsed time 1 second