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||      FILE:   #0050.PLD
||      PROJ:   20120601        
||      PART:   G22V10-#0050
||
||      DEV :   GAL22V10
||
||      DESC:   MASTER CLOCK
||
|
|GAL22V10
|
|| INPUT
|  1:CLK, 2:PD, 3:F2, 4:S0, 5:VPA, 6:VDA, 7:RES, 8:P2IN, 9:P1IN, 10:P0IN,
|  11:P4IN, 13:RDY,
|| OUTPUT 
|  14:P2O, 15:Q0, 16:Q1, 17:Q2, 18:VMA, 19:ALE, 20:GOE, 
|  21:PHI1, 22:PHI0, 23:P4O
|
| ACTIVE-LOW: VMA
|
| SIGNATURE: "0050    "
|
|| P2O -> CLOCK 02 CPU
|| CONNETTERE P0IN CON PHI0
|| CONNETTERE P1IN CON PHI1
|| CONNETTERE P4IN CON P4O
||
|| Q0 = 8M, Q1 = 4M, Q2 = 2M  
|  Q[2..0] = CLK // Q[2..0] + 1 
|  A = Q2 & F2'         || 2MHz
|  B = Q1 & F2          || 4MHz
|  PHI0 = (A # B)       || FASE 0
|  P4O = P0IN           || FASE 0 RITARDATA
|| P0IN -> FASE 0 RITARDO T  (PD = 1)
|| P4IN -> FASE 0 RITARDO 2T (PD = 0)
|  P2O = ((P0IN & PD) # (P4IN & PD'))
|  PHI1 = P2IN'         || FASE 1 RITARDATA RISPETTO A PHI2
|  VMA  = ((VDA & RES) # (VPA & RES))
|  ALE    = (RDY & P0IN' & P2IN')
|  DBEA   = (RDY & P2IN' & S0)
|  DBEB   = (RDY & P1IN  & S0')
|  GOE    = (DBEA # DBEB)