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OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0161.PLD)
1 || FILE: #0161.PLD
2 || PROJ: 20120600
3 || PART: G16V8-#0161
4 ||
5 || DEV : GAL16V8
6 ||
7 || DESC: INTERFACCIA SCART/VGA
8 ||
9 |
10 |GAL16V8A
11 |
12 || INPUT
13 | 1:RIN, 2:GIN, 3:BIN, 4:IIN, 5:-, 6:VSI, 7:HSI, 8:VP, 9:HP, 11:VDE,
14 || OUTPUT
15 | 12:R, 13:G, 14:B, 15:I, 16:CSY, 17:CSYN, 18:HSY, 19:VSY
16 |
17 | ACTIVE-LOW: CSYN
18 |
19 | PROPERTY: "SIMPLE"
20 |
21 | SIGNATURE: "0161 "
22 |
23 | R = (RIN & VDE')
24 | G = (GIN & VDE')
25 | B = (BIN & VDE')
26 | I = (IIN & VDE')
27 | CSY = (VSI ## HSI)
28 | CSYN = (VSI ## HSI)
29 | VSY = (VSI ## VP')
30 | HSY = (HSI ## HP')
I200 No fatal errors found in source code (logic phase).
I201 No warnings.
I202 7/5/12 2:56 pm (Thursday)
I203 Memory usage 75K
I204 Elapsed time 1 second
OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0161.PLA)
I289 Simple GAL architecture selected.
RESOLVED EXPRESSIONS (Reduction 0)
Signal name Row Terms
R 56 RIN VDE'
G 48 GIN VDE'
B 40 BIN VDE'
I 32 IIN VDE'
CSY 24 VSI' HSI
25 VSI HSI'
CSYN 16 VSI' HSI
17 VSI HSI'
VSY 0 VSI' VP'
1 VSI VP
HSY 8 HSI' HP'
9 HSI HP
SIGNAL ASSIGNMENT
Rows
Pin Signal name Column -------------- Activity
Beg Avail Used
1. RIN 2 - - - High (Clock)
2. GIN 0 - - - High
3. BIN 4 - - - High
4. IIN 8 - - - High
5. - 12 - - -
6. VSI 16 - - - High
7. HSI 20 - - - High
8. VP 24 - - - High
9. HP 28 - - - High
11. VDE 30 - - - High (Enable)
12. R 26 56 8 1 High
13. G 22 48 8 1 High
14. B 18 40 8 1 High
15. I 0 32 8 1 High
16. CSY 0 24 8 2 High
17. CSYN 15 16 8 2 Low
18. HSY 10 8 8 2 High
19. VSY 6 0 8 2 High
---- ----
64 12 (19%)
I200 No fatal errors found in source code (device phase).
I201 No warnings.
OrCAD DEVICE
Type: GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 11 11 11 11 10 11 11 11 10 11 11 11 *
L0032 11 11 11 11 11 11 11 11 01 11 11 11 01 11 11 11 *
L0256 11 11 11 11 11 11 11 11 11 11 10 11 11 11 10 11 *
L0288 11 11 11 11 11 11 11 11 11 11 01 11 11 11 01 11 *
L0512 11 11 11 11 11 11 11 11 10 11 01 11 11 11 11 11 *
L0544 11 11 11 11 11 11 11 11 01 11 10 11 11 11 11 11 *
L0768 11 11 11 11 11 11 11 11 10 11 01 11 11 11 11 11 *
L0800 11 11 11 11 11 11 11 11 01 11 10 11 11 11 11 11 *
L1024 11 11 11 11 01 11 11 11 11 11 11 11 11 11 11 10 *
L1280 11 11 01 11 11 11 11 11 11 11 11 11 11 11 11 10 *
L1536 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 10 *
L1792 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 10 *
L2048 11 01 11 11 00 11 00 00 00 11 00 01 00 11 01 10 *
L2080 00 11 00 01 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C3782*
I202 7/5/12 2:56 pm (Thursday)
I203 Memory usage 5K
I204 Elapsed time 1 second