Subversion Repositories MB01 Project

||      FILE:   #0160.PLD
||      PROJ:   20120600        
||      PART:   G16V8-#0160
||
||      DEV :   GAL16V8
||
||      DESC:   VDC CONTROL
||
|
|GAL16V8A
|
|| INPUT
|  1:VDC, 2:PHI2, 3:RW, 4:PHI0, 5:-, 6:WV, 7:EN2, 8:S0, 9:F16, 11:S16, 
|  12:F20, 13:S1, 14:SX, 
|| OUTPUT 
|  15:CS0, 16:CS1, 17:DCLK, 18:M16, 19:M20
|
| ACTIVE-LOW: CS0 
|
| PROPERTY:"SIMPLE"
|
| SIGNATURE: "0160    "
|
|| --------------------------------------------------------
|| SELEZIONE DCLK PER MOS8563 (S16=0 ->16MHz, S16=1->20MHz)
|  DCLK = ((S16 & F20) # (S16' & F16))
|  M16 = ((F20 & S1) # (F16 & S1'))
|  M20 = ((F16 & S1) # (F20 & S1')) 
|| --------------------------------------------------------
|| ABILITAZIONE MOS8563
|  VDCA = VDC'
|| --------------------------------------------------------
|| ABILITAZIONE MOS8563 (VDC, WAIT -> WV)
|| CICLO READ 
||  VR1  = (VDCA & WV  & RW  & PHI2)
||  VR2  = (VDCA & WV' & RW  & EN2)
||  VR1  = (VDCA & WV  & RW)
||  VR2  = (VDCA & WV' & RW)
||  VR1  = (VDCA & WV  & RW  & PHI2 & S1)
|  VR1  = (VDCA & WV  & RW  & PHI2)
|  VR2  = (VDCA & WV' & RW  & EN2)
||  VR3  = (VDCA & WV  & RW  & PHI0 & S1')

|| CICLO WRITE SINCRONIZZATO CON PHI2 (S0 = 1)
|  VW1  = (VDCA & WV  & RW' & PHI2 & S0)
|  VW2  = (VDCA & WV' & RW' & EN2)
|| CICLO WRITE SINCRONIZZATO CON PHI0 (S0 = 0)
||  VW3  = (VDCA & WV  & RW' & PHI0 & S0')
||  VW4  = (VDCA & WV' & RW' & EN0  & S0')
|  VW3  = (VDCA & WV  & RW' & PHI0 & S0')
||  VW4  = (VDCA & WV' & RW' & EN2  & S0')
||
|| ABILITAZIONE VDC
||  VDCB = (VR1 # VR2 # VR3 # VW1 # VW2 # VW3)
|  VDCB = (VR1 # VR2 # VW1 # VW2 # VW3)
|| S1 = 1 -> /CS0 QUALIFICATO CON PHI2,EN
||            CS1 = 1       SE SX = 1
||            CS1 = VDCA    SE SX = 0 
|  CS1A = (VDCA & SX')
|  CS1X = (SX)
|  CS0  = (VDCB)
|  CS1  = (CS1A # CS1X)