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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0160.PLD)

  1  || FILE:   #0160.PLD
  2  || PROJ:   20120600        
  3  || PART:   G16V8-#0160
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   VDC CONTROL
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:VDC, 2:PHI2, 3:RW, 4:PHI0, 5:-, 6:WV, 7:EN2, 8:S0, 9:F16, 11:S16, 
 14  |  12:F20, 13:S1, 14:SX, 
 15  || OUTPUT 
 16  |  15:CS0, 16:CS1, 17:DCLK, 18:M16, 19:M20
 17  |
 18  | ACTIVE-LOW: CS0 
 19  |
 20  | PROPERTY:"SIMPLE"
 21  |
 22  | SIGNATURE: "0160    "
 23  |
 24  || --------------------------------------------------------
 25  || SELEZIONE DCLK PER MOS8563 (S16=0 ->16MHz, S16=1->20MHz)
 26  |  DCLK = ((S16 & F20) # (S16' & F16))
 27  |  M16 = ((F20 & S1) # (F16 & S1'))
 28  |  M20 = ((F16 & S1) # (F20 & S1')) 
 29  || --------------------------------------------------------
 30  || ABILITAZIONE MOS8563
 31  |  VDCA = VDC'
 32  || --------------------------------------------------------
 33  || ABILITAZIONE MOS8563 (VDC, WAIT -> WV)
 34  || CICLO READ 
 35  ||  VR1  = (VDCA & WV  & RW  & PHI2)
 36  ||  VR2  = (VDCA & WV' & RW  & EN2)
 37  ||  VR1  = (VDCA & WV  & RW)
 38  ||  VR2  = (VDCA & WV' & RW)
 39  ||  VR1  = (VDCA & WV  & RW  & PHI2 & S1)
 40  |  VR1  = (VDCA & WV  & RW  & PHI2)
 41  |  VR2  = (VDCA & WV' & RW  & EN2)
 42  ||  VR3  = (VDCA & WV  & RW  & PHI0 & S1')
 43  
 44  || CICLO WRITE SINCRONIZZATO CON PHI2 (S0 = 1)
 45  |  VW1  = (VDCA & WV  & RW' & PHI2 & S0)
 46  |  VW2  = (VDCA & WV' & RW' & EN2)
 47  || CICLO WRITE SINCRONIZZATO CON PHI0 (S0 = 0)
 48  ||  VW3  = (VDCA & WV  & RW' & PHI0 & S0')
 49  ||  VW4  = (VDCA & WV' & RW' & EN0  & S0')
 50  |  VW3  = (VDCA & WV  & RW' & PHI0 & S0')
 51  ||  VW4  = (VDCA & WV' & RW' & EN2  & S0')
 52  ||
 53  || ABILITAZIONE VDC
 54  ||  VDCB = (VR1 # VR2 # VR3 # VW1 # VW2 # VW3)
 55  |  VDCB = (VR1 # VR2 # VW1 # VW2 # VW3)


 56  || S1 = 1 -> /CS0 QUALIFICATO CON PHI2,EN
 57  ||            CS1 = 1       SE SX = 1
 58  ||            CS1 = VDCA    SE SX = 0 
 59  |  CS1A = (VDCA & SX')
 60  |  CS1X = (SX)
 61  |  CS0  = (VDCB)
 62  |  CS1  = (CS1A # CS1X)



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  9/6/12  11:18 am  (Thursday)
I203  Memory usage 83K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0160.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

DCLK              16   F16  S16' 
                  17   S16  F20  

M16                8   F16  S1' 
                   9   F20  S1  

M20                0   F16  S1  
                   1   F20  S1' 

CS0               32   VDC' PHI2  RW' WV  S0  
                  33   VDC' RW' PHI0  WV  S0' 
                  34   VDC' PHI2  RW  WV  
                  35   VDC' RW' WV' EN2  
                  36   VDC' RW  WV' EN2  

CS1               24   VDC' SX' 
                  25   SX  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     VDC             2        -    -    -        High    (Clock)
  2.     PHI2            0        -    -    -        High     
  3.     RW              4        -    -    -        High     
  4.     PHI0            8        -    -    -        High     
  5.     -              12        -    -    -                 
  6.     WV             16        -    -    -        High     
  7.     EN2            20        -    -    -        High     
  8.     S0             24        -    -    -        High     
  9.     F16            28        -    -    -        High     
 11.     S16            30        -    -    -        High    (Enable)
 12.     F20            26       56    8    0        High     
 13.     S1             22       48    8    0        High     
 14.     SX             18       40    8    0        High     
 15.     CS0             1       32    8    5        Low      
 16.     CS1             0       24    8    2        High     
 17.     DCLK           14       16    8    2        High     
 18.     M16            10        8    8    2        High     
 19.     M20             6        0    8    2        High     
                                    ---- ----
                                      64   13  (20%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 11 11 11 11 11 11 11 01 11 11 01 11 *
L0032 11 11 11 11 11 11 11 11 11 11 11 10 11 01 11 11 *
L0256 11 11 11 11 11 11 11 11 11 11 11 10 11 11 01 11 *
L0288 11 11 11 11 11 11 11 11 11 11 11 01 11 01 11 11 *
L0512 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 10 *
L0544 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 01 *
L0768 11 10 11 11 11 11 11 11 11 10 11 11 11 11 11 11 *
L0800 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 *
L1024 01 10 10 11 11 11 11 11 01 11 11 11 01 11 11 11 *
L1056 11 10 10 11 01 11 11 11 01 11 11 11 10 11 11 11 *
L1088 01 10 01 11 11 11 11 11 01 11 11 11 11 11 11 11 *
L1120 11 10 10 11 11 11 11 11 10 11 01 11 11 11 11 11 *
L1152 11 10 01 11 11 11 11 11 10 11 01 11 11 11 11 11 *
L2048 11 11 01 11 00 11 00 00 00 11 00 01 00 11 01 10 *
L2080 00 11 00 00 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 01 11 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C3B4F*

I202  9/6/12  11:18 am  (Thursday)
I203  Memory usage 6K
I204  Elapsed time 1 second