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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0155B.PLD)

  1  || FILE:   #0155.PLD
  2  || PROJ:   20120600        
  3  || PART:   G16V8-#0155
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   DECODER ATA 0/1
  8  ||
  9  |
 10  |GAL16V8
 11  |
 12  || INPUT
 13  |  1:A0, 2:A1, 3:A2, 4:A3, 5:RW, 6:PHI2, 7:ATA, 8:EN, 9:WA, 11:PHI0,
 14  || OUTPUT 
 15  |  12:HWO, 13:HWC, 14:GA, 15:IOR, 16:IOW, 17:CS0, 18:CS1, 19:HRD
 16  |
 17  | ACTIVE-LOW: HWC, HWO, HRD, CS0, CS1, GA, IOR, IOW
 18  |
 19  | PROPERTY:"SIMPLE"
 20  |
 21  | SIGNATURE: "0155    "
 22  |
 23  || --------------------------------------------------------
 24  || INDIRIZZO I/O ATA
 25  |  IOA = (ATA')
 26  || --------------------------------------------------------
 27  || ATAA => XXX0 - XXX7
 28  |  ATAA = (IOA & A3')
 29  || ATAB => XXXE - XXXF
 30  |  ATAB = (IOA & A3 & A2 & A1)
 31  || REGISTRO HIGH DATA ATA => XXXC
 32  |  HDA0 = (IOA & A3 & A2 & A1' & A0')
 33  || REGISTRO DATI 16 BIT ATA => XXX0
 34  |  RDR0 = (ATAA & A2' & A1' & A0') 
 35  || --------------------------------------------------------
 36  || CONTROLLO ATA
 37  || CS0 => XXX0 - XXX7
 38  |  CS0 =  ((ATAA & PHI2 & WA) # (ATAA & EN & WA'))
 39  || CS1 => XXXE - XXXF
 40  |  CS1 = ((ATAB & PHI2 & WA) # (ATAB & EN & WA'))
 41  |  ATAX = (ATAA # ATAB)
 42  |  GA  = ATAX
 43  || --------------------------------------------------------
 44  || SEGNALI ATA IOR, IOW
 45  || IOR, IOW SINCRONIZZATI CON PHI2 (WA = 1)
 46  |  RD1 = (ATAX & WA  & RW  & PHI2)
 47  |  WR1 = (ATAX & WA  & RW' & PHI0)
 48  || IOR, IOW SINCRONIZZATI CON EN (WA = 0)
 49  |  RD2 = (ATAX & WA' & RW  & EN)
 50  |  WR2 = (ATAX & WA' & RW' & EN)
 51  |  IOR = (RD1 # RD2)
 52  |  IOW = (WR1 # WR2)
 53  || --------------------------------------------------------
 54  || CONTROLLO REGISTRO HIGH ATA
 55  || HWC => WRITE XXXC (comando clock)


 56  |  HWC = (HDA0 & RW' & PHI0)
 57  || HRD => READ  XXXC
 58  |  HRD = (HDA0 & RW)
 59  || HWO => WRITE REG. ATA XXX0 (8 bit alti)
 60  |  HWO = (RDR0 & RW')



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  6/10/13  6:04 pm  (Monday)
I203  Memory usage 87K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0155B.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

CS0               16   A3' PHI2  ATA' WA  
                  17   A3' ATA' EN  WA' 

CS1                8   A1  A2  A3  PHI2  ATA' WA  
                   9   A1  A2  A3  ATA' EN  WA' 

GA                40   A1  A2  A3  ATA' 
                  41   A3' ATA' 

IOR               32   A1  A2  A3  RW  PHI2  ATA' WA  
                  33   A1  A2  A3  RW  ATA' EN  WA' 
                  34   A3' RW  PHI2  ATA' WA  
                  35   A3' RW  ATA' EN  WA' 

IOW               24   A1  A2  A3  RW' ATA' EN  WA' 
                  25   A1  A2  A3  RW' ATA' WA  PHI0  
                  26   A3' RW' ATA' EN  WA' 
                  27   A3' RW' ATA' WA  PHI0  

HWC               48   A0' A1' A2  A3  RW' ATA' PHI0  

HRD                0   A0' A1' A2  A3  RW  ATA' 

HWO               56   A0' A1' A2' A3' RW' ATA' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A0              2        -    -    -        High    (Clock)
  2.     A1              0        -    -    -        High     
  3.     A2              4        -    -    -        High     
  4.     A3              8        -    -    -        High     
  5.     RW             12        -    -    -        High     
  6.     PHI2           16        -    -    -        High     
  7.     ATA            20        -    -    -        High     
  8.     EN             24        -    -    -        High     
  9.     WA             28        -    -    -        High     
 11.     PHI0           30        -    -    -        High    (Enable)
 12.     HWO            27       56    8    1        Low      
 13.     HWC            23       48    8    1        Low      
 14.     GA             19       40    8    2        Low      
 15.     IOR             1       32    8    4        Low      
 16.     IOW             1       24    8    4        Low      
 17.     CS0            15       16    8    2        Low      
 18.     CS1            11        8    8    2        Low      
 19.     HRD             7        0    8    1        Low      
                                    ---- ----
                                      64   17  (27%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 10 10 01 11 01 11 01 11 11 11 10 11 11 11 11 11 *
L0256 01 11 01 11 01 11 11 11 01 11 10 11 11 11 01 11 *
L0288 01 11 01 11 01 11 11 11 11 11 10 11 01 11 10 11 *
L0512 11 11 11 11 10 11 11 11 01 11 10 11 11 11 01 11 *
L0544 11 11 11 11 10 11 11 11 11 11 10 11 01 11 10 11 *
L0768 01 11 01 11 01 11 10 11 11 11 10 11 01 11 10 11 *
L0800 01 11 01 11 01 11 10 11 11 11 10 11 11 11 01 01 *
L0832 11 11 11 11 10 11 10 11 11 11 10 11 01 11 10 11 *
L0864 11 11 11 11 10 11 10 11 11 11 10 11 11 11 01 01 *
L1024 01 11 01 11 01 11 01 11 01 11 10 11 11 11 01 11 *
L1056 01 11 01 11 01 11 01 11 11 11 10 11 01 11 10 11 *
L1088 11 11 11 11 10 11 01 11 01 11 10 11 11 11 01 11 *
L1120 11 11 11 11 10 11 01 11 11 11 10 11 01 11 10 11 *
L1280 01 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L1312 11 11 11 11 10 11 11 11 11 11 10 11 11 11 11 11 *
L1536 10 10 01 11 01 11 10 11 11 11 10 11 11 11 11 01 *
L1792 10 10 10 11 10 11 10 11 11 11 10 11 11 11 11 11 *
L2048 00 00 00 00 00 11 00 00 00 11 00 01 00 11 01 01 *
L2080 00 11 01 01 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C47AD*

I202  6/10/13  6:04 pm  (Monday)
I203  Memory usage 7K
I204  Elapsed time 1 second