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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0154.PLD)

  1  || FILE:   #0154.PLD
  2  || PROJ:   20120600        
  3  || PART:   G16V8-#0154
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   DECODER RTC - CTC
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:A0, 2:A1, 3:A2, 4:A3, 5:RW, 6:PHI2, 7:IOX, 8:EN, 9:WT, 11:-,
 14  || OUTPUT 
 15  |  12:CS0, 13:ALE, 14:RRD, 15:RWE, 16:CS1, 17:IOR, 18:IOW, 19:CS2
 16  |
 17  ||
 18  |  ACTIVE-LOW: CS0, RRD, RWE, CS1, IOR, IOW, CS2
 19  |
 20  |  PROPERTY: "SIMPLE"
 21  |
 22  |  SIGNATURE: "0154    "
 23  |
 24  || RTC -> FE4C - FE4D
 25  |  RTC = (IOX' & A3 & A2  & A1')
 26  || RTC ADDRESS REG => FE4C
 27  |  RAR = (RTC & A0')
 28  || RTC DATA REG => FE4D
 29  |  RDR = (RTC & A0)
 30  || RTC READ DATA REG.  => FE4D
 31  |  RRD = (RDR & RW  & PHI2)
 32  || RTC WRITE DATA REG. => FE4D
 33  |  RWE = (RDR & RW' & PHI2)
 34  || RTC WRITE ADDRESS REG => FE4C
 35  |  ALE = (RAR & RW' & PHI2)
 36  |  CS0  = (RDR & PHI2)
 37  || CTC -> FE48 - FE4B
 38  |  CTC = (IOX' & A3 & A2')
 39  |  CS1 = CTC
 40  |  RD1 = (CTC & RW  & WT  & PHI2)  || NO WAIT
 41  |  RD2 = (CTC & RW  & WT' & EN)            || WAIT
 42  |  WR1 = (CTC & RW' & WT  & PHI2)  || NO WAIT
 43  |  WR2 = (CTC & RW' & WT' & EN)            || WAIT
 44  |  IOR = (RD1 # RD2)
 45  |  IOW = (WR1 # WR2)
 46  ||
 47  |  CS2 = PHI2



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/24/12  7:55 pm  (Tuesday)
I203  Memory usage 83K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0154.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

RRD               40   A0  A1' A2  A3  RW  PHI2  IOX' 

RWE               32   A0  A1' A2  A3  RW' PHI2  IOX' 

ALE               48   A0' A1' A2  A3  RW' PHI2  IOX' 

CS0               56   A0  A1' A2  A3  PHI2  IOX' 

CS1               24   A2' A3  IOX' 

IOR               16   A2' A3  RW  PHI2  IOX' WT  
                  17   A2' A3  RW  IOX' EN  WT' 

IOW                8   A2' A3  RW' PHI2  IOX' WT  
                   9   A2' A3  RW' IOX' EN  WT' 

CS2                0   PHI2  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A0              2        -    -    -        High    (Clock)
  2.     A1              0        -    -    -        High     
  3.     A2              4        -    -    -        High     
  4.     A3              8        -    -    -        High     
  5.     RW             12        -    -    -        High     
  6.     PHI2           16        -    -    -        High     
  7.     IOX            20        -    -    -        High     
  8.     EN             24        -    -    -        High     
  9.     WT             28        -    -    -        High     
 11.     -              30        -    -    -                (Enable)
 12.     CS0            27       56    8    1        Low      
 13.     ALE            22       48    8    1        High     
 14.     RRD            19       40    8    1        Low      
 15.     RWE             1       32    8    1        Low      
 16.     CS1             1       24    8    1        Low      
 17.     IOR            15       16    8    2        Low      
 18.     IOW            11        8    8    2        Low      
 19.     CS2             7        0    8    1        Low      
                                    ---- ----
                                      64   10  (16%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 11 11 11 11 01 11 11 11 11 11 11 11 *
L0256 11 11 10 11 01 11 10 11 01 11 10 11 11 11 01 11 *
L0288 11 11 10 11 01 11 10 11 11 11 10 11 01 11 10 11 *
L0512 11 11 10 11 01 11 01 11 01 11 10 11 11 11 01 11 *
L0544 11 11 10 11 01 11 01 11 11 11 10 11 01 11 10 11 *
L0768 11 11 10 11 01 11 11 11 11 11 10 11 11 11 11 11 *
L1024 10 01 01 11 01 11 10 11 01 11 10 11 11 11 11 11 *
L1280 10 01 01 11 01 11 01 11 01 11 10 11 11 11 11 11 *
L1536 10 10 01 11 01 11 10 11 01 11 10 11 11 11 11 11 *
L1792 10 01 01 11 01 11 11 11 01 11 10 11 11 11 11 11 *
L2048 00 00 00 10 00 11 00 00 00 11 00 01 00 11 01 01 *
L2080 00 11 01 00 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C2E53*

I202  7/24/12  7:55 pm  (Tuesday)
I203  Memory usage 6K
I204  Elapsed time 1 second