Subversion Repositories MB01 Project

OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0152.PLD)

  1  || FILE:   #0152.PLD
  2  || PROJ:   20120600        
  3  || PART:   G16V8-#0152
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   RDY CPU CONTROL
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:WAIT, 2:PHI2, 3:RDY0, 4:RDY1, 5:RDY2, 6:RDY3, 7:RDY4, 8:RDY5, 9:RDY6,
 14  |  11:RDY7, 12:RDY8N, 13:RDY9, 14:RDY10,
 15  || OUTPUT 
 16  |  15:BRDY, 16:P2, 17:J, 18:PHI2N, 19:K
 17  |
 18  ||
 19  |  ACTIVE-LOW: J, PHI2N
 20  |
 21  |  PROPERTY: "SIMPLE"
 22  |
 23  |  SIGNATURE: "0152    "
 24  |
 25  |  RDYA   = (RDY0 & RDY1 & RDY2 & RDY3 & RDY4)
 26  |  RDYB   = (RDY5 & RDY6 & RDY7 & RDY8N' & RDY9 & RDY10)
 27  |  BRDY   = (RDYA & RDYB)
 28  |  P2 = PHI2
 29  || --------------------------------------------------------
 30  || SEGNALI COMANDO FLIP-FLOP WAIT
 31  |  PHI2N = PHI2
 32  || COMANDO J,K
 33  |  DATA = (RDY8N # WAIT)
 34  |  J    = DATA
 35  |  K    = DATA



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/24/12  11:17 am  (Tuesday)
I203  Memory usage 76K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0152.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

BRDY              32   RDY0  RDY1  RDY2  RDY3  RDY4  RDY5  RDY6  RDY7  RDY8N' 
                       RDY9  RDY10  

P2                24   PHI2  

PHI2N              8   PHI2  

J                 16   WAIT  
                  17   RDY8N  

K                  0   WAIT  
                   1   RDY8N  




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     WAIT            2        -    -    -        High    (Clock)
  2.     PHI2            0        -    -    -        High     
  3.     RDY0            4        -    -    -        High     
  4.     RDY1            8        -    -    -        High     
  5.     RDY2           12        -    -    -        High     
  6.     RDY3           16        -    -    -        High     
  7.     RDY4           20        -    -    -        High     
  8.     RDY5           24        -    -    -        High     
  9.     RDY6           28        -    -    -        High     
 11.     RDY7           30        -    -    -        High    (Enable)
 12.     RDY8N          26       56    8    0        High     
 13.     RDY9           22       48    8    0        High     
 14.     RDY10          18       40    8    0        High     
 15.     BRDY            0       32    8    1        High     
 16.     P2              0       24    8    1        High     
 17.     J              15       16    8    2        Low      
 18.     PHI2N          11        8    8    1        Low      
 19.     K               6        0    8    2        High     
                                    ---- ----
                                      64    7  (11%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0032 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 *
L0256 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0512 11 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L0544 11 11 11 11 11 11 11 11 11 11 11 11 11 01 11 11 *
L0768 01 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L1024 11 11 01 11 01 11 01 11 01 01 01 01 01 10 01 01 *
L2048 10 01 11 11 00 11 00 00 00 11 00 01 00 11 01 01 *
L2080 00 11 00 10 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 01 11 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C2675*

I202  7/24/12  11:17 am  (Tuesday)
I203  Memory usage 5K
I204  Elapsed time 1 second