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OrCAD LOGIC COMPILER  v2.01 N 12/09/94  (Source file .\PLD\#0150.PLD)

  1  || FILE:   #0150.PLD
  2  || PROJ:   20120600        
  3  || PART:   G16V8-#0150
  4  ||
  5  || DEV :   GAL16V8
  6  ||
  7  ||         DESC:   DECODER I/O
  8  ||
  9  |
 10  |GAL16V8A
 11  |
 12  || INPUT
 13  |  1:A0, 2:A1, 3:A2, 4:A3, 5:A4, 6:A5, 7:A6, 8:A7,  
 14  |  9:IO1, 11:RW, 12:PHI2,
 15  || OUTPUT 
 16  |  13:DBE, 14:RDV, 15:LCD, 16:KFR, 17:V0, 18:V1, 19:S0
 17  |
 18  | ACTIVE-LOW: DBE, RDV, LCD, KFR, V0, V1, S0
 19  |
 20  |  PROPERTY: "SIMPLE"
 21  |
 22  | SIGNATURE: "0150    "
 23  |
 24  || --------------------------------------------------------
 25  || LCD -> FE38 - FE3B
 26  |  LCD = (IO1' & A7' & A6' & A5  & A4 & A3 & A2')
 27  ||
 28  || --------------------------------------------------------
 29  || RDV -> FE47 READ ONLY
 30  |  RDV = (IO1' & A7' & A6  & A5' & A4' & A3' & A2 & A1 & A0 & RW & PHI2)
 31  ||
 32  || --------------------------------------------------------
 33  || KFR -> FE40 - FE46
 34  |  KF0 = (IO1' & A7' & A6  & A5' & A4' & A3' & A2')
 35  |  KF1 = (IO1' & A7' & A6  & A5' & A4' & A3' & A2 & A1')
 36  |  KF2 = (IO1' & A7' & A6  & A5' & A4' & A3' & A2 & A1 & A0')
 37  |  KFR = (KF0 # KF1 # KF2)
 38  ||
 39  || --------------------------------------------------------
 40  || V0 -> FE00 - FE0F
 41  |  V0 = (IO1' & A7' & A6' & A5' & A4')
 42  || V1 -> FE10 - FE1F
 43  |  V1 = (IO1' & A7' & A6' & A5' & A4)
 44  || S0 -> FE50 - FE57 (ACIA)
 45  |  S0 = (IO1' & A7' & A6  & A5' & A4  & A3')
 46  ||
 47  || --------------------------------------------------------
 48  || DBE -> DATA BUS ENABLE -> FE00 - FE4F
 49  |  GA = (IO1' & A7' & A6' & A5')
 50  |  GB = (IO1' & A7' & A6' & A5)
 51  |  GC = (IO1' & A7' & A6  & A5' & A4')
 52  |  DBE = (GA # GB # GC)



I200  No fatal errors found in source code (logic phase).
I201  No warnings.


I202  7/24/12  11:17 am  (Tuesday)
I203  Memory usage 88K
I204  Elapsed time 1 second

OrCAD DEVICE FITTER  v2.01   12/09/94  (Source file .\PLD\#0150.PLA)

I289  Simple GAL architecture selected.



RESOLVED EXPRESSIONS (Reduction 0)

Signal name      Row   Terms

LCD               32   A2' A3  A4  A5  A6' A7' IO1' 

RDV               40   A0  A1  A2  A3' A4' A5' A6  A7' IO1' RW  PHI2  

KFR               24   A0' A1  A2  A3' A4' A5' A6  A7' IO1' 
                  25   A1' A2  A3' A4' A5' A6  A7' IO1' 
                  26   A2' A3' A4' A5' A6  A7' IO1' 

V0                16   A4' A5' A6' A7' IO1' 

V1                 8   A4  A5' A6' A7' IO1' 

S0                 0   A3' A4  A5' A6  A7' IO1' 

DBE               48   A4' A5' A6  A7' IO1' 
                  49   A5' A6' A7' IO1' 
                  50   A5  A6' A7' IO1' 




SIGNAL ASSIGNMENT
                                      Rows
 Pin    Signal name   Column     --------------    Activity
                                 Beg Avail Used

  1.     A0              2        -    -    -        High    (Clock)
  2.     A1              0        -    -    -        High     
  3.     A2              4        -    -    -        High     
  4.     A3              8        -    -    -        High     
  5.     A4             12        -    -    -        High     
  6.     A5             16        -    -    -        High     
  7.     A6             20        -    -    -        High     
  8.     A7             24        -    -    -        High     
  9.     IO1            28        -    -    -        High     
 11.     RW             30        -    -    -        High    (Enable)
 12.     PHI2           26       56    8    0        High     
 13.     DBE            23       48    8    3        Low      
 14.     RDV            19       40    8    1        Low      
 15.     LCD             1       32    8    1        Low      
 16.     KFR             1       24    8    3        Low      
 17.     V0             15       16    8    1        Low      
 18.     V1             11        8    8    1        Low      
 19.     S0              7        0    8    1        Low      
                                    ---- ----
                                      64   11  (17%)


I200  No fatal errors found in source code (device phase).
I201  No warnings.



OrCAD DEVICE
Type:       GAL16V8
*
QP20* QF2194* QV1024*
F0*
L0000 11 11 11 11 10 11 01 11 10 11 01 11 10 11 10 11 *
L0256 11 11 11 11 11 11 01 11 10 11 10 11 10 11 10 11 *
L0512 11 11 11 11 11 11 10 11 10 11 10 11 10 11 10 11 *
L0768 01 10 01 11 10 11 10 11 10 11 01 11 10 11 10 11 *
L0800 10 11 01 11 10 11 10 11 10 11 01 11 10 11 10 11 *
L0832 11 11 10 11 10 11 10 11 10 11 01 11 10 11 10 11 *
L1024 11 11 10 11 01 11 01 11 01 11 10 11 10 11 10 11 *
L1280 01 01 01 11 10 11 10 11 10 11 01 11 10 01 10 01 *
L1536 11 11 11 11 11 11 10 11 10 11 01 11 10 11 10 11 *
L1568 11 11 11 11 11 11 11 11 10 11 10 11 10 11 10 11 *
L1600 11 11 11 11 11 11 11 11 01 11 10 11 10 11 10 11 *
L2048 00 00 00 01 00 11 00 00 00 11 00 01 00 11 01 01 *
L2080 00 11 00 00 00 10 00 00 00 10 00 00 00 10 00 00 *
L2112 00 10 00 00 00 00 00 01 11 11 11 11 11 11 11 11 *
L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
L2176 11 11 11 11 11 11 11 11 10 *
C31E4*

I202  7/24/12  11:17 am  (Tuesday)
I203  Memory usage 6K
I204  Elapsed time 1 second