WebSVN – MB01 Project – Blame – /trunk/sources/lst/F8/start.lst

Rev	Author	Line No.	Line
1	-	1	Tue Jul 17 11:11:08 2018 Page 1
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		8
		9	2500 A.D. 65816 Macro Assembler #26960 - Version 5.02g
		10	-----------------------------------------------------
		11
		12	Input Filename : src\F8\start.asm
		13	Output Filename : obj\F8\start.obj
		14	Listing Has Been Relocated
		15
		16
		17	2596 .LIST on
		18	2597
		19	2598 F8FE00 .INCLUDE inc\dirp00.inc
		20	2599 ;----------------------------------------------------------
		21	2600 ; DIRP00.ASM
		22	2601 ; PROGETTO: B1601
		23	2602 ;
		24	2603 ; Variabili in Direct Page $00
		25	2604 ;----------------------------------------------------------
		26	2605
		27	2606 ; sezione COMMON -- questo permette di includere il file in piu' file
		28	2607
		29	2608 .LIST on
		30	2609
		31	2610 DIRP00: .SECTION page0, ref_only, common ;Direct-Page 00
		32	2611
		33	2612 000000 .ABSOLUTE ;; inizia sempre da $00
		34	2613 000000 .ORG 0x00
		35	2614 000000
		36	2615 000000 0000 JiffyClk .DW ; contatore 10ms 32 bit
		37	2616 000002 0000 .DW
		38	2617 000004 SysTmr .DS SYSTMRCNT ; system timer 0 (10ms)
		39	2618 000008 SysTMF .DS SYSTMRCNT ; flag timer (80 -> start)
		40	2619 00000C 00 Bnk0Flag .DB ; <7>: flag test RAM banco 0 ok
		41	2620 ; <6>: flag warm reset
		42	2621 00000D 00 RTCFlag .DB
		43	2622
		44	2623 00000E diskstat .DS 2 ; flag device on ata bus #0 & #1
		45	2624 ; <7>: device ready
		46	2625 ; <6>: compact flash device (C.F.)
		47	2626 ; <5>: device identification ok
		48	2627 ; <4>: MBR loaded
		49	2628 ; <3>: valid signature in MBR
		50	2629 ; <2>: first partition found&active
		51	2630 ; <1>:
		52	2631 ; <0>: valid partition flag
		53	2632
		54	2633 ; <7>: device ready
		55	2634 ; <6>: USB device
		56	2635 ; <5>: compact flash device (C.F.)
		57	2636 ; <4>: device identification ok
		58	2637 ; <3>: MBR loaded
		59	2638 ; <2>: first partition found&active
		60	2639 ; <1>: always 1
		61	2640 ; <0>: valid partition flag
		62	2641 000010
		63	Tue Jul 17 11:11:08 2018 Page 2
		64
		65
		66
		67
		68	2642
		69	2643 00000E atadev .EQU diskstat
		70	2644
		71	2645 000010 usbdev .DS 2 ; flag flash disk on usb bus #0
		72	2646 ; <7>: device plugged and ready
		73	2647 ; <6>: always 1
		74	2648 ; <5>: device identification ok
		75	2649 ; <4>: MBR loaded
		76	2650 ; <3>: valid signature in MBR
		77	2651 ; <2>: first partition found&active
		78	2652 ; <1>:
		79	2653 ; <0>: valid partition flag
		80	2654
		81	2655 000012 diskmax .DS 16 ; disk max. sector's
		82	2656 000012 atasec .EQU diskmax
		83	2657 00001A usbsec .EQU diskmax+8
		84	2658
		85	2659
		86	2660 000022 atambr .DS 8 ; data for first partition found in mbr
		87	2661 ; first 3 bytes for start sector of partition
		88	2662 ; last byte for partition type
		89	2663 00002A usbmbr .DS 8
		90	2664
		91	2665 000032 ataprt .DS 8 ; total sec's of first partition
		92	2666 00003A usbprt .DS 8 ; total sec's of first partition
		93	2667
		94	2668
		95	2669 000042 00 usb0ch .DB ; usb0 (ch375/ch376) flag
		96	2670 ; <7>: module on
		97	2671 ; <6>: ch376 flag
		98	2672 ; <5:0>: chip version
		99	2673
		100	2674 000043 00 usb0st .DB ; usb0 status
		101	2675 ; <7>: usb0 host mode ok
		102	2676 ; <6>: flash disk attached flag
		103	2677 ; <5>: usb device attached
		104	2678
		105	2679 000044 00 fdcdrv .DB ; phisycal drive status (drive #0)
		106	2680 ; <7>: disk format established in bit 0&1
		107	2681 ; <6>: double step seek done
		108	2682 ; <5>: trust format bit's (set after ok r/w)
		109	2683 ; <4>: write protect bit (if disk in drive)
		110	2684 ; <3>: don't care
		111	2685 ; <2>: don't care
		112	2686 ; <1>: HD disk if set else DD disk
		113	2687 ; <0>: CBM format if set else IBM format
		114	2688
		115	2689 000045 00 vdrive .DB ; virtual drive status (ram disk, drive #1)
		116	2690 ; <7>: disk format established in bit 0&1
		117	2691 ; <6>: change disk simulation (after format)
		118	2692 ; <5>: don't care
		119	2693 ; <4>: write protect bit (under sw control)
		120	2694 ; <3>: don't care
		121	2695 ; <2>: don't care
		122	2696 ; <1>: HD disk if set else DD disk
		123	2697 ; <0>: CBM format if set else IBM format
		124	2698
		125	Tue Jul 17 11:11:08 2018 Page 3
		126
		127
		128
		129
		130	2699 000046 00 fdcctl .DB ; fdc controller status
		131	2700 ; <7>: drive is attached
		132	2701 ; <6>: drive need recalibration (restore)
		133	2702 ; <5>: FDC controller ok
		134	2703 ; <4>: motor on
		135	2704 ; <3>: dma is active
		136	2705 ; <2>: dma chip ok (post routine)
		137	2706 ; <1>: clock rate (1=HD,0=DD)
		138	2707 ; <0>: disk ready
		139	2708
		140	2709 000047 00 fdctrk .DB ; fd: current seek track
		141	2710 000048 00 fdcerr .DB ; fd: last error code
		142	2711 000049 00 ataerr .DB ; ata: last error code
		143	2712 00004A 00 ataxer .DB ; ata: last extended error code
		144	2713
		145	2714 00004B 00 CtrlBrk .DB ; flag CTRL+BREAK (NMI)
		146	2715
		147	2716 00004C 0000 MemTop .DW ; top memoria RAM
		148	2717 00004E 00 .DB ; banco top mem
		149	2718
		150	2719 00004F 00 DflTxtIn .DB ; device di default text input
		151	2720 000050 00 DflTxtOut .DB ; device di default text output
		152	2721
		153	2722 000051 COPPtr LP ; long pointer for COP decoding
		154	2723 000054 00 COPIdx .DB ; COP signature/index
		155	2724
		156	2725 000055 00 BiosEnt .DB ; flag accesso a bios setup
		157	2726
		158	2727 ; variabili utilizzate da ACIA
		159	2728 000056 spwrk .DS $30
		160	2729
		161	2730 ; bios mem
		162	2731 000086 0000 nsize .DW ; dimensione blocco da allocare
		163	2732 ;bsize .DW ; dimensione vera blocco free
		164	2733 000088 0000 splitsz .DW ; dimensione blocco splittato
		165	2734 00008A 0000 bfree .DW ; puntatore blocco free
		166	2735 00008C 0000 hdrptr .DW ; puntatore header heap
		167	2736
		168	2737 00008E 0000 pbrklv .DW ; current break level of current process
		169	2738 000090 0000 pbrkmin .DW ; minimum breal level of current process
		170	2739 000092 0000 pbrkmax .DW ; maximum breal level of current process
		171	2740 000094
		172	2741 ; bios temp. work area
		173	2742 000094 bwrktmp .DS $28
		174	2743
		175	2744 0000BC 00 coptmp .DB ; temp. used while cop
		176	2745
		177	2746 0000BD 00 tstser .DB ; check ser/usb test board post
		178	2747 ; <7>: VIA2 ok
		179	2748 ; <6>: PICRAM ok
		180	2749 ; <1>: UART 16C550 ok
		181	2750 ; <0>: R65C51 ok
		182	2751
		183	2752
		184	2753 ;crc16 .DW
		185	2754
		186	2755 0000BD .RELATIVE
		187	Tue Jul 17 11:11:08 2018 Page 4
		188
		189
		190
		191
		192	2756
		193	2757 .ENDS
		194	2758
		195	2759 [01] .IFDEF _ACIA_INC_
		196	2760 F8FE00 .INCLUDE INC\SP.INC
		197	2761 ;;
		198	2762 ;; Copyright (c) 2016 Marco Granati <mg@unet.bz>
		199	2763 ;;
		200	2764 ;; Permission to use, copy, modify, and distribute this software for any
		201	2765 ;; purpose with or without fee is hereby granted, provided that the above
		202	2766 ;; copyright notice and this permission notice appear in all copies.
		203	2767 ;;
		204	2768 ;; THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		205	2769 ;; WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		206	2770 ;; MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		207	2771 ;; ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		208	2772 ;; WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		209	2773 ;; ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		210	2774 ;; OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		211	2775 ;;
		212	2776
		213	2777 ;; name: sp.inc
		214	2778 ;; rev.: 2016/07/28
		215	2779 ;; bios C816 version v1.0
		216	2780
		217	2781 .LIST on
		218	2782
		219	2783 000001 SOH .EQU $01
		220	2784 000002 STX .EQU $02
		221	2785 000003 ETX .EQU $03
		222	2786 000004 EOT .EQU $04
		223	2787 000005 ENQ .EQU $05
		224	2788 000006 ACK .EQU $06
		225	2789 000010 DLE .EQU $10
		226	2790 000016 SYN .EQU $16
		227	2791
		228	2792 002000 SOBUFSIZ .EQU $2000 ; dimensione coda TX1/TX2 ACIA (8K)
		229	2793 ;SOBUFSIZ .EQU $0100 ; dimensione coda TX1/TX2 ACIA (8K)
		230	2794 004000 SIBUFSIZ .EQU $4000 ; dimensione coda RX1/RX2 ACIA (16K)
		231	2795 ;SIBUFSIZ .EQU $0100 ; dimensione coda RX1/RX2 ACIA (16K)
		232	2796
		233	2797 000080 NGUARD1 .EQU $80 ; numero bytes di guardia buffer RX XON/XOFF
		234	2798 000040 NGUARD2 .EQU $40 ; numero bytes di guardia buffer RX handshake
		235	2799 ;NGUARD1 .EQU $40 ; numero bytes di guardia buffer RX XON/XOFF
		236	2800 ;NGUARD2 .EQU $20 ; numero bytes di guardia buffer RX handshake
		237	2801 001000 NFREE1 .EQU $1000 ; minimo posto in coda RX per cancellare pausa remota
		238	2802 000800 NFREE2 .EQU $0800
		239	2803 ;NGUARD3 .EQU $F0
		240	2804 ;NGUARD4 .EQU $F8
		241	2805
		242	2806 ;---------------------------------------------------------------------------
		243	2807 ; direct page var's for serial ports handling
		244	2808 ;---------------------------------------------------------------------------
		245	2809
		246	2810 DPSP: .SECTION page0, common, ref_only, offset spwrk ;ACIA D.P.
		247	2811
		248	2812 000056 _DPSP_START .DS 0
		249	Tue Jul 17 11:11:08 2018 Page 5
		250
		251
		252
		253
		254	2813
		255	2814 ; WARNING: not change order and type of the following variables
		256	2815
		257	2816 ; acia 1 var's
		258	2817 000056 00 splin .DB ; interrupt status register
		259	2818 000057 00 spcsr .DB ; control status register
		260	2819 000058 00 spfr .DB ; format register
		261	2820 000059 00 spout .DB ; XON/XOFF send flag
		262	2821
		263	2822 ; acia 2 var's
		264	2823 00005A 00 splin2 .DB ; interrupt status register
		265	2824 00005B 00 spcsr2 .DB ; control status register
		266	2825 00005C 00 spfr2 .DB ; format register
		267	2826 00005D 00 spout2 .DB ; XON/XOFF send flag
		268	2827
		269	2828 ; serial port's mode & status
		270	2829 00005E 00 spmode .DB ; <7>: 0=no handshake, 1=handshake
		271	2830 ; <6>: 0=software/1=hardware handshake
		272	2831 ; <5>: not used
		273	2832 ; <4>: baud rate: 0=19200, 1=38400
		274	2833 ; <3>: 0=odd parity, 1=even parity
		275	2834 ; <2>: 0=no parity, 1=parity as specified
		276	2835 ; by bit <3>
		277	2836 ; <1>: interface type: 0=RS232, 1=RS485
		278	2837 ; <0>: RS232: uplink flow control (RTS/DCD)
		279	2838 ; RS485: 120 ohm termination on
		280	2839 ; if bit 7=1 and bit 1=1, bit 6 is forced to 0
		281	2840 00005F
		282	2841 00005F 00 spstat .DB ; serial port status
		283	2842 ; <7>: rx error (data discarded)
		284	2843 ; <6>: rx buffer overflow
		285	2844 ; <5>: remote disconnession (DSR line = 1)
		286	2845 ; <4>: output buffer overflow
		287	2846 ; <3>: not used
		288	2847 ; <2>: framing error
		289	2848 ; <1>: parity error
		290	2849 ; <0>: overrun error
		291	2850
		292	2851 000060 00 sppause .DB ; local/remote pause flag's
		293	2852 ; <7>: remote pause (sent an XON or set RTS=1)
		294	2853 ; <6>: local pause (received an XON or CTS=1)
		295	2854
		296	2855 000061 00 sptmp .DB ; temp. byte used while get data
		297	2856
		298	2857 ; serial port's mode & status
		299	2858 000062 00 spmode2 .DB ; <7>: 0=no handshake, 1=handshake
		300	2859 ; <6>: 0=software/1=hardware handshake
		301	2860 ; <5>: not used
		302	2861 ; <4>: baud rate: 0=19200, 1=38400
		303	2862 ; <3>: 0=odd parity, 1=even parity
		304	2863 ; <2>: 0=no parity, 1=parity as specified
		305	2864 ; by bit <3>
		306	2865 ; <1>: interface type: 0=RS232, 1=RS485
		307	2866 ; <0>: RS232: uplink flow control (RTS/DCD)
		308	2867 ; RS485: 120 ohm termination on
		309	2868 ; if bit 7=1 and bit 1=1, bit 6 is forced to 0
		310	2869 000063
		311	Tue Jul 17 11:11:08 2018 Page 6
		312
		313
		314
		315
		316	2870 000063 00 spstat2 .DB ; serial port status
		317	2871 ; <7>: rx error (data discarded)
		318	2872 ; <6>: rx buffer overflow
		319	2873 ; <5>: remote disconnession (DSR line = 1)
		320	2874 ; <4>: output buffer overflow
		321	2875 ; <3>: not used
		322	2876 ; <2>: framing error
		323	2877 ; <1>: parity error
		324	2878 ; <0>: overrun error
		325	2879
		326	2880 000064 00 sppause2 .DB ; local/remote pause flag's
		327	2881 ; <7>: remote pause (sent XOFF/XON or RTS=1/0)
		328	2882 ; <6>: local pause (rx XOFF/XON or CTS=0/1)
		329	2883
		330	2884 000065 00 sppost .DB ; after POST must hold $C0
		331	2885
		332	2886 000066 0000 ibuftail .DW ; pointer to tail of input buffer
		333	2887 000068 0000 ibufhead .DW ; pointer to head of input buffer
		334	2888 00006A 0000 ibuftail2 .DW
		335	2889 00006C 0000 ibufhead2 .DW
		336	2890
		337	2891 00006E 0000 obuftail .DW ; pointer to tail of output buffer
		338	2892 000070 0000 obufhead .DW ; pointer to head of output buffer
		339	2893 000072 0000 obuftail2 .DW
		340	2894 000074 0000 obufhead2 .DW
		341	2895
		342	2896 000076 0000 ibufcnt .DW ; count of bytes in input buffer
		343	2897 000078 0000 obufcnt .DW ; count of bytes in output buffer
		344	2898 00007A 0000 ibufcnt2 .DW
		345	2899 00007C 0000 obufcnt2 .DW
		346	2900
		347	2901 00007E 0000 icntmin .DW ; min. count for clear remote pause
		348	2902 000080 0000 icntmax .DW ; max. count for set remote pause
		349	2903 000082 0000 icntmin2 .DW
		350	2904 000084 0000 icntmax2 .DW
		351	2905
		352	2906 000086 _DPSP_END .DS 0
		353	2907 000030 DPSPSIZ .EQU (_DPSP_END - _DPSP_START)
		354	2908
		355	2909
		356	2910 .ENDS
		357	2911
		358	2912 00005F ACIArxe_1 .EQU spstat
		359	2913 000063 ACIArxe_2 .EQU spstat2
		360	2914 00005E ACIAhsk_1 .EQU spmode
		361	2915 000062 ACIAhsk_2 .EQU spmode2
		362	2916 000060 ACIAPause_1 .EQU sppause
		363	2917 000064 ACIAPause_2 .EQU sppause2
		364	2918 000057 ACIAcsr_1 .EQU spcsr
		365	2919 00005B ACIAcsr_2 .EQU spcsr2
		366	2920 000058 ACIAfr_1 .EQU spfr
		367	2921 00005C ACIAfr_2 .EQU spfr2
		368	2922 000060 ACIAOut_1 .EQU sppause
		369	2923 000064 ACIAOut_2 .EQU sppause2
		370	2924 000076 ACIAICnt_1 .EQU ibufcnt
		371	2925 00007A ACIAICnt_2 .EQU ibufcnt2
		372	2926 000068 ACIAIHead_1 .EQU ibufhead
		373	Tue Jul 17 11:11:08 2018 Page 7
		374
		375
		376
		377
		378	2927 00006C ACIAIHead_2 .EQU ibufhead2
		379	2928 000066 ACIAITail_1 .EQU ibuftail
		380	2929 00006A ACIAITail_2 .EQU ibuftail2
		381	2930 000078 ACIAOCnt_1 .EQU obufcnt
		382	2931 00007C ACIAOCnt_2 .EQU obufcnt2
		383	2932 000070 ACIAOHead_1 .EQU obufhead
		384	2933 000074 ACIAOHead_2 .EQU obufhead2
		385	2934 00006E ACIAOTail_1 .EQU obuftail
		386	2935 000072 ACIAOTail_2 .EQU obuftail2
		387	2936
		388	2937 002000 ACIAOBUFLEN .EQU SOBUFSIZ
		389	2938 004000 ACIAIBUFLEN .EQU SIBUFSIZ
		390	2939 050000 ACIAOUTBUF1 .EQU SPOUTBUFF
		391	2940 052000 ACIAOUTBUF2 .EQU SPOUTBUFF2
		392	2941 054000 ACIAINBUF1 .EQU SPINBUFF
		393	2942 058000 ACIAINBUF2 .EQU SPINBUFF2
		394	2943
		395	2944 000061 ACIATmp .EQU sptmp
		396	2945
		397	2963 .LIST on
		398	2964
		399	2965 000060 KBDBUFLEN .EQU 96 ; dimensione buffer di tastiera
		400	2966
		401	2967 DIRP01: .SECTION page0, ref_only, common ;Direct-Page 01
		402	2968
		403	2969 000000 .ABSOLUTE ;; inizia sempre da $00
		404	2970 000000 .ORG 0x00
		405	2971
		406	2972 000000
		407	2973 000000 KbdBuf .DS KBDBUFLEN ; buffer della tastiera
		408	2974 000060 00 KbdITail .DB ; coda buffer tastiera
		409	2975 000061 00 KbdIHead .DB ; testa buffer tastiera
		410	2976 000062 00 KbdCnt .DB ; numero bytes nel buffer
		411	2977 000063 00 KbdShift .DB
		412	2978 000064 00 KbdFlag .DB
		413	2979 000065 00 KbdToggle .DB
		414	2980 000066 00 KbdSt .DB ; status tastiera dopo reset
		415	2981 000067 00 PS2Ctl .DB ; flag controller PS2 keyboard
		416	2982
		417	2983 000068 00 LCDFlag .DB
		418	2984 000069 00 LCDTmp .DB
		419	2985 00006A 0000 LCDVal .DW
		420	2986
		421	2987 00006C 00 VBBFlag .DB ; flag video board
		422	2988 00006D 00 VBBRam .DB ; flag video RAM
		423	2989
		424	2990 00006E 00 ScnLinTmp .DB
		425	2991 00006F 00 ScnChBase .DB ; base video ram VDC
		426	2992 000070 00 ScnAttBase .DB ; base ram attributi VDC
		427	2993 000071 00 ScnCursMode .DB ; VDC cursore default
		428	2994 000072 00 ScnSaveAttr .DB
		429	2995 000073 00 ScnInsert .DB
		430	2996 000074 00 ScnAutoIns .DB ; bit 7 -> autoins - bit 6 -> modo input
		431	2997 000075 00 ScnScroll .DB
		432	2998 000076 00 ScnMaxRow .DB ; max. righe finestra (-1)
		433	2999 000077 00 ScnMaxCols .DB ; max. colonne finestra (-1)
		434	3000
		435	Tue Jul 17 11:11:08 2018 Page 8
		436
		437
		438
		439
		440	3001 000078 ScnMapTabs1 .DS 10
		441	3002 000082 ScnMapTabs2 .DS 4
		442	3003 000086
		443	3004 000086 0000 ScnPtr .DW ; puntatore video ram linea corrente
		444	3005 000088 00 .DB
		445	3006
		446	3007 000089 00 ScnFiltLen .DB ; lunghezza set caratteri filtro
		447	3008
		448	3009 00008A 0000 ScnAtPtr .DW ; puntatore attributi ram linea corrente
		449	3010 00008C 00 .DB
		450	3011
		451	3012 00008D 00 ScnTmpx .DB ; temporaneo: durante put char
		452	3013 00008E
		453	3014 00008E 00 ScnTop .DB ; riga superiore finestra
		454	3015 00008F 00 ScnLeft .DB ; colonna sinistra finestra
		455	3016 000090 00 ScnBottom .DB ; riga inferiore finestra
		456	3017 000091 00 ScnRight .DB ; colonna destra finestra
		457	3018 000092 00 ScnAttr .DB ; attributo default
		458	3019 000093 00 ScnAttr2 .DB ; attributo alternativo
		459	3020 000094 00 ScnRow .DB ; riga cursore
		460	3021 000095 00 ScnCol .DB ; colonna cursore
		461	3022 000096 00 ScnRowStart .DB ; riga di start input
		462	3023 000097 00 ScnInput .DB ; riga di fine input
		463	3024 000098 00 ScnColStart .DB ; colonna di start input
		464	3025 000099 00 ScnSaveX .DB
		465	3026 00009A 00 ScnSaveY .DB
		466	3027 00009B 00 ScnTmpL .DB
		467	3028 00009C 00 ScnTmpH .DB
		468	3029 00009D 00 ScnSaveRow .DB
		469	3030 00009E 00 ScnSaveCol .DB
		470	3031 00009F 00 ScnCurChr .DB
		471	3032 0000A0 00 ScnLstChr .DB
		472	3033 0000A1 00 ScnCR .DB
		473	3034 0000A2 0000 ScnPrm .DW ; puntatore long utilizzato da print imm
		474	3035 0000A4 00 .DB ; banco puntatore ScnPrm
		475	3036 0000A5 00 ScnMode .DB ; flag modo schermo
		476	3037
		477	3038 0000A6 ScnPtr1 LP
		478	3039
		479	3040 0000A9 00 ScnDefCol .DB ; default foreground color
		480	3041
		481	3042 0000AA ScnPtr2 LP
		482	3043
		483	3044 0000AD 00 ScnDefBkgCol .DB ; default background color
		484	3045 0000AE 00 ScnInpRow .DB ; modo input line: riga start input
		485	3046 0000AF 00 ScnInpCol .DB ; modo input line: colonna start input
		486	3047 0000B0 00 ScnLstRow .DB ; modo input line: riga stop input
		487	3048 0000B1 00 ScnLstCol .DB ; modo input line: colonna stop input
		488	3049 0000B2 00 ScnFlag .DB ; Bit 7: input line - Bit 6: input riga unica
		489	3050 0000B3 00 ScnMask .DB ; flag tasti funzione editor di linea
		490	3051 0000B4 00 ScnFilt .DB ; filtro tasti editor di linea
		491	3052 0000B5 00 ScnCntrl .DB ; flag ASCII/CONTROL
		492	3053 ;DflTxtIn .DB ; device di default text input
		493	3054 ;DflTxtOut .DB ; device di default text output
		494	3055 0000B6
		495	3056 000047 SCNCLRLEN .EQU ($ - ScnLinTmp - 1)
		496	3057
		497	Tue Jul 17 11:11:08 2018 Page 9
		498
		499
		500
		501
		502	3058 ;SCNCLRLEN .EQU (DflTxtOut - ScnLinTmp)
		503	3059
		504	3060 ; variabili monitor
		505	3061 0000B6 00 SMAddrL .DB ; address low/high
		506	3062 0000B7 00 SMAddrH .DB
		507	3063 0000B8 00 SMAddrK .DB ; address bank
		508	3064 0000B9 00 SMFlag32 .DB ; flag parametro 32 bit
		509	3065 0000BA 00 SMTmpL .DB ; temp. low/high
		510	3066 0000BB 00 SMTmpH .DB
		511	3067 0000BC 00 SMTmpK .DB ; temp. bank
		512	3068 0000BD 00 SMTmpKK .DB ; high byte param. 32 bit
		513	3069 0000BE 00 SMSizeL .DB ; size low/high
		514	3070 0000BF 00 SMSizeH .DB
		515	3071 0000C0 00 SMSizeK .DB ; size bank
		516	3072 0000C1 00 SMXAddrL .DB ; address low/high XM
		517	3073 0000C2 00 SMXAddrH .DB
		518	3074 0000C3 00 SMXAddrK .DB ; address bank XM
		519	3075 0000C4 00 SMbndx .DB ; indice input buffer
		520	3076 0000C5 00 SMnprm .DB ; numero parametri riga di comando
		521	3077 0000C6 00 SMdumb .DB
		522	3078 0000C7 00 SMkr .DB
		523	3079 0000C8 0000 SMpc .DW
		524	3080 0000CA 00 SMsr .DB
		525	3081 0000CB 00 SMbr .DB
		526	3082 0000CC 0000 SMdp .DW
		527	3083 0000CE 0000 SMac .DW
		528	3084 0000D0 0000 SMxr .DW
		529	3085 0000D2 0000 SMyr .DW
		530	3086 0000D4 0000 SMsp .DW
		531	3087
		532	3088 0000D6 00 SMAuxL .DB
		533	3089 0000D7 00 SMAuxH .DB
		534	3090
		535	3091 0000D8 00 asmlong .DB ; flag for CPU in 16 mode
		536	3092 ; <7> -> A/M in 16 bit mode
		537	3093 ; <6> -> X/Y in 16 bit mode
		538	3094 0000D9 00 asmcpu .DB ; <7> -> 8 bit family
		539	3095 ; <6> -> 65C02 cmos version
		540	3096
		541	3097 0000DA 00 SMctx .DB ; context (if = $00 no quit command)
		542	3098 0000DB SMrsm LP ; long pointer to resume caller context
		543	3099
		544	3100 0000DE 00 rtcadr .DB ; rtc internal ram address
		545	3101 0000DF 00 rtcbnk .DB ; RTC internal bank ram
		546	3102 0000E0 00 cmdlin .DB ;
		547	3103 0000E1 00 SMesc .DB
		548	3104
		549	3105 0000E2 SMXTmp: .DS 26 ; 26 bytes tmp
		550	3106
		551	3107 0000E2 SMTmp2 .EQU SMXTmp
		552	3108 0000E4 SMTmp3 .EQU SMXTmp+2
		553	3109 0000E6 SMdwTmp1 .EQU SMXTmp+4
		554	3110 0000EA SMdwTmp2 .EQU SMXTmp+8
		555	3111 0000EE SMFsrc .EQU SMXTmp+12 ; source bank for flash update
		556	3112 0000EF SMFflag .EQU SMXTmp+13 ; flag file for flash update
		557	3113 0000F0 SMXPos2 .EQU SMXTmp+14
		558	3114 0000F1 SMYPos2 .EQU SMXTmp+15
		559	Tue Jul 17 11:11:08 2018 Page 10
		560
		561
		562
		563
		564	3115 0000F2 SMXPos3 .EQU SMXTmp+16
		565	3116 0000F3 SMYPos3 .EQU SMXTmp+17
		566	3117 ;SMAuxL .EQU SMXTmp+18
		567	3118 ;SMAuxH .EQU SMXTmp+19
		568	3119 0000F6 SMXPos .EQU SMXTmp+20
		569	3120 0000F7 SMYPos .EQU SMXTmp+21
		570	3121 0000F8 SMdwTmp3 .EQU SMXTmp+22
		571	3122
		572	3123 0000E2 atcmd .EQU SMXTmp ; save @ command
		573	3124 0000E3 atnum .EQU SMXTmp+1 ; @ command index
		574	3125 0000E4 atflag .EQU SMXTmp+2 ; @ L,S,V,R,W start address flag
		575	3126 0000E5 atbnk .EQU SMXTmp+3 ; @ L,S,V,R,W bank
		576	3127 0000E6 atstr .EQU SMXTmp+4 ; @ command string start (word)
		577	3128 0000E8 atstart .EQU SMXTmp+6 ; @ L,S,V,R,W start address (word)
		578	3129 0000EA atend .EQU SMXTmp+8 ; @ S,W end address (word)
		579	3130 0000EC atbuf .EQU SMXTmp+10 ; @ local buffer pointer (word)
		580	3131 0000EE atipb .EQU SMXTmp+12 ; @ bank of input buffer
		581	3132 0000EF atdir .EQU SMXTmp+13 ; @ load dir flag
		582	3133 0000F0 atptr .EQU SMXTmp+14 ; @ load dir pointer (word)
		583	3134 0000F2 atsiz .EQU SMXTmp+16 ; @ buffer size (word)
		584	3135 0000F5 atlp .EQU SMXTmp+19 ; @ long pointer
		585	3136 0000F8 atsa .EQU SMXTmp+22 ; @ sa
		586	3137
		587	3138 0000E2 btmpx .EQU SMXTmp ; asc2bin conversion
		588	3139 0000E3 brtcsec .EQU SMXTmp+1
		589	3140 0000E4 brtcmin .EQU SMXTmp+2
		590	3141 0000E5 brtchour .EQU SMXTmp+3
		591	3142 0000E6 brtcday .EQU SMXTmp+4
		592	3143 0000E7 brtcmonth .EQU SMXTmp+5
		593	3144 0000E8 brtcyear .EQU SMXTmp+6
		594	3145 0000E9 brtcct .EQU SMXTmp+7
		595	3146
		596	3147
		597	3148 0000FC .RELATIVE
		598	3149
		599	3150 .ENDS
		600	3151
		601	3175 .LIST on
		602	3176
		603	3177 05C000 SOBUFADDR3 .EQU SPOUTBUFF3
		604	3178 05D000 SIBUFADDR3 .EQU SPINBUFF3
		605	3179 001000 SOBUFSIZ3 .EQU $1000
		606	3180 001000 SIBUFSIZ3 .EQU $1000
		607	3181
		608	3182 060000 SOBUFADDR4 .EQU SPOUTBUFF4
		609	3183 068000 SIBUFADDR4 .EQU SPINBUFF4
		610	3184 ;SOBUFSIZ4 .EQU $1000
		611	3185 ;SIBUFSIZ4 .EQU $1000
		612	3186 008000 SOBUFSIZ4 .EQU $8000
		613	3187 008000 SIBUFSIZ4 .EQU $8000
		614	3188
		615	3189 000200 NGUARD31 .EQU $0200 ; numero bytes di guardia buffer RX XON/XOFF
		616	3190 000100 NGUARD32 .EQU $0100 ; numero bytes di guardia buffer RX handshake
		617	3191 000800 NFREE31 .EQU $0800 ; minimo posto in coda RX per cancellare pausa remota
		618	3192 000400 NFREE32 .EQU $0400
		619	3193
		620	3194 ;---------------------------------------------------------------------------
		621	Tue Jul 17 11:11:08 2018 Page 11
		622
		623
		624
		625
		626	3195 ; direct page var's for test serial ports/usb handling
		627	3196 ;---------------------------------------------------------------------------
		628	3197
		629	3198 DPSP2: .SECTION page0, common, ref_only ;UART D.P.
		630	3199
		631	3200 000000 00 usbslv .DB ; <7>: plugged-in, <6>: plug-in pending
		632	3201 000001 00 usbum .DB ; <7>: pending message, <6>: connected
		633	3202 000002 00 usbcnt1 .DB ; timeout UM245 plug-in detection
		634	3203 000003 usbbuf .DS 8
		635	3204 00000B 00 usbtim .DB
		636	3205 00000C 00 usbcnt .DB
		637	3206 00000D 00 usbmst .DB
		638	3207 00000E 0000 usbsiz .DW
		639	3208 000010 usbptr LP
		640	3209 000013 00 usbtmp .DB
		641	3210 000014 00 usbcmp .DB
		642	3211
		643	3212 ; serial port 65C51
		644	3213 000015 00 spmode3 .DB ; <7>: 0=no handshake, 1=handshake
		645	3214 ; <6>: 0=software/1=hardware handshake
		646	3215 ; <5>: not used
		647	3216 ; <4>: not used
		648	3217 ; <3>: 0=odd parity, 1=even parity
		649	3218 ; <2>: 0=no parity, 1=parity as specified
		650	3219 ; by bit <3>
		651	3220 ; <1:0> : baud rate
		652	3221 ; 00 = 19200
		653	3222 ; 01 = 38400
		654	3223 ; 10 = 57600
		655	3224 ; 11 = 115200
		656	3225 000016
		657	3226 000016 00 splin3 .DB ; <7>: /CTS line level
		658	3227 ; <6>: /DSR line status
		659	3228 000017
		660	3229 000017 00 sppause3 .DB
		661	3230 000018 00 spout3 .DB
		662	3231 000019 00 spstat3 .DB ; staus
		663	3232 ; <7>: rx error (data discarded)
		664	3233 ; <6>: rx buffer overflow
		665	3234 ; <5>: remote disconnession (/DSR line = 1)
		666	3235 ; <4>: output buffer overflow
		667	3236 ; <3>: not used
		668	3237 ; <2>: framing error
		669	3238 ; <1>: parity error
		670	3239 ; <0>: overrun error
		671	3240
		672	3241 00001A 00 sptmp3 .DB
		673	3242
		674	3243 00001B 0000 ibuftail3 .DW
		675	3244 00001D 0000 ibufhead3 .DW
		676	3245 00001F 0000 obuftail3 .DW
		677	3246 000021 0000 obufhead3 .DW
		678	3247 000023 0000 ibufcnt3 .DW
		679	3248 000025 0000 obufcnt3 .DW
		680	3249 000027 0000 icntmin3 .DW
		681	3250 000029 0000 icntmax3 .DW
		682	3251
		683	Tue Jul 17 11:11:08 2018 Page 12
		684
		685
		686
		687
		688	3252 ; serial port 16C550
		689	3253 00002B 00 spmode4 .DB ; <7>: 0=no handshake, 1=handshake
		690	3254 ; <6>: 0=software/1=hardware handshake
		691	3255 ; <5>: not used
		692	3256 ; <4>: not used
		693	3257 ; <3>: 0=odd parity, 1=even parity
		694	3258 ; <2>: 0=no parity, 1=parity as specified
		695	3259 ; by bit <3>
		696	3260 ; <1:0> : baud rate
		697	3261 ; 00 = 19200
		698	3262 ; 01 = 38400
		699	3263 ; 10 = 57600
		700	3264 ; 11 = 115200
		701	3265 00002C
		702	3266 00002C 00 splin4 .DB ; <7>: /DSR line level
		703	3267 ; <6>: /CTS line status
		704	3268 00002D
		705	3269 00002D 00 sppause4 .DB
		706	3270 00002E 00 spout4 .DB
		707	3271 00002F 00 spstat4 .DB ; staus
		708	3272 ; <7>: rx error (data discarded)
		709	3273 ; <6>: rx buffer overflow
		710	3274 ; <5>: remote disconnession (/DSR line = 1)
		711	3275 ; <4>: output buffer overflow
		712	3276 ; <3>: break
		713	3277 ; <2>: framing error
		714	3278 ; <1>: parity error
		715	3279 ; <0>: overrun error
		716	3280
		717	3281 000030 00 sptmp4 .DB
		718	3282
		719	3283 000031 0000 ibuftail4 .DW
		720	3284 000033 0000 ibufhead4 .DW
		721	3285 000035 0000 obuftail4 .DW
		722	3286 000037 0000 obufhead4 .DW
		723	3287 000039 0000 ibufcnt4 .DW
		724	3288 00003B 0000 obufcnt4 .DW
		725	3289 00003D 0000 icntmin4 .DW
		726	3290 00003F 0000 icntmax4 .DW
		727	3291
		728	3292 000041 00 spcnt4 .DB
		729	3293 000042 00 uartlsr .DB
		730	3294 000043 00 uartiir .DB
		731	3295
		732	3296 000044 usb0name .DS 36
		733	3297
		734	3298 .ENDS
		735	3299
		736	3305 .LIST on
		737	3306
		738	3307 .CODEF8
		739	3308
		740	3309 ;----------------------------------------------------------
		741	3310 ; ---- CODICE START & INTERRUPT
		742	3311 ;----------------------------------------------------------
		743	3312
		744	3313 .SYSCODE
		745	Tue Jul 17 11:11:08 2018 Page 13
		746
		747
		748
		749
		750	3314 F8F000
		751	3315 000162 _KbdCnt .EQU (DP01ADDR + KbdCnt)
		752	3316 000165 _KbdToggle .EQU (DP01ADDR + KbdToggle)
		753	3317 000166 _KbdSt .EQU (DP01ADDR + KbdSt)
		754	3318 000167 _PS2Ctl .EQU (DP01ADDR + PS2Ctl)
		755	3319 000160 _KbdITail .EQU (DP01ADDR + KbdITail)
		756	3320 000161 _KbdIHead .EQU (DP01ADDR + KbdIHead)
		757	3321 000163 _KbdShift .EQU (DP01ADDR + KbdShift)
		758	3322 000164 _KbdFlag .EQU (DP01ADDR + KbdFlag)
		759	3323 F8F000
		760	3324 F8F000 LONG_OFF
		761	3325 .LONGA off
		762	3326 .LONGI off
		763	3327 .MNLIST
		764	3328 F8F000
		765	3329 .GLOBAL _KbdCnt, _KbdToggle, _KbdSt, _PS2Ctl, _KbdITail
		766	3330 .GLOBAL _KbdIHead, _KbdShift, _KbdFlag
		767	3331 .GLOBAL TORAM
		768	3332
		769	3333 F8F000 TORAM:
		770	3334 ; vettori ISR
		771	3335 F8F000 intsr:
		772	3336 F8F000 10F0 04F1 F8F1 .DW int0sr, int1sr, int2sr, int3sr
		773	ACF2
		774	3337 F8F008 D3F3 C9F5 C9F5 .DW int4sr, int5sr, int6sr, int7sr
		775	CAF5
		776	3338
		777	3339 F8F010 int0sr:
		778	3340 F8F010 SPISR 0
		779	3341 [01] .IFZ 0
		780	3342 000000 k .SET 0
		781	3343 050000 SOBUFADDR .SET SPOUTBUFF
		782	3344 054000 SIBUFADDR .SET SPINBUFF
		783	3345 [01] .ELSE
		784	3346 k .SET 4
		785	3347 SOBUFADDR .SET SPOUTBUFF2
		786	3348 SIBUFADDR .SET SPINBUFF2
		787	3349 [00] .ENDIF
		788	3350
		789	3351 F8F010 AC 50 FD ldy .ABS.ACIAISR+k ; interrupt status reg. (clear bit 3,4,5)
		790	3352 F8F013 AD 51 FD lda .ABS.ACIACSR+k ; control status register
		791	3353 ;sty spisr+k ; save interrupt status reg.
		792	3354 F8F016 85 57 sta spcsr+k ; save control status reg.
		793	3355 F8F018 98 tya ; Y=status reg.
		794	3356 F8F019 4A lsr a ; test RDRF bit
		795	3357 F8F01A 90 76 bcc ?lin ; go to test control lines
		796	3358 F8F01C AE 53 FD ldx .ABS.ACIARDR+k ; fetch rx data (clear int. status bits 0,1,2)
		797	3359 F8F01F 24 5F bit spstat+k ; rx error pending?
		798	3360 F8F021 30 6F bmi ?lin ; yes, discard received data & test ctr. lines
		799	3361 F8F023 29 03 and #00000011B ; 1: overrun/frame error, 2: parity error
		800	3362 F8F025 24 57 bit spcsr+k ; test control status reg. bit 7: FE
		801	3363 F8F027 10 04 bpl ?nof ; no framing error
		802	3364 F8F029 09 04 ora #00000100B ; set framing error bit...
		803	3365 F8F02B 29 FE and #$FE ; ...and clear overrun error
		804	3366 F8F02D C9 00 ?nof: cmp #0
		805	3367 F8F02F F0 04 beq ?rxok ; no rx error
		806	3368 F8F031 09 80 ora #10000000B ; set rx error bit
		807	Tue Jul 17 11:11:08 2018 Page 14
		808
		809
		810
		811
		812	3369 F8F033 80 45 bra ?sst ; set stus reg. & discard received data
		813	3370 F8F035 8A ?rxok: txa ; A=received data
		814	3371 F8F036 INDEX16
		815	3372 .MLIST
		816	3373 F8F036 C2 10 rep #PXFLAG
		817	3374 .LONGI on
		818	3375 .MNLIST
		819	3376 F8F038 A6 76 ldx ibufcnt+k ; count of bytes stored in input buffer
		820	3377 F8F03A 24 5E bit spmode+k ; test if handshake is active
		821	3378 F8F03C 10 35 bpl ?chk ; bit 7=0 -> no handshake so check input buff.
		822	3379 F8F03E 70 14 bvs ?tst ; bit 6=1 -> hardware handshake
		823	3380 F8F040 C9 11 cmp #SPXON ; received an XON control byte?
		824	3381 F8F042 D0 06 bne ?xoff ; no, check if received an XOFF
		825	3382 F8F044 A9 40 lda #$40 ; received an XON: clear local pause flag
		826	3383 F8F046 14 60 trb sppause+k ; bit 6=0 -> local pause off (resume tx)
		827	3384 F8F048 80 46 bra ?cnt ; discard received data
		828	3385 F8F04A C9 13 ?xoff: cmp #SPXOFF ; received an XOFF control byte?
		829	3386 F8F04C D0 06 bne ?tst ; no, check condition for remote pause
		830	3387 F8F04E A9 40 lda #$40 ; set local pause flag
		831	3388 F8F050 04 60 tsb sppause+k ; bit 6=1 -> local pause on (stop tx operation)
		832	3389 F8F052 80 3C bra ?cnt ; discard received data
		833	3390 F8F054 E4 80 ?tst: cpx icntmax+k ; check input buff. for remote pause condition
		834	3391 F8F056 90 26 bcc ?str ; below guard limit: store data
		835	3392 F8F058 24 60 bit sppause+k ; remote pause is already on ?
		836	3393 F8F05A 30 17 bmi ?chk ; yes, so check input buffer
		837	3394 F8F05C EB xba ; B = received data
		838	3395 F8F05D 24 5E bit spmode+k ; test handshake type
		839	3396 F8F05F 70 06 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=1
		840	3397 F8F061 A9 13 lda #SPXOFF ; send an XOFF to remote terminal
		841	3398 F8F063 85 59 sta spout+k ; XOFF sending deffered until TDRE is set
		842	3399 F8F065 80 0B bra ?xba ; check input buffer
		843	3400 F8F067 A5 58 ?rtsh: lda spfr+k ; hardware handshake...
		844	3401 F8F069 09 81 ora #10000001B ; ...set RTS=1
		845	3402 F8F06B 8D 51 FD sta .ABS.ACIAFR+k ; update format register
		846	3403 F8F06E A9 80 lda #$80 ; set remote pause
		847	3404 F8F070 04 60 tsb sppause+k ; bit 7=1 -> remote pause on
		848	3405 F8F072 EB ?xba: xba ; A = received data
		849	3406 F8F073 E0 00 40 ?chk: cpx #SIBUFSIZ ; left room in input buffer?
		850	3407 F8F076 90 06 bcc ?str ; yes, store received byte
		851	3408 F8F078 A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow
		852	3409 F8F07A 85 5F ?sst: sta spstat+k ; set status register
		853	3410 F8F07C 80 12 bra ?cnt ; discard received data
		854	3411 F8F07E E8 ?str: inx ; now store received data
		855	3412 F8F07F 86 76 stx ibufcnt+k ; update bytes count
		856	3413 F8F081 A6 66 ldx ibuftail+k ; pointer to rx tail queue
		857	3414 F8F083 9F 00 40 05 sta >SIBUFADDR,x
		858	3415 F8F087 E8 inx ; update tail pointer
		859	3416 F8F088 CPU16
		860	3417 .MLIST
		861	3418 F8F088 C2 30 rep #(PMFLAG.OR.PXFLAG)
		862	3419 .LONGA on
		863	3420 .LONGI on
		864	3421 .MNLIST
		865	3422 F8F08A 8A txa
		866	3423 F8F08B 29 FF 3F and #(SIBUFSIZ-1) ; circular queue
		867	3424 F8F08E 85 66 sta ibuftail+k
		868	3425 F8F090 ?cnt: CPU08 ; continue...
		869	Tue Jul 17 11:11:08 2018 Page 15
		870
		871
		872
		873
		874	3426 .MLIST
		875	3427 F8F090 E2 30 sep #(PMFLAG.OR.PXFLAG)
		876	3428 .LONGA off
		877	3429 .LONGI off
		878	3430 .MNLIST
		879	3431 F8F092 A5 57 ?lin: lda spcsr+k ; get control lines status
		880	3432 F8F094 29 3B and #00111011B ; mask lines level
		881	3433 F8F096 89 08 bit #00001000B ; check DSR line level
		882	3434 F8F098 F0 02 beq ?lin2 ; DSR is low
		883	3435 F8F09A 09 40 ora #01000000B ; DSR is high
		884	3436 F8F09C 0A ?lin2: asl a ; 7:DSR, 6:CTS, 5:DCD, 2:DTR, 1:RTS
		885	3437 F8F09D 85 56 sta splin+k ; save lines level
		886	3438 ;tya
		887	3439 F8F09F 24 5E bit spmode+k ; test for active handshake
		888	3440 F8F0A1 10 24 bpl ?cnt2 ; no handshake, so ignore CTS/DCD trans.
		889	3441 F8F0A3 50 22 bvc ?cnt2 ; softw. handshake, so ignore CTS/DCD trans.
		890	3442 ;bit #00001000B ; change state on DSR line?
		891	3443 ;beq ?cts ; no, go to check CTS line
		892	3444 ;ldx #00100000B ; remote disconnession flag
		893	3445 ;lda #00001000B ; check DSR line level
		894	3446 ;bit spcsr+k
		895	3447 ;beq ?dsrl ; DSR line at low level
		896	3448 ;txa ; remote disconnession
		897	3449 ;tsb spstat+k ; set status register
		898	3450 ;bra ?cts
		899	3451 ;?dsrl: ;txa ; remote terminal ready
		900	3452 ;trb spstat+k ; set status register
		901	3453 ;?cts:
		902	3454 F8F0A5 A5 5E lda spmode+k
		903	3455 F8F0A7 4A lsr a ; check if uplink handshake (RTS/DCD control)
		904	3456 F8F0A8 98 tya ; A=interrupt status reg.
		905	3457 F8F0A9 B0 08 bcs ?dcd ; yes, so check DCD line (uplink cable)
		906	3458 F8F0AB 89 20 bit #00100000B ; change state on CTS line?
		907	3459 F8F0AD F0 19 beq ?chkt ; no, so check TDRE flag
		908	3460 F8F0AF A9 20 lda #00100000B ; check CTS line level
		909	3461 F8F0B1 80 06 bra ?lvl
		910	3462 F8F0B3 89 10 ?dcd: bit #00010000B ; change state on DCD line?
		911	3463 F8F0B5 F0 11 beq ?chkt ; no, so check TDRE flag
		912	3464 F8F0B7 A9 10 lda #00010000B ; check DCD line level
		913	3465 F8F0B9 A2 40 ?lvl: ldx #$40 ; local pause flag
		914	3466 F8F0BB 24 57 bit spcsr+k
		915	3467 F8F0BD F0 05 beq ?clp ; CTS (or DCD) = low so clear local pause
		916	3468 F8F0BF 8A txa ; CTS (or DCD) = high so set local pause
		917	3469 F8F0C0 04 60 tsb sppause+k
		918	3470 F8F0C2 80 03 bra ?cnt2
		919	3471 F8F0C4 8A ?clp: txa
		920	3472 F8F0C5 14 60 trb sppause+k
		921	3473 F8F0C7 98 ?cnt2: tya
		922	3474 F8F0C8 0A ?chkt: asl a ; check TDRE bit
		923	3475 F8F0C9 10 11 bpl ?end ; TDRE=0: can't transmit at this time
		924	3476 F8F0CB A5 59 lda spout+k ; pending an XON/XOFF sending?
		925	3477 F8F0CD F0 13 beq ?cklp ; no... check local pause flag
		926	3478 F8F0CF 8D 53 FD sta .ABS.ACIATDR+k ; send XON/XOFF
		927	3479 F8F0D2 64 59 stz spout+k ; clear XON/XOFF flag
		928	3480 F8F0D4 C9 13 cmp #SPXOFF
		929	3481 F8F0D6 F0 05 beq ?srp ; sent an XOFF
		930	3482 F8F0D8 A9 80 lda #$80 ; sent an XON: clear remote pause flag
		931	Tue Jul 17 11:11:08 2018 Page 16
		932
		933
		934
		935
		936	3483 F8F0DA 14 60 trb sppause+k ; bit 7 = 0 -> remote pause off
		937	3484 F8F0DC 60 ?end: rts ; done
		938	3485 F8F0DD A9 80 ?srp: lda #$80 ; set remote pause flag
		939	3486 F8F0DF 04 60 tsb sppause+k
		940	3487 F8F0E1 60 rts
		941	3488 F8F0E2 24 60 ?cklp: bit sppause+k ; local pause is set ?
		942	3489 F8F0E4 70 F6 bvs ?end ; yes, no tx possible at this time
		943	3490 ;bit spcsr+k ; check if remote terminal is ready
		944	3491 ;bmi ?end ; not ready, skip tx
		945	3492 F8F0E6 INDEX16
		946	3493 .MLIST
		947	3494 F8F0E6 C2 10 rep #PXFLAG
		948	3495 .LONGI on
		949	3496 .MNLIST
		950	3497 F8F0E8 A6 78 ldx obufcnt+k ; count of bytes in output buffer
		951	3498 F8F0EA F0 15 beq ?done ; output buffer is empty: nothing to send
		952	3499 F8F0EC CA dex ; update count
		953	3500 F8F0ED 86 78 stx obufcnt+k
		954	3501 F8F0EF A6 70 ldx obufhead+k ; pointer to head of out buffer
		955	3502 F8F0F1 BF 00 00 05 lda >SOBUFADDR,x ; get data from output buffer
		956	3503 F8F0F5 8D 53 FD sta .ABS.ACIATDR+k ; send data
		957	3504 F8F0F8 E8 inx ; update head pointer
		958	3505 F8F0F9 CPU16
		959	3506 .MLIST
		960	3507 F8F0F9 C2 30 rep #(PMFLAG.OR.PXFLAG)
		961	3508 .LONGA on
		962	3509 .LONGI on
		963	3510 .MNLIST
		964	3511 F8F0FB 8A txa
		965	3512 F8F0FC 29 FF 1F and #(SOBUFSIZ-1) ; circular queue
		966	3513 F8F0FF 85 70 sta obufhead+k
		967	3514 F8F101 ?done: CPU08
		968	3515 .MLIST
		969	3516 F8F101 E2 30 sep #(PMFLAG.OR.PXFLAG)
		970	3517 .LONGA off
		971	3518 .LONGI off
		972	3519 .MNLIST
		973	3520 F8F103 60 rts
		974	3521 F8F104 .ENDM
		975	3522
		976	3523 F8F104 int1sr:
		977	3524 F8F104 SPISR 1
		978	3525
		979	3526 .MLIST
		980	3527 [01] .IFZ 1
		981	3528 k .SET 0
		982	3529 SOBUFADDR .SET SPOUTBUFF
		983	3530 SIBUFADDR .SET SPINBUFF
		984	3531 [01] .ELSE
		985	3532 000004 k .SET 4
		986	3533 052000 SOBUFADDR .SET SPOUTBUFF2
		987	3534 058000 SIBUFADDR .SET SPINBUFF2
		988	3535 [00] .ENDIF
		989	3536
		990	3537 F8F104 AC 54 FD ldy .ABS.ACIAISR+k ; interrupt status reg. (clear bit 3,4,5)
		991	3538 F8F107 AD 55 FD lda .ABS.ACIACSR+k ; control status register
		992	3539 ;sty spisr+k ; save interrupt status reg.
		993	Tue Jul 17 11:11:08 2018 Page 17
		994
		995
		996
		997
		998	3540 F8F10A 85 5B sta spcsr+k ; save control status reg.
		999	3541 F8F10C 98 tya ; Y=status reg.
		1000	3542 F8F10D 4A lsr a ; test RDRF bit
		1001	3543 F8F10E 90 76 bcc ?lin ; go to test control lines
		1002	3544 F8F110 AE 57 FD ldx .ABS.ACIARDR+k ; fetch rx data (clear int. status bits 0,1,2)
		1003	3545 F8F113 24 63 bit spstat+k ; rx error pending?
		1004	3546 F8F115 30 6F bmi ?lin ; yes, discard received data & test ctr. lines
		1005	3547 F8F117 29 03 and #00000011B ; 1: overrun/frame error, 2: parity error
		1006	3548 F8F119 24 5B bit spcsr+k ; test control status reg. bit 7: FE
		1007	3549 F8F11B 10 04 bpl ?nof ; no framing error
		1008	3550 F8F11D 09 04 ora #00000100B ; set framing error bit...
		1009	3551 F8F11F 29 FE and #$FE ; ...and clear overrun error
		1010	3552 F8F121 C9 00 ?nof: cmp #0
		1011	3553 F8F123 F0 04 beq ?rxok ; no rx error
		1012	3554 F8F125 09 80 ora #10000000B ; set rx error bit
		1013	3555 F8F127 80 45 bra ?sst ; set stus reg. & discard received data
		1014	3556 F8F129 8A ?rxok: txa ; A=received data
		1015	3557 F8F12A INDEX16
		1016	3558 .MLIST
		1017	3559 F8F12A C2 10 rep #PXFLAG
		1018	3560 .LONGI on
		1019	3561 .MNLIST
		1020	3562 F8F12C A6 7A ldx ibufcnt+k ; count of bytes stored in input buffer
		1021	3563 F8F12E 24 62 bit spmode+k ; test if handshake is active
		1022	3564 F8F130 10 35 bpl ?chk ; bit 7=0 -> no handshake so check input buff.
		1023	3565 F8F132 70 14 bvs ?tst ; bit 6=1 -> hardware handshake
		1024	3566 F8F134 C9 11 cmp #SPXON ; received an XON control byte?
		1025	3567 F8F136 D0 06 bne ?xoff ; no, check if received an XOFF
		1026	3568 F8F138 A9 40 lda #$40 ; received an XON: clear local pause flag
		1027	3569 F8F13A 14 64 trb sppause+k ; bit 6=0 -> local pause off (resume tx)
		1028	3570 F8F13C 80 46 bra ?cnt ; discard received data
		1029	3571 F8F13E C9 13 ?xoff: cmp #SPXOFF ; received an XOFF control byte?
		1030	3572 F8F140 D0 06 bne ?tst ; no, check condition for remote pause
		1031	3573 F8F142 A9 40 lda #$40 ; set local pause flag
		1032	3574 F8F144 04 64 tsb sppause+k ; bit 6=1 -> local pause on (stop tx operation)
		1033	3575 F8F146 80 3C bra ?cnt ; discard received data
		1034	3576 F8F148 E4 84 ?tst: cpx icntmax+k ; check input buff. for remote pause condition
		1035	3577 F8F14A 90 26 bcc ?str ; below guard limit: store data
		1036	3578 F8F14C 24 64 bit sppause+k ; remote pause is already on ?
		1037	3579 F8F14E 30 17 bmi ?chk ; yes, so check input buffer
		1038	3580 F8F150 EB xba ; B = received data
		1039	3581 F8F151 24 62 bit spmode+k ; test handshake type
		1040	3582 F8F153 70 06 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=1
		1041	3583 F8F155 A9 13 lda #SPXOFF ; send an XOFF to remote terminal
		1042	3584 F8F157 85 5D sta spout+k ; XOFF sending deffered until TDRE is set
		1043	3585 F8F159 80 0B bra ?xba ; check input buffer
		1044	3586 F8F15B A5 5C ?rtsh: lda spfr+k ; hardware handshake...
		1045	3587 F8F15D 09 81 ora #10000001B ; ...set RTS=1
		1046	3588 F8F15F 8D 55 FD sta .ABS.ACIAFR+k ; update format register
		1047	3589 F8F162 A9 80 lda #$80 ; set remote pause
		1048	3590 F8F164 04 64 tsb sppause+k ; bit 7=1 -> remote pause on
		1049	3591 F8F166 EB ?xba: xba ; A = received data
		1050	3592 F8F167 E0 00 40 ?chk: cpx #SIBUFSIZ ; left room in input buffer?
		1051	3593 F8F16A 90 06 bcc ?str ; yes, store received byte
		1052	3594 F8F16C A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow
		1053	3595 F8F16E 85 63 ?sst: sta spstat+k ; set status register
		1054	3596 F8F170 80 12 bra ?cnt ; discard received data
		1055	Tue Jul 17 11:11:08 2018 Page 18
		1056
		1057
		1058
		1059
		1060	3597 F8F172 E8 ?str: inx ; now store received data
		1061	3598 F8F173 86 7A stx ibufcnt+k ; update bytes count
		1062	3599 F8F175 A6 6A ldx ibuftail+k ; pointer to rx tail queue
		1063	3600 F8F177 9F 00 80 05 sta >SIBUFADDR,x
		1064	3601 F8F17B E8 inx ; update tail pointer
		1065	3602 F8F17C CPU16
		1066	3603 .MLIST
		1067	3604 F8F17C C2 30 rep #(PMFLAG.OR.PXFLAG)
		1068	3605 .LONGA on
		1069	3606 .LONGI on
		1070	3607 .MNLIST
		1071	3608 F8F17E 8A txa
		1072	3609 F8F17F 29 FF 3F and #(SIBUFSIZ-1) ; circular queue
		1073	3610 F8F182 85 6A sta ibuftail+k
		1074	3611 F8F184 ?cnt: CPU08 ; continue...
		1075	3612 .MLIST
		1076	3613 F8F184 E2 30 sep #(PMFLAG.OR.PXFLAG)
		1077	3614 .LONGA off
		1078	3615 .LONGI off
		1079	3616 .MNLIST
		1080	3617 F8F186 A5 5B ?lin: lda spcsr+k ; get control lines status
		1081	3618 F8F188 29 3B and #00111011B ; mask lines level
		1082	3619 F8F18A 89 08 bit #00001000B ; check DSR line level
		1083	3620 F8F18C F0 02 beq ?lin2 ; DSR is low
		1084	3621 F8F18E 09 40 ora #01000000B ; DSR is high
		1085	3622 F8F190 0A ?lin2: asl a ; 7:DSR, 6:CTS, 5:DCD, 2:DTR, 1:RTS
		1086	3623 F8F191 85 5A sta splin+k ; save lines level
		1087	3624 ;tya
		1088	3625 F8F193 24 62 bit spmode+k ; test for active handshake
		1089	3626 F8F195 10 24 bpl ?cnt2 ; no handshake, so ignore CTS/DCD trans.
		1090	3627 F8F197 50 22 bvc ?cnt2 ; softw. handshake, so ignore CTS/DCD trans.
		1091	3628 ;bit #00001000B ; change state on DSR line?
		1092	3629 ;beq ?cts ; no, go to check CTS line
		1093	3630 ;ldx #00100000B ; remote disconnession flag
		1094	3631 ;lda #00001000B ; check DSR line level
		1095	3632 ;bit spcsr+k
		1096	3633 ;beq ?dsrl ; DSR line at low level
		1097	3634 ;txa ; remote disconnession
		1098	3635 ;tsb spstat+k ; set status register
		1099	3636 ;bra ?cts
		1100	3637 ;?dsrl: ;txa ; remote terminal ready
		1101	3638 ;trb spstat+k ; set status register
		1102	3639 ;?cts:
		1103	3640 F8F199 A5 62 lda spmode+k
		1104	3641 F8F19B 4A lsr a ; check if uplink handshake (RTS/DCD control)
		1105	3642 F8F19C 98 tya ; A=interrupt status reg.
		1106	3643 F8F19D B0 08 bcs ?dcd ; yes, so check DCD line (uplink cable)
		1107	3644 F8F19F 89 20 bit #00100000B ; change state on CTS line?
		1108	3645 F8F1A1 F0 19 beq ?chkt ; no, so check TDRE flag
		1109	3646 F8F1A3 A9 20 lda #00100000B ; check CTS line level
		1110	3647 F8F1A5 80 06 bra ?lvl
		1111	3648 F8F1A7 89 10 ?dcd: bit #00010000B ; change state on DCD line?
		1112	3649 F8F1A9 F0 11 beq ?chkt ; no, so check TDRE flag
		1113	3650 F8F1AB A9 10 lda #00010000B ; check DCD line level
		1114	3651 F8F1AD A2 40 ?lvl: ldx #$40 ; local pause flag
		1115	3652 F8F1AF 24 5B bit spcsr+k
		1116	3653 F8F1B1 F0 05 beq ?clp ; CTS (or DCD) = low so clear local pause
		1117	Tue Jul 17 11:11:08 2018 Page 19
		1118
		1119
		1120
		1121
		1122	3654 F8F1B3 8A txa ; CTS (or DCD) = high so set local pause
		1123	3655 F8F1B4 04 64 tsb sppause+k
		1124	3656 F8F1B6 80 03 bra ?cnt2
		1125	3657 F8F1B8 8A ?clp: txa
		1126	3658 F8F1B9 14 64 trb sppause+k
		1127	3659 F8F1BB 98 ?cnt2: tya
		1128	3660 F8F1BC 0A ?chkt: asl a ; check TDRE bit
		1129	3661 F8F1BD 10 11 bpl ?end ; TDRE=0: can't transmit at this time
		1130	3662 F8F1BF A5 5D lda spout+k ; pending an XON/XOFF sending?
		1131	3663 F8F1C1 F0 13 beq ?cklp ; no... check local pause flag
		1132	3664 F8F1C3 8D 57 FD sta .ABS.ACIATDR+k ; send XON/XOFF
		1133	3665 F8F1C6 64 5D stz spout+k ; clear XON/XOFF flag
		1134	3666 F8F1C8 C9 13 cmp #SPXOFF
		1135	3667 F8F1CA F0 05 beq ?srp ; sent an XOFF
		1136	3668 F8F1CC A9 80 lda #$80 ; sent an XON: clear remote pause flag
		1137	3669 F8F1CE 14 64 trb sppause+k ; bit 7 = 0 -> remote pause off
		1138	3670 F8F1D0 60 ?end: rts ; done
		1139	3671 F8F1D1 A9 80 ?srp: lda #$80 ; set remote pause flag
		1140	3672 F8F1D3 04 64 tsb sppause+k
		1141	3673 F8F1D5 60 rts
		1142	3674 F8F1D6 24 64 ?cklp: bit sppause+k ; local pause is set ?
		1143	3675 F8F1D8 70 F6 bvs ?end ; yes, no tx possible at this time
		1144	3676 ;bit spcsr+k ; check if remote terminal is ready
		1145	3677 ;bmi ?end ; not ready, skip tx
		1146	3678 F8F1DA INDEX16
		1147	3679 .MLIST
		1148	3680 F8F1DA C2 10 rep #PXFLAG
		1149	3681 .LONGI on
		1150	3682 .MNLIST
		1151	3683 F8F1DC A6 7C ldx obufcnt+k ; count of bytes in output buffer
		1152	3684 F8F1DE F0 15 beq ?done ; output buffer is empty: nothing to send
		1153	3685 F8F1E0 CA dex ; update count
		1154	3686 F8F1E1 86 7C stx obufcnt+k
		1155	3687 F8F1E3 A6 74 ldx obufhead+k ; pointer to head of out buffer
		1156	3688 F8F1E5 BF 00 20 05 lda >SOBUFADDR,x ; get data from output buffer
		1157	3689 F8F1E9 8D 57 FD sta .ABS.ACIATDR+k ; send data
		1158	3690 F8F1EC E8 inx ; update head pointer
		1159	3691 F8F1ED CPU16
		1160	3692 .MLIST
		1161	3693 F8F1ED C2 30 rep #(PMFLAG.OR.PXFLAG)
		1162	3694 .LONGA on
		1163	3695 .LONGI on
		1164	3696 .MNLIST
		1165	3697 F8F1EF 8A txa
		1166	3698 F8F1F0 29 FF 1F and #(SOBUFSIZ-1) ; circular queue
		1167	3699 F8F1F3 85 74 sta obufhead+k
		1168	3700 F8F1F5 ?done: CPU08
		1169	3701 .MLIST
		1170	3702 F8F1F5 E2 30 sep #(PMFLAG.OR.PXFLAG)
		1171	3703 .LONGA off
		1172	3704 .LONGI off
		1173	3705 .MNLIST
		1174	3706 F8F1F7 60 rts
		1175	3707 F8F1F8 .ENDM
		1176	3708
		1177	3709 F8F1F8
		1178	3710 ; gestione IRQ2 - VIA 0 (T1, CA2, CB2, CA1)
		1179	Tue Jul 17 11:11:08 2018 Page 20
		1180
		1181
		1182
		1183
		1184	3711 F8F1F8 int2sr:
		1185	3712 F8F1F8 AC 0D FD ldy VIA0+VIAIFR ; flag IFR VIA
		1186	3713 F8F1FB 10 48 bpl ?50 ; no irq da VIA
		1187	3714 F8F1FD 98 tya ; IFR
		1188	3715 F8F1FE 0A asl a ; N = bit 6 (T1IFRB)
		1189	3716 F8F1FF 10 1C bpl ?20 ; no T1 IRQ
		1190	3717 ;tay
		1191	3718 F8F201 ACC16 ; A,M -> 16 bit
		1192	3719 .MLIST
		1193	3720 F8F201 C2 20 rep #PMFLAG
		1194	3721 .LONGA on
		1195	3722 .MNLIST
		1196	3723 F8F203 E6 00 inc JiffyClk ; incrementa contatore clock 10ms
		1197	3724 F8F205 D0 02 bne ?02
		1198	3725 F8F207 E6 02 inc JiffyClk+2
		1199	3726 F8F209 ?02: ACC08 ; A,M -> 8 bit
		1200	3727 F8F209 E2 20 sep #PMFLAG
		1201	3728 .LONGA off
		1202	3729 .MNLIST
		1203	3730 F8F20B A2 03 ldx #SYSTMRCNT-1 ; System Timer (max. 2560ms)
		1204	3731 F8F20D 34 08 ?04: bit SysTMF,x ; timer attivo ?
		1205	3732 F8F20F 10 06 bpl ?05 ; no
		1206	3733 F8F211 D6 04 dec SysTmr,x ; update timer x
		1207	3734 F8F213 D0 02 bne ?05
		1208	3735 F8F215 74 08 stz SysTMF,x ; cancella timer
		1209	3736 F8F217 CA ?05: dex
		1210	3737 F8F218 10 F3 bpl ?04
		1211	3738 F8F21A AD 04 FD lda VIA0+VIAT1CL ; clear flag T1
		1212	3739 F8F21D 98 ?20: tya ; IFR
		1213	3740 F8F21E 4A lsr a ; C = CA2IFRB
		1214	3741 F8F21F 90 0B bcc ?30 ; no IRQ CA2 da controller tastiera
		1215	3742 F8F221 20 46 F2 jsr KbInt ; gestione IRQ tastiera
		1216	3743 F8F224 A9 01 lda #CA2IFRB ; azzera flag CA2
		1217	3744 F8F226 8D 0D FD sta VIA0+VIAIFR
		1218	3745 F8F229 8D 46 FD sta KBCLRIRQ ; azzera linea INT
		1219	3746 F8F22C 98 ?30: tya ; IFR
		1220	3747 F8F22D 29 08 and #CB2IFRB ; CB2-TMF0 abilitato ?
		1221	3748 F8F22F 2D 0E FD and VIA0+VIAIER ; e Timer motor spirato ?
		1222	3749 F8F232 F0 11 beq ?40 ; no
		1223	3750 F8F234 A9 10 lda #00010000B
		1224	3751 F8F236 14 46 trb fdcctl ; flag motor off
		1225	3752 F8F238 A9 0C lda #00001100B
		1226	3753 F8F23A 8D DA FD sta !FDCDOR ; enable controller, motor off
		1227	3754 F8F23D A9 08 lda #CB2IFRB ; disabilita CB2-TMF0
		1228	3755 F8F23F 8D 0E FD sta VIA0+VIAIER
		1229	3756 F8F242 8D 0D FD sta VIA0+VIAIFR ; clear flag CB2
		1230	3757 F8F245 ?40:
		1231	3758 F8F245 60 ?50: rts
		1232	3759 F8F246
		1233	3760 F8F246 KbInt:
		1234	3761 F8F246 F4 00 01 pea #DP01ADDR ; DP = pagina 1
		1235	3762 F8F249 2B pld
		1236	3763 F8F24A AE 40 FD ldx KBFR ; primo byte (flag)
		1237	3764 F8F24D 10 2E bpl ?20 ; bit 7 = 0 -> codice ASCII
		1238	3765 F8F24F 8A txa
		1239	3766 F8F250 29 B0 and #$B0 ; maschera 4 bit alti - ignora release (6)
		1240	3767 F8F252 C9 80 cmp #$80 ; codice FLAG ?
		1241	Tue Jul 17 11:11:08 2018 Page 21
		1242
		1243
		1244
		1245
		1246	3768 F8F254 D0 10 bne ?10 ; no
		1247	3769 F8F256 8A txa
		1248	3770 F8F257 29 03 and #$03 ; bit 7 e 6 di KbdShift
		1249	3771 F8F259 4A lsr a ; C = bit 6
		1250	3772 F8F25A 6A ror a ; C = bit 7
		1251	3773 F8F25B 6A ror a
		1252	3774 F8F25C 29 C0 and #$C0 ; maschera bit 7,6
		1253	3775 F8F25E 85 63 sta KbdShift
		1254	3776 F8F260 AD 41 FD lda KBFR+1 ; flag
		1255	3777 F8F263 85 64 sta KbdFlag
		1256	3778 F8F265 60 rts
		1257	3779 F8F266 C9 90 ?10: cmp #$90 ; toggle bit ?
		1258	3780 F8F268 D0 13 bne ?20 ; no
		1259	3781 F8F26A AD 41 FD lda KBFR+1 ; toggle bit
		1260	3782 F8F26D 85 65 sta KbdToggle
		1261	3783 F8F26F 29 20 and #SCROLLLOCKB ; test SCROLL LOCK BIT
		1262	3784 F8F271 08 php
		1263	3785 F8F272 A9 80 lda #$80 ; SCOLL LOCK bit di ScnScroll
		1264	3786 F8F274 28 plp
		1265	3787 F8F275 F0 03 beq ?12
		1266	3788 F8F277 04 75 tsb ScnScroll ; disabilita scroll
		1267	3789 F8F279 60 rts
		1268	3790 F8F27A 14 75 ?12: trb ScnScroll ; abilita scroll
		1269	3791 F8F27C 60 rts
		1270	3792 F8F27D A4 62 ?20: ldy KbdCnt ; test spazio nel buffer
		1271	3793 F8F27F C0 60 cpy #KBDBUFLEN
		1272	3794 F8F281 B0 28 bcs ?90 ; no room - scarta tasto
		1273	3795 F8F283 8A txa
		1274	3796 F8F284 89 10 bit #$10 ; test 4 bit bassi toggle
		1275	3797 F8F286 F0 0A beq ?30 ; no toggle
		1276	3798 F8F288 A9 0F lda #$0F ; azzera 4 bit bassi di KbdToggle
		1277	3799 F8F28A 14 65 trb KbdToggle
		1278	3800 F8F28C 8A txa
		1279	3801 F8F28D 29 0F and #$0F ; 4 bit bassi di KbdToggle
		1280	3802 F8F28F 04 65 tsb KbdToggle ; imposta 4 bit bassi di KbdToggle
		1281	3803 F8F291 8A txa
		1282	3804 ?30: ; inserisce codice tasto nel buffer
		1283	3805 F8F292 29 C0 and #$C0 ; bit 7 -> ASCII(0) oppure CONTROL(1)
		1284	3806 ; bit 6 -> MAKE(0) oppure RELEASE(1)
		1285	3807 F8F294 A6 60 ldx KbdITail ; indice coda buffer
		1286	3808 F8F296 95 00 sta KbdBuf,x ; inserisce flag tasto
		1287	3809 F8F298 E8 inx
		1288	3810 F8F299 AD 41 FD lda KBFR+1 ; codice tasto
		1289	3811 F8F29C 95 00 sta KbdBuf,x
		1290	3812 F8F29E E8 inx
		1291	3813 F8F29F C8 iny ; aggiorna contatore bytes
		1292	3814 F8F2A0 C8 iny
		1293	3815 F8F2A1 84 62 sty KbdCnt
		1294	3816 F8F2A3 E0 60 cpx #KBDBUFLEN ; test coda piena
		1295	3817 F8F2A5 90 02 bcc ?40 ; no
		1296	3818 F8F2A7 A2 00 ldx #0 ; coda circolare
		1297	3819 F8F2A9 86 60 ?40: stx KbdITail ; aggiorna ptr. coda buffer
		1298	3820 F8F2AB 60 ?90: rts
		1299	3821
		1300	3822
		1301	3823 ; ISR for VIA2/VIA3
		1302	3824 ; VIA3
		1303	Tue Jul 17 11:11:08 2018 Page 22
		1304
		1305
		1306
		1307
		1308	3825 ; CB2 (neg. edge) : ch375/376 interrupt line
		1309	3826 ;
		1310	3827 ; VIA2
		1311	3828 ; CA1 (negative edge) : interrupt from pic usb host
		1312	3829 ; CA2 (negative edge) : interrupt from UM245R (usb slave)
		1313	3830 ; CB1
		1314	3831 ; CB2 (pos/neg. edge) : acia CTS sensing
		1315	3832 ; T1 free-run interrupt
		1316	3833 F8F2AC int3sr:
		1317	3834 .EXTERN usbdskon, umgetcmd
		1318	3835
		1319	3836 F8F2AC AD CD FD lda !VIA3+VIAIFR
		1320	3837 F8F2AF 10 25 bpl ?via2
		1321	3838 F8F2B1 8D CD FD sta !VIA3+VIAIFR ; clear interrupt flags
		1322	3839 F8F2B4 89 08 bit #CB2IFRB
		1323	3840 F8F2B6 F0 1E beq ?via2 ; no usb interrupt
		1324	3841 F8F2B8 A9 22 lda #CMD_GET_STATUS
		1325	3842 F8F2BA 8D D1 FD sta usb0cmd
		1326	3843 F8F2BD EA nop ; 2uS
		1327	3844 F8F2BE EA nop
		1328	3845 F8F2BF EA nop
		1329	3846 F8F2C0 EA nop
		1330	3847 F8F2C1 AD D0 FD lda usb0dat
		1331	3848 F8F2C4 C9 16 cmp #USB_INT_DISCONNECT
		1332	3849 F8F2C6 D0 06 bne ?nxt
		1333	3850 F8F2C8 A9 7F lda #$7F ; clear all status bits but not bit 7
		1334	3851 F8F2CA 14 43 trb usb0st
		1335	3852 F8F2CC 80 08 bra ?via2 ; check via2
		1336	3853 F8F2CE C9 15 ?nxt: cmp #USB_INT_CONNECT
		1337	3854 F8F2D0 D0 04 bne ?via2
		1338	3855 F8F2D2 22 53 B2 F8 jsl usbdskon
		1339	3856 F8F2D6 F4 00 05 ?via2: pea #DP05ADDR
		1340	3857 F8F2D9 2B pld
		1341	3858 F8F2DA AD 1D FC lda !VIA2+VIAIFR
		1342	3859 F8F2DD 30 01 bmi ?go
		1343	3860 F8F2DF 60 rts ; no interrupt from VIA3
		1344	3861 F8F2E0 2D 1E FC ?go: and !VIA2+VIAIER ; mask off disbled flags
		1345	3862 F8F2E3 4A lsr a ; <0>: CA2 int. ?
		1346	3863 F8F2E4 90 4B bcc ?ca1 ; no, test bit <1>
		1347	3864 F8F2E6
		1348	3865 ; /RXF line from UM245R request service
		1349	3866 ; if UM245 is already plugged to usb host then have data on FIFO
		1350	3867 ; if UM245 was previously unplugged then it assert some pulses
		1351	3868 ; on /RXF line with dummy data: FF, 1D, 3D, 3D or FF, 3D, 3D
		1352	3869 ; last two bytes must be 3D 3D
		1353	3870 ;
		1354	3871 F8F2E6 A8 tay ; save flags
		1355	3872 F8F2E7 A2 01 ldx #CA2IFRB ; clear CA2 flag
		1356	3873 F8F2E9 8E 1D FC stx .ABS.VIA2+VIAIFR
		1357	3874 F8F2EC 24 00 bit usbslv ; UM245 already plugged to usb host?
		1358	3875 F8F2EE 30 11 bmi ?umrx ; yes so this is incoming data
		1359	3876 F8F2F0
		1360	3877 ; sensing a plug in
		1361	3878 ;
		1362	3879 F8F2F0 AE 2F FC ldx .ABS.UM245R ; read UM245 port and discard data
		1363	3880 F8F2F3 24 00 bit usbslv ; first transition?
		1364	3881 F8F2F5 70 3A bvs ?ca1 ; no
		1365	Tue Jul 17 11:11:08 2018 Page 23
		1366
		1367
		1368
		1369
		1370	3882 F8F2F7 A2 40 ldx #$40 ; set usb host pending plug-in flag
		1371	3883 F8F2F9 86 00 stx usbslv
		1372	3884 F8F2FB A2 28 ldx #40 ; 600ms timeout
		1373	3885 F8F2FD 86 02 stx usbcnt1
		1374	3886 ;tya ; restore flags
		1375	3887 F8F2FF 80 30 bra ?ca1 ; go to test CA1 flag
		1376	3888
		1377	3889 ?umrx: ; /RXF line low mean data is available from UM245 FIFO
		1378	3890 ; expect 8 bytes
		1379	3891 F8F301 A2 00 ldx #0
		1380	3892 F8F303 A9 01 ?umrxl: lda #CA2IFRB ; clear CA2 flag
		1381	3893 F8F305 8D 1D FC sta !VIA2+VIAIFR
		1382	3894 F8F308 AD 2F FC lda !UM245R
		1383	3895 F8F30B 95 03 sta usbbuf,x
		1384	3896 F8F30D E8 inx
		1385	3897 F8F30E E0 08 cpx #8
		1386	3898 F8F310 B0 1A bcs ?umrx3
		1387	3899 F8F312 9C 18 FC stz VIA2+VIAT2CL
		1388	3900 F8F315 9C 19 FC stz VIA2+VIAT2CH
		1389	3901 F8F318 A9 01 ?umrx2: lda #CA2IFRB ; check CA2 flag
		1390	3902 F8F31A 2C 1D FC bit VIA2+VIAIFR
		1391	3903 F8F31D D0 E4 bne ?umrxl
		1392	3904 F8F31F A9 20 lda #T2IFRB
		1393	3905 F8F321 2C 1D FC bit VIA2+VIAIFR
		1394	3906 F8F324 F0 F2 beq ?umrx2
		1395	3907 F8F326 A9 40 lda #$40
		1396	3908 F8F328 14 01 trb usbum
		1397	3909 F8F32A 80 04 bra ?ca1r
		1398	3910
		1399	3911 ;?umrx3: bit usbum
		1400	3912 ; bmi ?setu ; already connected
		1401	3913 F8F32C
		1402	3914 ; check connession request
		1403	3915 ; dex
		1404	3916 ;?umrx4: lda usbbuf,x
		1405	3917 ; cmp .ABS.?usbt,x
		1406	3918 ; beq ?umrx5
		1407	3919 ; lda #$55
		1408	3920 ; sta !UM245R
		1409	3921 ; bra ?ca1r
		1410	3922 ;?umrx5: dex
		1411	3923 ; bpl ?umrx4
		1412	3924 ; lda #$AA
		1413	3925 ; sta !UM245R
		1414	3926 ; lda #$80
		1415	3927 ; tsb usbum
		1416	3928 ; bra ?ca1r
		1417	3929 ;?setu: lda #$40
		1418	3930
		1419	3931 F8F32C A9 40 ?umrx3: lda #$40
		1420	3932 F8F32E 04 01 tsb usbum ; set bit <6>: fifo data available
		1421	3933 F8F330 98 ?ca1r: tya ; restore flag
		1422	3934 F8F331
		1423	3935 F8F331 4A ?ca1: lsr a ; <1>: CA1 int.?
		1424	3936 F8F332 90 0B bcc ?cb2 ; no, test bit <3>
		1425	3937 F8F334
		1426	3938 ; this is pic that request a service (usb host)
		1427	Tue Jul 17 11:11:08 2018 Page 24
		1428
		1429
		1430
		1431
		1432	3939 ;
		1433	3940 F8F334 A8 tay ; save flags
		1434	3941 F8F335 A9 02 lda #CA1IFRB ; clear CA1 flag
		1435	3942 F8F337 8D 1D FC sta !VIA2+VIAIFR
		1436	3943 F8F33A A9 80 lda #$80
		1437	3944 F8F33C 04 0D tsb usbmst ; set usb master flag request
		1438	3945 F8F33E 98 tya ; restore flag
		1439	3946 F8F33F
		1440	3947 F8F33F 4A ?cb2: lsr a ; discard bit <2>
		1441	3948 F8F340 4A lsr a ; <3>: CB2 int.?
		1442	3949 F8F341 90 36 bcc ?cb1 ; no, test bit <4>
		1443	3950
		1444	3951 ; /CTS line of R65C51 changed state (transition)
		1445	3952 ;
		1446	3953 F8F343 A8 tay ; save flags
		1447	3954 F8F344 A9 08 lda #CB2IFRB ; clear CB2 flag
		1448	3955 F8F346 8D 1D FC sta !VIA2+VIAIFR
		1449	3956 F8F349 A9 01 lda #$01
		1450	3957 F8F34B 04 16 tsb splin3 ; transition on /CST line
		1451	3958 F8F34D A2 40 ldx #$40
		1452	3959 F8F34F A9 08 lda #00001000B ; check /CTS line level: PA<3>
		1453	3960 F8F351 2C 1F FC bit !VIA2+VIAPRANH
		1454	3961 F8F354 F0 0A beq ?ctsl ; was a negative transition: /CTS is low
		1455	3962
		1456	3963 ; positive edge transition on /CTS line: /CTS line is high
		1457	3964 ;
		1458	3965 F8F356 8A txa
		1459	3966 F8F357 1C 1C FC trb !VIA2+VIAPCR ; next time sense a negative edge on /CTS line
		1460	3967 F8F35A A9 80 lda #$80
		1461	3968 F8F35C 04 16 tsb splin3 ; now /CTS line is high
		1462	3969 F8F35E 80 09 bra ?hsk ; check handshake mode for R65C51 (CF=1 here)
		1463	3970 F8F360
		1464	3971 ?ctsl: ; negative edge transition on /CTS line: /CTS line is low
		1465	3972 ;
		1466	3973 F8F360 8A txa
		1467	3974 F8F361 0C 1C FC tsb !VIA2+VIAPCR ; next time sense a positive edge on /CTS line
		1468	3975 F8F364 A9 80 lda #$80
		1469	3976 F8F366 14 16 trb splin3 ; now /CTS line is low
		1470	3977 F8F368 18 clc ; CF=0: resume TX
		1471	3978
		1472	3979 ?hsk: ; if 65C51 is in hardware handshake mode then must handle
		1473	3980 ; local pause flag and TX interrupt state
		1474	3981 ;
		1475	3982 F8F369 24 15 bit spmode3 ; test for active handshake
		1476	3983 F8F36B 10 0B bpl ?cnt ; no handshake, so ignore CTS trans.
		1477	3984 F8F36D 50 09 bvc ?cnt ; softw. handshake, so ignore CTS trans.
		1478	3985 F8F36F 8A txa
		1479	3986 F8F370 90 04 bcc ?clp ; /CTS low clear local pause and resume TX
		1480	3987 F8F372 04 17 tsb sppause3 ; /CTS high set local pause and stop TX
		1481	3988 F8F374 80 02 bra ?cnt
		1482	3989 F8F376 14 17 ?clp: trb sppause3
		1483	3990 F8F378 98 ?cnt: tya ; restore flag
		1484	3991
		1485	3992 F8F379 4A ?cb1: lsr a ; <4>: CB1 int.?
		1486	3993 F8F37A 90 03 bcc ?t1 ; no, test bit <6>
		1487	3994 F8F37C AE 10 FC ldx .ABS.VIA2+VIAPRB
		1488	3995 F8F37F
		1489	Tue Jul 17 11:11:08 2018 Page 25
		1490
		1491
		1492
		1493
		1494	3996 F8F37F 4A ?t1: lsr a ; discadrd bit <5>
		1495	3997 F8F380 4A lsr a ; <6>: T1 int.?
		1496	3998 F8F381 90 47 bcc ?end ; no
		1497	3999
		1498	4000 ; T1 used for check UM245 /TXE line: if this line is high
		1499	4001 ; for long time this mean that usb host was unplugged,
		1500	4002 ; and used for check /DSR line when ACIA interrupt is disabled
		1501	4003 ; T1 timeout = 15ms
		1502	4004 F8F383 AD 14 FC lda !VIA2+VIAT1CL ; clear T1 flag
		1503	4005 F8F386 24 00 bit usbslv ; plug-in pending?
		1504	4006 F8F388 50 08 bvc ?t2 ; no
		1505	4007 F8F38A C6 02 dec usbcnt1 ; update counter
		1506	4008 F8F38C D0 04 bne ?t2 ; timeout not expired
		1507	4009 F8F38E A9 80 lda #$80
		1508	4010 F8F390 85 00 sta usbslv ; assume UM245 plugged-in
		1509	4011 F8F392 AD 2A FC ?t2: lda !ACIACMD
		1510	4012 F8F395 4A lsr a ; check bit <0>
		1511	4013 F8F396 B0 0F bcs ?usb ; ACIA interrupt is enabled
		1512	4014 F8F398 AD 29 FC lda !ACIASR ; is safe to read ACIA status now
		1513	4015 F8F39B 29 40 and #01000000B ; mask off all bits but /DSR
		1514	4016 F8F39D F0 04 beq ?dsr ; clear /DSR flag
		1515	4017 F8F39F 04 16 tsb splin3 ; set /DSR flag
		1516	4018 F8F3A1 80 04 bra ?usb
		1517	4019 F8F3A3 A9 40 ?dsr: lda #$40
		1518	4020 F8F3A5 14 16 trb splin3
		1519	4021 F8F3A7 24 00 ?usb: bit usbslv
		1520	4022 F8F3A9 10 15 bpl ?txel ; usb unplugged: nothing to do
		1521	4023 F8F3AB 2C 1F FC bit !VIA2+VIAPRANH ; check /TXE
		1522	4024 F8F3AE 50 10 bvc ?txel ; /TXE is low: clear timeout
		1523	4025 F8F3B0 A5 0B lda usbtim ; timeout started?
		1524	4026 F8F3B2 D0 06 bne ?dec ; yes, update counter
		1525	4027 F8F3B4 A9 2C lda #44 ; set 660ms (44 x 15) timeout
		1526	4028 F8F3B6 85 0B sta usbtim
		1527	4029 F8F3B8 80 10 bra ?end
		1528	4030 F8F3BA C6 0B ?dec: dec usbtim ; update counter
		1529	4031 F8F3BC D0 0C bne ?end ; no timeout
		1530	4032 F8F3BE 64 00 stz usbslv ; assume cable unplugged
		1531	4033 F8F3C0 64 0B ?txel: stz usbtim ; clear any pending timeout
		1532	4034 F8F3C2
		1533	4035 ;?umrx: ldx usbcnt
		1534	4036 ;?lp1: lda !VIA2+VIAPRA ; check /RXF line
		1535	4037 ; cmp !VIA2+VIAPRA
		1536	4038 ; bne ?lp1
		1537	4039 ; tay
		1538	4040 ; asl a
		1539	4041 ; bcs ?xx
		1540	4042 ; lda !UM245R ; read um245 port
		1541	4043 ; sta !$8000,x
		1542	4044 ; tya
		1543	4045 ; sta !$8100,x
		1544	4046 ; inx
		1545	4047 ;?xx: stx usbcnt
		1546	4048
		1547	4049 F8F3C2 24 01 bit usbum
		1548	4050 F8F3C4 50 04 bvc ?end
		1549	4051 F8F3C6 22 5E 0E F8 jsl umgetcmd
		1550	4052 F8F3CA ?end:
		1551	Tue Jul 17 11:11:08 2018 Page 26
		1552
		1553
		1554
		1555
		1556	4053 F8F3CA 60 rts
		1557	4054
		1558	4055 F8F3CB 87 E9 5D 93 B7 ?usbt: .DB $87, $E9, $5D, $93, $B7, $57, $7D, $3B
		1559	57 7D 3B
		1560	4056
		1561	4057 ; serial test board interrupt from 16C550 & 65C51
		1562	4058 F8F3D3 int4sr:
		1563	4059 F8F3D3 F4 00 05 pea #DP05ADDR
		1564	4060 F8F3D6 2B pld
		1565	4061 F8F3D7 AD 29 FC lda !ACIASR
		1566	4062 F8F3DA 30 03 bmi ?acia
		1567	4063 F8F3DC 4C B8 F4 jmp uartisr ; 16C550 interrupt?
		1568	4064 F8F3DF 89 08 ?acia: bit #ACIARDRF ; rx data?
		1569	4065 F8F3E1 F0 6F beq ?lin ; no, check lines
		1570	4066 F8F3E3 A8 tay ; Y = status
		1571	4067 F8F3E4 AE 28 FC ldx .ABS.ACIADR ; X = received data
		1572	4068 F8F3E7 29 07 and #00000111B ; any rx error pending?
		1573	4069 F8F3E9 F0 0B beq ?rx ; no
		1574	4070 F8F3EB 0A asl a ; translate overrun (bit 3) to bit 0
		1575	4071 F8F3EC 89 08 bit #00001000B ; test overrun
		1576	4072 F8F3EE F0 02 beq $+4 ; skip next instruction if not overrun
		1577	4073 F8F3F0 09 01 ora #$01 ; overrun bit (bit<0>)
		1578	4074 F8F3F2 09 80 ora #$80 ; set x error bit
		1579	4075 F8F3F4 80 43 bra ?sst ; set status reg. & discard received data
		1580	4076 F8F3F6 8A ?rx: txa ; A = received data
		1581	4077 F8F3F7 INDEX16
		1582	4078 F8F3F7 C2 10 rep #PXFLAG
		1583	4079 .LONGI on
		1584	4080 .MNLIST
		1585	4081 F8F3F9 A6 23 ldx ibufcnt3 ; count of bytes stored in input queue
		1586	4082 F8F3FB 24 15 bit spmode3 ; test for active handshake
		1587	4083 F8F3FD 10 33 bpl ?chk ; no handshake: goto to check input queue
		1588	4084 F8F3FF 70 14 bvs ?tst ; hardware handshake (check queue overflow)
		1589	4085 F8F401 C9 11 cmp #SPXON ; received an XON control byte?
		1590	4086 F8F403 D0 06 bne ?xoff ; no, check if received an XOFF
		1591	4087 F8F405 A9 40 lda #$40 ; clear local pause flag
		1592	4088 F8F407 14 17 trb sppause3 ; bit<6> = 0 -> local pause off (resume tx)
		1593	4089 F8F409 80 44 bra ?cnt ; discard received data
		1594	4090 F8F40B C9 13 ?xoff: cmp #SPXOFF ; received an XOFF control byte?
		1595	4091 F8F40D D0 06 bne ?tst ; no, so check queue overflow
		1596	4092 F8F40F A9 40 lda #$40 ; set local pause flag
		1597	4093 F8F411 04 17 tsb sppause3 ; bit<6> = 1 -> local pause on (stop tx)
		1598	4094 F8F413 80 3A bra ?cnt ; discard received data
		1599	4095 F8F415 E4 29 ?tst: cpx icntmax3 ; check input buff. for remote pause condition
		1600	4096 F8F417 90 24 bcc ?sto ; below guard limit: store data
		1601	4097 F8F419 24 17 bit sppause3 ; remote pause is already on ?
		1602	4098 F8F41B 30 15 bmi ?chk ; yes, so check input buffer
		1603	4099 F8F41D EB xba ; B = received data
		1604	4100 F8F41E 24 15 bit spmode3 ; test handshake type
		1605	4101 F8F420 70 06 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=1
		1606	4102 F8F422 A9 13 lda #SPXOFF ; send an XOFF to remote terminal
		1607	4103 F8F424 85 18 sta spout3 ; XOFF sending deffered until TDRE is set
		1608	4104 F8F426 80 09 bra ?xba ; check input buffer
		1609	4105 F8F428 A9 04 ?rtsh: lda #$04 ; hardware handshake...
		1610	4106 F8F42A 0C 1F FC tsb !VIA2+VIAPRANH ; ...set RTS=1
		1611	4107 F8F42D A9 80 lda #$80 ; set remote pause
		1612	4108 F8F42F 04 17 tsb sppause3 ; bit 7=1 -> remote pause on
		1613	Tue Jul 17 11:11:08 2018 Page 27
		1614
		1615
		1616
		1617
		1618	4109 F8F431 EB ?xba: xba ; A = received data
		1619	4110 F8F432 E0 00 10 ?chk: cpx #SIBUFSIZ3 ; left room in input buffer?
		1620	4111 F8F435 90 06 bcc ?sto ; yes, store received byte
		1621	4112 F8F437 A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow
		1622	4113 F8F439 85 19 ?sst: sta spstat3 ; set status register
		1623	4114 F8F43B 80 12 bra ?cnt ; discard received data
		1624	4115 F8F43D E8 ?sto: inx ; now store received data
		1625	4116 F8F43E 86 23 stx ibufcnt3 ; update bytes count
		1626	4117 F8F440 A6 1B ldx ibuftail3 ; pointer to rx tail queue
		1627	4118 F8F442 9F 00 D0 05 sta >SIBUFADDR3,x
		1628	4119 F8F446 E8 inx ; update tail pointer
		1629	4120 F8F447 CPU16
		1630	4121 F8F447 C2 30 rep #(PMFLAG.OR.PXFLAG)
		1631	4122 .LONGA on
		1632	4123 .LONGI on
		1633	4124 .MNLIST
		1634	4125 .MLIST
		1635	4126 F8F449 8A txa
		1636	4127 F8F44A 29 FF 0F and #(SIBUFSIZ3-1) ; circular queue
		1637	4128 F8F44D 85 1B sta ibuftail3
		1638	4129 F8F44F ?cnt: CPU08 ; continue...
		1639	4130 .MLIST
		1640	4131 F8F44F E2 30 sep #(PMFLAG.OR.PXFLAG)
		1641	4132 .LONGA off
		1642	4133 .LONGI off
		1643	4134 .MNLIST
		1644	4135 F8F451 98 tya ; A = acia status
		1645	4136 F8F452 A8 ?lin: tay
		1646	4137 F8F453 29 40 and #01000000B ; mask off all bits but /DSR
		1647	4138 F8F455 F0 04 beq ?dsr ; clear /DSR flag
		1648	4139 F8F457 04 16 tsb splin3 ; set /DSR flag
		1649	4140 F8F459 80 04 bra ?cnt2
		1650	4141 F8F45B A9 40 ?dsr: lda #$40
		1651	4142 F8F45D 14 16 trb splin3
		1652	4143 F8F45F 98 ?cnt2: tya
		1653	4144 F8F460 89 10 bit #ACIATDRE ; TX reg. empty?
		1654	4145 F8F462 F0 23 beq ?end ; no
		1655	4146 F8F464 A6 18 ldx spout3 ; pending an XON/XOFF sending?
		1656	4147 F8F466 F0 23 beq ?cklp ; no... check local pause flag
		1657	4148 F8F468
		1658	4149 ; if send an XON then we will re-enable tx interrupt
		1659	4150 ; else we will disable tx interrupt
		1660	4151 ;
		1661	4152 F8F468 A9 0C lda #00001100B ; disable tx for now (is safe)
		1662	4153 F8F46A 1C 2A FC trb !ACIACMD
		1663	4154 F8F46D E0 11 cpx #SPXON
		1664	4155 F8F46F D0 04 bne ?di
		1665	4156 F8F471 A9 04 lda #00000100B ; re-enable tx interrupt
		1666	4157 F8F473 80 02 bra ?cmd
		1667	4158 F8F475 A9 08 ?di: lda #00001000B ; disable tx interrupt
		1668	4159 F8F477 0C 2A FC ?cmd: tsb !ACIACMD
		1669	4160 F8F47A 8E 28 FC stx .ABS.ACIADR ; send XON/XOFF
		1670	4161 F8F47D 64 18 stz spout3 ; clear XON/XOFF flag
		1671	4162 F8F47F A9 80 lda #$80 ; remote pause flag
		1672	4163 F8F481 E0 13 cpx #SPXOFF
		1673	4164 F8F483 F0 03 beq ?srp ; sent an XOFF: set remote pause flag
		1674	4165 F8F485 14 17 trb sppause3 ; sent an XON: clear remote pause flag
		1675	Tue Jul 17 11:11:08 2018 Page 28
		1676
		1677
		1678
		1679
		1680	4166 F8F487 60 ?end: rts ; done
		1681	4167 F8F488 04 17 ?srp: tsb sppause3 ; set remote pause flag
		1682	4168 F8F48A 60 rts
		1683	4169 F8F48B 24 17 ?cklp: bit sppause3 ; local pause is set ?
		1684	4170 F8F48D 70 06 bvs ?off ; yes, no tx possible at this time
		1685	4171 F8F48F INDEX16
		1686	4172 F8F48F C2 10 rep #PXFLAG
		1687	4173 .LONGI on
		1688	4174 .MNLIST
		1689	4175 F8F491 A6 25 ldx obufcnt3 ; count of bytes in output buffer
		1690	4176 F8F493 D0 0C bne ?snd ; output buffer inot empty: send next byte
		1691	4177 F8F495 A9 0C ?off: lda #00001100B ; disable TX interrupt for avoid cont. int.
		1692	4178 F8F497 1C 2A FC trb !ACIACMD
		1693	4179 F8F49A A9 08 lda #00001000B
		1694	4180 F8F49C 0C 2A FC tsb !ACIACMD
		1695	4181 F8F49F 80 15 bra ?done
		1696	4182 F8F4A1 CA ?snd: dex ; update count
		1697	4183 F8F4A2 86 25 stx obufcnt3
		1698	4184 F8F4A4 A6 21 ldx obufhead3 ; pointer to head of out buffer
		1699	4185 F8F4A6 BF 00 C0 05 lda >SOBUFADDR3,x ; get data from output buffer
		1700	4186 F8F4AA 8D 28 FC sta .ABS.ACIADR ; send data
		1701	4187 F8F4AD E8 inx ; update head pointer
		1702	4188 F8F4AE CPU16
		1703	4189 F8F4AE C2 30 rep #(PMFLAG.OR.PXFLAG)
		1704	4190 .LONGA on
		1705	4191 .LONGI on
		1706	4192 .MNLIST
		1707	4193 F8F4B0 8A txa
		1708	4194 F8F4B1 29 FF 0F and #(SOBUFSIZ3-1) ; circular queue
		1709	4195 F8F4B4 85 21 sta obufhead3
		1710	4196 F8F4B6 ?done: CPU08
		1711	4197 F8F4B6 E2 30 sep #(PMFLAG.OR.PXFLAG)
		1712	4198 .LONGA off
		1713	4199 .LONGI off
		1714	4200 .MNLIST
		1715	4201 ;rts
		1716	4202
		1717	4203 ; 16C550 interrupt
		1718	4204 ; ISR routine (prologue and epilogue code for context switching not showed here)
		1719	4205 ; handle 16C550 interrupt
		1720	4206 ; WARNING: assume DBR = 0 and DP saved by interrupt handler prologue code
		1721	4207 F8F4B8 uartisr:
		1722	4208 F8F4B8 AD 22 FC lda !UART_IIR
		1723	4209 F8F4BB 85 43 sta uartiir ; save for late check FIFO enabled
		1724	4210 F8F4BD 4A lsr a ; if bit <0> = 1 no interrupt
		1725	4211 F8F4BE 90 01 bcc $+3 ; interrupt pending
		1726	4212 F8F4C0 60 rts
		1727	4213 F8F4C1 29 03 and #0000011B ; mask on priority code
		1728	4214 F8F4C3 0A asl a
		1729	4215 F8F4C4 AA tax
		1730	4216 ; ldy #40
		1731	4217 ;?00: dey
		1732	4218 ; bne ?00
		1733	4219 ; RX timeout interrupt and RX data available interrupt use the same routine
		1734	4220 F8F4C5 7C C8 F4 jmp (?uarttbl,x) ; jump to right routine
		1735	4221
		1736	4222 F8F4C8 ?uarttbl:
		1737	Tue Jul 17 11:11:08 2018 Page 29
		1738
		1739
		1740
		1741
		1742	4223 F8F4C8 D5F4 DAF4 DFF4 .DW ?msr, ?tx, ?rx, ?lsr
		1743	D0F4
		1744	4224
		1745	4225 F8F4D0 20 5A F5 ?lsr: jsr uartilsr
		1746	4226 ;rts
		1747	4227 F8F4D3 80 E3 bra uartisr ; check again interrupt (was a test)
		1748	4228 F8F4D5
		1749	4229 F8F4D5 20 E4 F4 ?msr: jsr uartmsr ; MSR: modem status register
		1750	4230 ;rts
		1751	4231 F8F4D8 80 DE bra uartisr ; check again iterrupt
		1752	4232 F8F4DA
		1753	4233 F8F4DA 20 15 F5 ?tx: jsr uarttx ; TX FIFO or THR is empty
		1754	4234 ;rts
		1755	4235 F8F4DD 80 D9 bra uartisr ; check again interrupt
		1756	4236
		1757	4237 F8F4DF 20 7A F5 ?rx: jsr uartrx ; data available in RX FIFO or RHR
		1758	4238 ;rts
		1759	4239 F8F4E2 80 D4 bra uartisr ; check again interrupt
		1760	4240
		1761	4241 ; this interrupt is raised when one of the modem lines change state
		1762	4242 ; here just DSR and CTS are used: DSR for signaling remote disconnession,
		1763	4243 ; CTS for hardware handshake (put local TX in pause)
		1764	4244 F8F4E4 uartmsr:
		1765	4245 F8F4E4 AD 26 FC lda !UART_MSR ; clear interrupt
		1766	4246 F8F4E7 AA tax
		1767	4247 F8F4E8 0A asl a
		1768	4248 F8F4E9 0A asl a ; <7>: /DSR, <6>: /CTS
		1769	4249 F8F4EA 49 C0 eor #$C0
		1770	4250 F8F4EC 85 2C sta splin4 ; update line status
		1771	4251 F8F4EE 24 2B bit spmode4
		1772	4252 F8F4F0 10 22 bpl ?end ; no handshake: ignore line changes
		1773	4253 F8F4F2 A8 tay
		1774	4254 F8F4F3 10 04 bpl ?cts ; /DSR is low, check /CTS
		1775	4255 F8F4F5 A9 A0 lda #$A0 ; /DSR is high
		1776	4256 F8F4F7 04 2F tsb spstat4 ; remote terminal disconnected
		1777	4257 F8F4F9 8A ?cts: txa
		1778	4258 F8F4FA 4A lsr a ; check /CTS transition
		1779	4259 F8F4FB 90 17 bcc ?end ; no /CTS transition
		1780	4260 F8F4FD A2 40 ldx #$40 ; local pause flag
		1781	4261 F8F4FF 98 tya
		1782	4262 F8F500 0A asl a
		1783	4263 F8F501 10 09 bpl ?clp ; transition /CTS high->low: clear local pause
		1784	4264 F8F503 8A txa
		1785	4265 F8F504 04 2D tsb sppause4 ; /CTS high -> set local pause
		1786	4266 F8F506 A9 02 lda #00000010B ; disable TX interrupt
		1787	4267 F8F508 1C 21 FC trb !UART_IER
		1788	4268 F8F50B 60 rts
		1789	4269 F8F50C 8A ?clp: txa
		1790	4270 F8F50D 14 2D trb sppause4 ; /CTS low -> clear local pause
		1791	4271 F8F50F A9 02 lda #00000010B ; enable TX interrupt
		1792	4272 F8F511 0C 21 FC tsb !UART_IER
		1793	4273 F8F514 60 ?end: rts
		1794	4274
		1795	4275 ; this interrupt is raised either when THR is empty
		1796	4276 ; or when TX FIFO is empty
		1797	4277 F8F515 uarttx:
		1798	4278 F8F515 A9 02 lda #00000010B ; disable TX interrupt
		1799	Tue Jul 17 11:11:08 2018 Page 30
		1800
		1801
		1802
		1803
		1804	4279 F8F517 1C 21 FC trb !UART_IER
		1805	4280 F8F51A 24 2D bit sppause4 ; local pause is set ?
		1806	4281 F8F51C 70 39 bvs ?done ; yes, no tx possible at this time
		1807	4282 F8F51E INDEX16
		1808	4283 F8F51E C2 10 rep #PXFLAG
		1809	4284 .LONGI on
		1810	4285 .MNLIST
		1811	4286 F8F520 A4 3B ldy obufcnt4 ; count of bytes in output buffer
		1812	4287 F8F522 F0 33 beq ?done ; nothing to send at this time
		1813	4288 F8F524 A6 35 ldx obuftail4 ; pointer to tail of out buffer
		1814	4289 ;lda spcnt4 ; set the bytes count
		1815	4290 F8F526 A9 10 lda #16 ; set the bytes count
		1816	4291 F8F528 85 30 sta sptmp4
		1817	4292 F8F52A BF 00 00 06 ?txl: lda >SOBUFADDR4,x ; get data from the tail of output buffer
		1818	4293 F8F52E 8D 27 FC sta !UART_SCP
		1819	4294 F8F531 EA nop
		1820	4295 F8F532 EA nop
		1821	4296 F8F533 EA nop
		1822	4297 F8F534 EA nop
		1823	4298 F8F535 8D 27 FC sta !UART_SCP
		1824	4299 F8F538 EA nop
		1825	4300 F8F539 EA nop
		1826	4301 F8F53A EA nop
		1827	4302 F8F53B EA nop
		1828	4303 F8F53C EA nop
		1829	4304 F8F53D EA nop
		1830	4305 F8F53E 8F 20 FC 00 sta >UART_RXTX ; load data into FIFO/THR
		1831	4306 F8F542 E8 inx ; update head pointer
		1832	4307 F8F543 ACC16
		1833	4308 F8F543 C2 20 rep #PMFLAG
		1834	4309 .LONGA on
		1835	4310 .MNLIST
		1836	4311 F8F545 8A txa
		1837	4312 F8F546 29 FF 7F and #(SOBUFSIZ4-1) ; circular queue
		1838	4313 F8F549 AA tax
		1839	4314 F8F54A ACC08
		1840	4315 F8F54A E2 20 sep #PMFLAG
		1841	4316 .LONGA off
		1842	4317 .MNLIST
		1843	4318 F8F54C 88 dey ; update count
		1844	4319 F8F54D F0 04 beq ?upd ; nothing else to send
		1845	4320 F8F54F C6 30 dec sptmp4
		1846	4321 F8F551 D0 D7 bne ?txl ; loop: load more bytes if FIFO enabled
		1847	4322 F8F553 86 35 ?upd: stx obuftail4
		1848	4323 F8F555 84 3B sty obufcnt4
		1849	4324 F8F557 ?done: CPU08 ; NOTE: tx interrupt will be re-enabled by put routine
		1850	4325 F8F557 E2 30 sep #(PMFLAG.OR.PXFLAG)
		1851	4326 .LONGA off
		1852	4327 .LONGI off
		1853	4328 .MNLIST
		1854	4329 F8F559 60 rts ; or by a negative /CTS transition
		1855	4330
		1856	4331 ; this interrupt is raised when receive a byte with some errors
		1857	4332 F8F55A uartilsr:
		1858	4333 F8F55A A9 05 lda #00000101B ; disable LSR & RX interrupt
		1859	4334 F8F55C 1C 21 FC trb UART_IER
		1860	4335 F8F55F AD 25 FC lda !UART_LSR ; get line status and clear interrupt
		1861	Tue Jul 17 11:11:08 2018 Page 31
		1862
		1863
		1864
		1865
		1866	4336 F8F562 85 42 sta uartlsr ; save for further debugging
		1867	4337 F8F564 4A lsr a ; CF = 1 if available a new rx byte
		1868	4338 F8F565 29 0F and #$0F ; mask on rx errors
		1869	4339 ;beq uartrx1
		1870	4340 F8F567 09 80 ora #$80 ; set rx error bit
		1871	4341 F8F569 85 2F sta spstat4 ; set status register
		1872	4342 F8F56B 90 0C bcc ?done ; no new char received
		1873	4343 F8F56D AD 20 FC lda !UART_RXTX ; get top fifo data or THR & discard
		1874	4344 F8F570 24 43 bit uartiir
		1875	4345 F8F572 50 05 bvc ?done ; no FIFO enabled
		1876	4346 F8F574 A9 83 lda #10000011B ; clear RX FIFO
		1877	4347 F8F576 8D 22 FC sta !UART_FCR
		1878	4348 F8F579 60 ?done: rts ; after rx error, rx interrupt are disabled
		1879	4349
		1880	4350 ; this interrupt is raised either when RHR is full or when RX FIFO reach the
		1881	4351 ; programmed trigger level (in this case 8)
		1882	4352 F8F57A uartrx:
		1883	4353 F8F57A EA nop
		1884	4354 F8F57B EA nop
		1885	4355 F8F57C EA nop
		1886	4356 F8F57D EA nop
		1887	4357 F8F57E INDEX16
		1888	4358 F8F57E C2 10 rep #PXFLAG
		1889	4359 .LONGI on
		1890	4360 .MNLIST
		1891	4361 F8F580 A4 39 ldy ibufcnt4 ; count of bytes in input buffer
		1892	4362 F8F582 A6 33 ldx ibufhead4 ; pointer to head of input buffer
		1893	4363 F8F584 AD 20 FC ?loop: lda !UART_RXTX ; get top fifo data or THR
		1894	4364 F8F587 C4 3F cpy icntmax4 ; check input buff. for remote pause condition
		1895	4365 F8F589 90 14 bcc ?str ; below guard limit: store data
		1896	4366 F8F58B EB xba ; B = received data
		1897	4367 F8F58C A9 02 lda #00000010B ; hardware handshake...
		1898	4368 F8F58E 1C 24 FC trb !UART_MCR ; ...set RTS=1
		1899	4369 F8F591 A9 80 lda #$80 ; set remote pause flag
		1900	4370 F8F593 04 2D tsb sppause4 ; bit 7=1 -> remote pause on
		1901	4371 F8F595 EB xba ; A = received data
		1902	4372 F8F596 C0 00 80 ?chk: cpy #SIBUFSIZ4 ; left room in input buffer?
		1903	4373 F8F599 90 04 bcc ?str ; yes, store received byte
		1904	4374 F8F59B A9 C0 lda #$C0 ; set bit 7: rx error, bit 6: rx overrun
		1905	4375 F8F59D 80 21 bra ?sst ; discard received data & exit
		1906	4376 F8F59F 9F 00 80 06 ?str: sta >SIBUFADDR4,x ; now store received data
		1907	4377 F8F5A3 C8 iny ; update bytes count
		1908	4378 F8F5A4 E8 inx ; update rx head pointer
		1909	4379 F8F5A5 ACC16
		1910	4380 F8F5A5 C2 20 rep #PMFLAG
		1911	4381 .LONGA on
		1912	4382 .MNLIST
		1913	4383 F8F5A7 8A txa
		1914	4384 F8F5A8 29 FF 7F and #(SIBUFSIZ4-1) ; circular queue
		1915	4385 F8F5AB AA tax
		1916	4386 F8F5AC ACC08
		1917	4387 F8F5AC E2 20 sep #PMFLAG
		1918	4388 .LONGA off
		1919	4389 .MNLIST
		1920	4390 F8F5AE 24 43 bit uartiir
		1921	4391 F8F5B0 50 10 bvc ?done
		1922	4392 F8F5B2 AD 25 FC lda !UART_LSR ; get line status
		1923	Tue Jul 17 11:11:08 2018 Page 32
		1924
		1925
		1926
		1927
		1928	4393 F8F5B5 85 42 sta uartlsr
		1929	4394 F8F5B7 4A lsr a ; CF = 1 if available a new rx byte
		1930	4395 F8F5B8 29 0F and #$0F ; mask on rx errors
		1931	4396 F8F5BA 90 06 bcc ?done ; no data available, re-enable rx int. & exit
		1932	4397 F8F5BC F0 C6 beq ?loop
		1933	4398 F8F5BE 09 80 ora #$80
		1934	4399 F8F5C0 85 2F ?sst: sta spstat4
		1935	4400 F8F5C2 86 33 ?done: stx ibufhead4 ; save rx head pointer
		1936	4401 F8F5C4 84 39 sty ibufcnt4 ; save bytes count
		1937	4402 F8F5C6 INDEX08
		1938	4403 F8F5C6 E2 10 sep #PXFLAG
		1939	4404 .LONGI off
		1940	4405 .MNLIST
		1941	4406 F8F5C8 60 rts
		1942	4407
		1943	4408 .COMMENT @
		1944	4409 uartrx:
		1945	4410 ;lda #$01 ; disable RX interrupt
		1946	4411 ;trb UART_IER
		1947	4412 INDEX16
		1948	4413 ldy ibufcnt4 ; count of bytes in input buffer
		1949	4414 ldx ibufhead4 ; pointer to head of input buffer
		1950	4415 rxloop: lda !UART_LSR ; get line status
		1951	4416 sta uartlsr
		1952	4417 lsr a ; CF = 1 if available a new rx byte
		1953	4418 and #$0F ; mask on rx errors
		1954	4419 uartrx1:
		1955	4420 bcc ?done ; no data available, re-enable rx int. & exit
		1956	4421 xba ; save error code
		1957	4422
		1958	4423 nop
		1959	4424 nop
		1960	4425 nop
		1961	4426 nop
		1962	4427
		1963	4428 lda !UART_RXTX ; get top fifo data or THR
		1964	4429 xba
		1965	4430 ?tst: beq ?rx ; no rx error pending
		1966	4431 ora #$80 ; set rx error bit
		1967	4432 bra ?sst ; set status reg. & discard received data
		1968	4433 ?rx: xba ; A = received data
		1969	4434 cpy icntmax4 ; check input buff. for remote pause condition
		1970	4435 bcc ?str ; below guard limit: store data
		1971	4436 xba ; B = received data
		1972	4437 lda #00000010B ; hardware handshake...
		1973	4438 trb !UART_MCR ; ...set RTS=1
		1974	4439 lda #$80 ; set remote pause flag
		1975	4440 tsb sppause4 ; bit 7=1 -> remote pause on
		1976	4441 xba ; A = received data
		1977	4442 ?chk: cpy #SIBUFSIZ4 ; left room in input buffer?
		1978	4443 bcc ?str ; yes, store received byte
		1979	4444 lda #$C0 ; set bit 7: rx error, bit 6: rx overrun
		1980	4445 ?sst: sta spstat4 ; set status register
		1981	4446 bra ?done ; discard received data & exit
		1982	4447 ?str: sta >SIBUFADDR4,x ; now store received data
		1983	4448 iny ; update bytes count
		1984	4449 inx ; update rx head pointer
		1985	Tue Jul 17 11:11:08 2018 Page 33
		1986
		1987
		1988
		1989
		1990	4450 ACC16
		1991	4451 txa
		1992	4452 and #(SIBUFSIZ4-1) ; circular queue
		1993	4453 tax
		1994	4454 ACC08
		1995	4455 bra rxloop ; check again if rx data available
		1996	4456 ?done: stx ibufhead4 ; save rx head pointer
		1997	4457 sty ibufcnt4 ; save bytes count
		1998	4458 ?done1: INDEX08
		1999	4459 ;lda #$01 ; re-enable rx interrupt
		2000	4460 ;tsb UART_IER
		2001	4461 rts
		2002	4462 @
		2003	4463
		2004	4464 .COMMENT @
		2005	4465 uart:
		2006	4466 lda !UART_IIR
		2007	4467 sta uartiir
		2008	4468 lsr a ; if <0> = 1 no interrupt
		2009	4469 bcc $+3 ; interrupt pending
		2010	4470 rts
		2011	4471 and #0000011B ; mask on priority code
		2012	4472 asl a
		2013	4473 tax
		2014	4474 jmp (?uarttbl,x)
		2015	4475
		2016	4476 ?uarttbl:
		2017	4477 .DW ?msr, ?tx, ?rx, ?lsr
		2018	4478
		2019	4479
		2020	4480 ; int. 3: line status register (LSR)
		2021	4481 ;
		2022	4482 ?lsr: ;jsr uartrx
		2023	4483 lda !UART_LSR ; read LSR and clear interrupt
		2024	4484 sta uartlsr
		2025	4485 ;rts
		2026	4486 bra uart ; check again interrupt
		2027	4487
		2028	4488 ?msr: jsr uartmsr ; MSR: modem status register
		2029	4489 ;rts
		2030	4490 bra uart ; check again iterrupt
		2031	4491
		2032	4492 ?tx: jsr uarttx ; TX FIFO is empty
		2033	4493 ;rts
		2034	4494 bra uart ; check again interrupt
		2035	4495
		2036	4496 ?rx: jsr uartrx ; data available in RX FIFO
		2037	4497 ;rts
		2038	4498 bra uart ; check again interrupt
		2039	4499
		2040	4500
		2041	4501 uartmsr:
		2042	4502 lda !UART_MSR
		2043	4503 tax
		2044	4504 asl a
		2045	4505 asl a ; <7>: /DSR, <6>: /CTS
		2046	4506 eor #$C0
		2047	Tue Jul 17 11:11:08 2018 Page 34
		2048
		2049
		2050
		2051
		2052	4507 sta splin4 ; update line status
		2053	4508 tay
		2054	4509 bit spmode4
		2055	4510 bpl ?end ; no handshake
		2056	4511 bvc ?end ; software handshake: no /CTS and /DSR check
		2057	4512 tya
		2058	4513 bpl ?cts ; /DSR is low
		2059	4514 lda #$A0
		2060	4515 tsb spstat4 ; remote terminal disconnected
		2061	4516 ?cts: bvc ?end ; handshake software: no check /CTS
		2062	4517 txa
		2063	4518 lsr a ; check /CTS transition
		2064	4519 bcc ?end ; no /CTS transition
		2065	4520 ldx #$40 ; local pause flag
		2066	4521 tya
		2067	4522 asl a
		2068	4523 bpl ?clp ; transition high->low
		2069	4524 txa
		2070	4525 tsb sppause4 ; /CTS high set local pause
		2071	4526 rts
		2072	4527 ?clp: txa
		2073	4528 trb sppause4 ; /CTS low clear local pause
		2074	4529 ?end: rts
		2075	4530
		2076	4531 uarttx:
		2077	4532 ;;lda !UART_IIR
		2078	4533
		2079	4534 lda !UART_LSR
		2080	4535 and #$40
		2081	4536 ;;cmp #$60
		2082	4537 bne ?cklp
		2083	4538 lda !UART_IIR
		2084	4539 rts
		2085	4540 ;lda #$20
		2086	4541 ;bit !UART_LSR
		2087	4542 ;bne ?cklp
		2088	4543 ;rts
		2089	4544
		2090	4545 bra ?cklp
		2091	4546 ldx spout4 ; pending an XON/XOFF sending?
		2092	4547 beq ?cklp ; no... check local pause flag
		2093	4548
		2094	4549 ; if send an XON then we will re-enable tx interrupt
		2095	4550 ; else we will disable tx interrupt
		2096	4551 ;
		2097	4552 lda #00000010B ; IER<1>: tx interrupt
		2098	4553 cpx #SPXON
		2099	4554 bne ?di
		2100	4555 tsb !UART_IER ; enable tx interrupt
		2101	4556 bra ?htx1
		2102	4557 ?di: trb !UART_IER ; disable tx interrupt
		2103	4558 ?htx1: stx .ABS.UART_RXTX ; send XON/XOFF
		2104	4559 stz spout4 ; clear XON/XOFF flag
		2105	4560 lda #$80 ; remote pause flag
		2106	4561 cpx #SPXOFF
		2107	4562 beq ?srp ; sent an XOFF: set remote pause flag
		2108	4563 trb sppause4 ; sent an XON: clear remote pause flag
		2109	Tue Jul 17 11:11:08 2018 Page 35
		2110
		2111
		2112
		2113
		2114	4564 rts ; done
		2115	4565 ?srp: tsb sppause4 ; set remote pause flag
		2116	4566 rts
		2117	4567 ?cklp: bit sppause4 ; local pause is set ?
		2118	4568 bvs ?off ; yes, no tx possible at this time
		2119	4569 INDEX16
		2120	4570 ldx obufhead4 ; pointer to head of out buffer
		2121	4571 ldy obufcnt4 ; count of bytes in output buffer
		2122	4572 bne ?snd ; output buffer is not empty
		2123	4573 ?off: lda #00000010B ; disable TX interrupt for avoid cont. int.
		2124	4574 trb !UART_IER
		2125	4575 bra ?done
		2126	4576 ?snd:
		2127	4577 lda #00000010B ; disable TX interrupt for avoid cont. int.
		2128	4578 trb !UART_IER
		2129	4579
		2130	4580 lda #1 ; fill fifo
		2131	4581 sta spout4
		2132	4582 lda #$20
		2133	4583 bit spmode4
		2134	4584 bne ?txl
		2135	4585 lda #1
		2136	4586 sta spout4
		2137	4587 ?txl:
		2138	4588 lda >SOBUFADDR4,x ; get data from output buffer
		2139	4589 sta !UART_RXTX ; send data to FIFO
		2140	4590 inx ; update head pointer
		2141	4591 ACC16
		2142	4592 txa
		2143	4593 and #(SOBUFSIZ4-1) ; circular queue
		2144	4594 tax
		2145	4595 ACC08
		2146	4596 dey
		2147	4597 beq ?upd
		2148	4598 dec spout4
		2149	4599 bne ?txl
		2150	4600 ?upd: stz spout4
		2151	4601 stx obufhead4
		2152	4602 sty obufcnt4
		2153	4603 ?done: CPU08
		2154	4604 lda !UART_IIR
		2155	4605 rts
		2156	4606
		2157	4607 uartrx:
		2158	4608 ;lda spstat4
		2159	4609 ;bmi ?rts
		2160	4610
		2161	4611 lda #$01
		2162	4612 trb UART_IER
		2163	4613 INDEX16
		2164	4614 ldy ibufcnt4
		2165	4615 ldx ibuftail4
		2166	4616 ?lp1: lda !UART_LSR
		2167	4617 sta uartlsr
		2168	4618 lsr a
		2169	4619 bcc ?done
		2170	4620
		2171	Tue Jul 17 11:11:08 2018 Page 36
		2172
		2173
		2174
		2175
		2176	4621 ;bcs ?loop
		2177	4622 ;and #$0F
		2178	4623 ;beq ?done1
		2179	4624 ;ora #$80 ; set rx error bit
		2180	4625 ;sta spstat4
		2181	4626 ;bra ?done1
		2182	4627
		2183	4628 ?loop: and #$0F ; mask on errors
		2184	4629 xba
		2185	4630 lda !UART_RXTX ; get top fifo data
		2186	4631 xba
		2187	4632 beq ?rx ; no rx error pending
		2188	4633 ora #$80 ; set rx error bit
		2189	4634 bra ?sst ; set status reg. & discard received data
		2190	4635 ?rx: xba ; A = received data
		2191	4636 bit spmode4 ; test for active handshake
		2192	4637 bpl ?chk ; no handshake: goto to check input queue
		2193	4638 bvs ?tst ; hardware handshake (check queue overflow)
		2194	4639 cmp #SPXON ; received an XON control byte?
		2195	4640 bne ?xoff ; no, check if received an XOFF
		2196	4641 lda #$40 ; clear local pause flag
		2197	4642 trb sppause4 ; bit<6> = 0 -> local pause off (resume tx)
		2198	4643 bra ?cnt ; discard received data
		2199	4644 ?xoff: cmp #SPXOFF ; received an XOFF control byte?
		2200	4645 bne ?tst ; no, so check queue overflow
		2201	4646 lda #$40 ; set local pause flag
		2202	4647 tsb sppause4 ; bit<6> = 1 -> local pause on (will stop tx)
		2203	4648 bra ?cnt ; discard received data
		2204	4649 ?tst: cpy icntmax4 ; check input buff. for remote pause condition
		2205	4650 bcc ?str ; below guard limit: store data
		2206	4651 bit sppause4 ; remote pause is already on ?
		2207	4652 bmi ?chk ; yes, so check input buffer
		2208	4653 xba ; B = received data
		2209	4654 bit spmode4 ; test handshake type
		2210	4655 bvs ?rtsh ; bit 6=1 -> hardware handshake so set RTS=1
		2211	4656 lda #SPXOFF ; send an XOFF to remote terminal
		2212	4657 sta spout4 ; XOFF sending deffered until THR is empty
		2213	4658 lda #00000010B ; IER<1>: tx interrupt
		2214	4659 tsb !UART_IER ; enable tx interrupt
		2215	4660 bra ?xba ; check input buffer
		2216	4661 ?rtsh: lda #00000010B ; hardware handshake...
		2217	4662 trb !UART_MCR ; ...set RTS=1
		2218	4663 lda #$80 ; set remote pause
		2219	4664 tsb sppause4 ; bit 7=1 -> remote pause on
		2220	4665 ?xba: xba ; A = received data
		2221	4666 ?chk: cpy #SIBUFSIZ4 ; left room in input buffer?
		2222	4667 bcc ?str ; yes, store received byte
		2223	4668 lda #$C0 ; set bit 7: rx error, bit 6: rx overflow
		2224	4669 ?sst: sta spstat4 ; set status register
		2225	4670 bra ?done ; discard received data & exit
		2226	4671 ?str: sta >SIBUFADDR4,x ; now store received data
		2227	4672 iny ; update bytes count
		2228	4673 inx ; update rx tail pointer
		2229	4674 ACC16
		2230	4675 txa
		2231	4676 and #(SIBUFSIZ4-1) ; circular queue
		2232	4677 tax
		2233	Tue Jul 17 11:11:08 2018 Page 37
		2234
		2235
		2236
		2237
		2238	4678 ACC08
		2239	4679 ?cnt: ;lda !UART_LSR ; any rx data pending?
		2240	4680 ;sta uartlsr
		2241	4681 ;lsr a
		2242	4682 ;bcs ?loop ; yes, get again from top fifo
		2243	4683 bra ?lp1
		2244	4684 ?done: stx ibuftail4 ; save rx tail pointer
		2245	4685 sty ibufcnt4 ; save bytes count
		2246	4686 ?done1: INDEX08
		2247	4687 ?rts:
		2248	4688 lda #$01
		2249	4689 tsb UART_IER
		2250	4690 rts
		2251	4691 @
		2252	4692
		2253	4693 F8F5C9 int5sr:
		2254	4694 F8F5C9 int6sr:
		2255	4695 F8F5C9 60 rts
		2256	4696
		2257	4697 ; INT from RTC
		2258	4698 F8F5CA int7sr:
		2259	4699 F8F5CA A2 0A ldx #RTCCTRLA ; setta banco 1 RTC
		2260	4700 F8F5CC 8E 4C FD stx RTCALE
		2261	4701 F8F5CF AD 4D FD lda RTCDATA ; salva flag banco
		2262	4702 F8F5D2 48 pha
		2263	4703 F8F5D3 09 10 ora #$10 ; setta banco 1
		2264	4704 F8F5D5 8D 4D FD sta RTCDATA
		2265	4705 F8F5D8 A2 4E ldx #RTCSMI2 ; recupera eventuale ALE
		2266	4706 F8F5DA 8E 4C FD stx RTCALE
		2267	4707 F8F5DD AD 4D FD lda RTCDATA
		2268	4708 F8F5E0 48 pha ; ALE da ripristinare
		2269	4709 F8F5E1 A2 0C ldx #RTCSTATUS
		2270	4710 F8F5E3 8E 4C FD stx RTCALE
		2271	4711 F8F5E6 AD 4D FD lda RTCDATA ; azzera flag
		2272	4712 F8F5E9 30 03 bmi ?01
		2273	4713 F8F5EB 4C 74 F6 jmp ?20 ; NO IRQ da RTC
		2274	4714 F8F5EE 89 20 ?01: bit #$20 ; flag AF (alarm)
		2275	4715 F8F5F0 F0 5E beq ?10 ; no alarm
		2276	4716 F8F5F2 A2 4A ldx #RTCEXTCTRLA ; check INCR bit 6
		2277	4717 F8F5F4 8E 4C FD stx RTCALE
		2278	4718 F8F5F7 2C 4D FD ?02: bit RTCDATA
		2279	4719 F8F5FA 70 FB bvs ?02
		2280	4720 F8F5FC A2 06 ldx #RTCDAY ; day of week
		2281	4721 F8F5FE 8E 4C FD stx RTCALE
		2282	4722 F8F601 AD 4D FD lda RTCDATA
		2283	4723 F8F604 C9 01 cmp #1 ; sunday?
		2284	4724 F8F606 D0 48 bne ?10 ; no
		2285	4725 F8F608 E8 inx
		2286	4726 F8F609 8E 4C FD stx RTCALE
		2287	4727 F8F60C AD 4D FD lda RTCDATA ; day of month (date)
		2288	4728 F8F60F C9 19 cmp #25 ; last sunday of month?
		2289	4729 F8F611 90 3D bcc ?10 ; no
		2290	4730 F8F613 E8 inx
		2291	4731 F8F614 8E 4C FD stx RTCALE ; month
		2292	4732 F8F617 AD 4D FD lda RTCDATA
		2293	4733 F8F61A C9 03 cmp #3 ; march?
		2294	4734 F8F61C D0 12 bne ?04 ; no
		2295	Tue Jul 17 11:11:08 2018 Page 38
		2296
		2297
		2298
		2299
		2300	4735 F8F61E A2 04 ldx #RTCHOURS ; increment hours
		2301	4736 F8F620 8E 4C FD stx RTCALE
		2302	4737 F8F623 EE 4D FD inc RTCDATA
		2303	4738 F8F626 A2 0F ldx #RTCRAM0F
		2304	4739 F8F628 8E 4C FD stx RTCALE
		2305	4740 F8F62B 9C 4D FD stz RTCDATA ; reset flag for next time
		2306	4741 F8F62E 80 20 bra ?10
		2307	4742 F8F630 C9 0A ?04: cmp #10 ; october?
		2308	4743 F8F632 D0 1C bne ?10 ; no
		2309	4744 F8F634 A2 0F ldx #RTCRAM0F
		2310	4745 F8F636 8E 4C FD stx RTCALE
		2311	4746 F8F639 AD 4D FD lda RTCDATA ; already updated?
		2312	4747 F8F63C 10 05 bpl ?06 ; no
		2313	4748 F8F63E 9C 4D FD stz RTCDATA ; yes...so reset flag
		2314	4749 F8F641 80 0D bra ?10
		2315	4750 F8F643 A9 FF ?06: lda #$FF
		2316	4751 F8F645 8D 4D FD sta RTCDATA ; set updated flag
		2317	4752 F8F648 A2 04 ldx #RTCHOURS ; decrement hours
		2318	4753 F8F64A 8E 4C FD stx RTCALE
		2319	4754 F8F64D CE 4D FD dec RTCDATA
		2320	4755 F8F650 A2 4A ?10: ldx #RTCEXTCTRLA ; check others interrupt's
		2321	4756 F8F652 8E 4C FD stx RTCALE
		2322	4757 F8F655 AD 4D FD lda RTCDATA
		2323	4758 F8F658 89 01 bit #$01 ; KF ?
		2324	4759 F8F65A 08 php
		2325	4760 F8F65B A9 07 lda #$07 ; cancella altri IRQ
		2326	4761 F8F65D 1C 4D FD trb RTCDATA
		2327	4762 F8F660 28 plp
		2328	4763 F8F661 F0 11 beq ?20 ; NO KF
		2329	4764 F8F663 A9 01 lda #$01 ; TEST KS START
		2330	4765 F8F665 24 0D bit RTCFlag
		2331	4766 F8F667 D0 04 bne ?11 ; KS OFF
		2332	4767 F8F669 04 0D tsb RTCFlag ; segnala KS OFF
		2333	4768 F8F66B 80 07 bra ?20
		2334	4769 F8F66D A9 08 ?11: lda #$08 ; PAB = 1, PWR OFF
		2335	4770 ;tsb RTCDATA
		2336	4771 F8F66F 1C 4D FD trb RTCDATA
		2337	4772 F8F672 A9 01 lda #$01 ; CLEAR KS START
		2338	4773 ;trb SysRTC
		2339	4774 F8F674 7A ?20: ply ; ALE da ripristinare
		2340	4775 F8F675 A2 0A ldx #RTCCTRLA ; setta banco originale RTC
		2341	4776 F8F677 8E 4C FD stx RTCALE
		2342	4777 F8F67A 68 pla ; banco originale
		2343	4778 F8F67B 8D 4D FD sta RTCDATA ; salva flag banco
		2344	4779 F8F67E 8C 4C FD sty RTCALE ; ripristina ALE
		2345	4780 F8F681 60 rts
		2346	4781 F8F682
		2347	4782
		2348	4783 .CODE
		2349	4784
		2350	4785 .EXTERN SysStart
		2351	4786 .GLOBAL intsr
		2352	4787
		2353	4788 ;
		2354	4789 ; FWE XFE R/W BANK $F0
		2355	4790 ; 0 X X RAM
		2356	4791 ; 1 0 X FLASH
		2357	Tue Jul 17 11:11:08 2018 Page 39
		2358
		2359
		2360
		2361
		2362	4792 ; 1 1 1 EEROM8U
		2363	4793 ; 1 1 0 RAM
		2364	4794 ;
		2365	4795 ; codice di startup
		2366	4796 F8FE00 _RSTEntry:
		2367	4797
		2368	4798 ; at start: XFE=0, FWE=0, HIM=0
		2369	4799 F8FE00 78 sei
		2370	4800 F8FE01 D8 cld
		2371	4801 ;sta !CRHIMOFF ; forza start da flash
		2372	4802 F8FE02 18 clc
		2373	4803 F8FE03 FB xce ; CPU in modo nativo
		2374	4804 F8FE04 A0 00 ldy #0
		2375	4805 F8FE06 CPU16
		2376	4806 F8FE06 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2377	4807 .LONGA on
		2378	4808 .LONGI on
		2379	4809 .MNLIST
		2380	4810 F8FE08 A2 FF DF ldx #STACK_ADDR ; init stack
		2381	4811 F8FE0B 9A txs
		2382	4812 F8FE0C 98 tya ; DP = 0 (page 0)
		2383	4813 F8FE0D 5B tcd
		2384	4814 F8FE0E BB tyx
		2385	4815 F8FE0F CPU08
		2386	4816 F8FE0F E2 30 sep #(PMFLAG.OR.PXFLAG)
		2387	4817 .LONGA off
		2388	4818 .LONGI off
		2389	4819 .MNLIST
		2390	4820 F8FE11 4B phk
		2391	4821 F8FE12 AB plb ; DBR = PBR = 0
		2392	4822
		2393	4823 F8FE13 AD 00 FC lda !CRBIT0 ; test boot
		2394	4824 F8FE16 F0 46 beq ?09 ; firmware from FLASH
		2395	4825
		2396	4826 ; check EEROM emulator board
		2397	4827 F8FE18 8C 62 FC ?00: sty .ABS.VIA4+VIADDRB
		2398	4828 F8FE1B CC 62 FC cpy .ABS.VIA4+VIADDRB
		2399	4829 F8FE1E D0 3E bne ?09 ; fail -- goto old way
		2400	4830 F8FE20 C8 iny
		2401	4831 F8FE21 D0 F5 bne ?00
		2402	4832 F8FE23
		2403	4833 ; ok, seem present
		2404	4834 F8FE23 88 dey
		2405	4835 F8FE24 8C 62 FC sty .ABS.VIA4+VIADDRB ; port B out
		2406	4836
		2407	4837 ; transfer emulator data to $F0 bank
		2408	4838 F8FE27 A9 F0 lda #$F0
		2409	4839 F8FE29 85 02 sta <2
		2410	4840 F8FE2B 64 00 stz <0
		2411	4841 F8FE2D 64 01 stz <1
		2412	4842 F8FE2F 9C 60 FC stz !VIA4+VIAPRB
		2413	4843 F8FE32 8D 0D FC sta !CREMEON
		2414	4844 F8FE35 INDEX16
		2415	4845 F8FE35 C2 10 rep #PXFLAG
		2416	4846 .LONGI on
		2417	4847 .MNLIST
		2418	4848 F8FE37 A0 00 00 ?lp1: ldy #0
		2419	Tue Jul 17 11:11:08 2018 Page 40
		2420
		2421
		2422
		2423
		2424	4849 F8FE3A BB tyx
		2425	4850 F8FE3B BF 00 18 01 ?lp2: lda >EMURAM,x
		2426	4851 F8FE3F 97 00 sta [0],y
		2427	4852 F8FE41 C8 iny
		2428	4853 F8FE42 E8 inx
		2429	4854 F8FE43 E0 00 08 cpx #$0800
		2430	4855 F8FE46 90 F3 bcc ?lp2
		2431	4856 F8FE48 ACC16CLC
		2432	4857 F8FE48 C2 21 rep #(PMFLAG.OR.PCFLAG)
		2433	4858 .LONGA on
		2434	4859 .MNLIST
		2435	4860 F8FE4A 8A txa
		2436	4861 F8FE4B 65 00 adc <0
		2437	4862 F8FE4D 85 00 sta <0
		2438	4863 F8FE4F ACC08
		2439	4864 F8FE4F E2 20 sep #PMFLAG
		2440	4865 .LONGA off
		2441	4866 .MNLIST
		2442	4867 F8FE51 90 02 bcc ?nxt
		2443	4868 F8FE53 E6 02 inc <2
		2444	4869 F8FE55 EE 60 FC ?nxt: inc !VIA4+VIAPRB
		2445	4870 F8FE58 D0 DD bne ?lp1
		2446	4871 F8FE5A CPU08
		2447	4872 F8FE5A E2 30 sep #(PMFLAG.OR.PXFLAG)
		2448	4873 .LONGA off
		2449	4874 .LONGI off
		2450	4875 .MNLIST
		2451	4876 F8FE5C 80 08 bra ?10
		2452	4877
		2453	4878 ;sta !CREMEOFF
		2454	4879 ;ldy #0
		2455	4880 ;CPU16
		2456	4881 ;tyx
		2457	4882 ;lda #$FFFF
		2458	4883 ;mvn #$E8, #$F8
		2459	4884 ;mvn #$E9, #$F9
		2460	4885 ;mvn #$EA, #$FA
		2461	4886 ;mvn #$EB, #$FB
		2462	4887 ;mvn #$EC, #$FC
		2463	4888 ;mvn #$ED, #$FD
		2464	4889 ;mvn #$EE, #$FE
		2465	4890 ;mvn #$EF, #$FF
		2466	4891 ;CPU08
		2467	4892 ;bra ?11
		2468	4893
		2469	4894 ; original boot sequence
		2470	4895 F8FE5E 8D 07 FC ?09: sta !CRFWEON ; enable FLASH/EMU IN BANK $F0
		2471	4896 ;lda !CRBIT0 ; test boot
		2472	4897 F8FE61 F0 03 beq ?10 ; firmware from flash
		2473	4898 F8FE63 8D 09 FC sta !CRXFEON ; enable EEROM8U
		2474	4899 F8FE66 A0 00 ?10: ldy #0
		2475	4900 F8FE68 CPU16
		2476	4901 F8FE68 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2477	4902 .LONGA on
		2478	4903 .LONGI on
		2479	4904 .MNLIST
		2480	4905 F8FE6A BB tyx
		2481	Tue Jul 17 11:11:08 2018 Page 41
		2482
		2483
		2484
		2485
		2486	4906 F8FE6B A9 FF FF lda #$FFFF
		2487	4907 F8FE6E 54 F8 F0 mvn #$F0, #$F8
		2488	4908 F8FE71 54 F9 F1 mvn #$F1, #$F9
		2489	4909 F8FE74 54 FA F2 mvn #$F2, #$FA
		2490	4910 F8FE77 54 FB F3 mvn #$F3, #$FB
		2491	4911 F8FE7A 54 FC F4 mvn #$F4, #$FC
		2492	4912 F8FE7D 54 FD F5 mvn #$F5, #$FD
		2493	4913 F8FE80 54 FE F6 mvn #$F6, #$FE
		2494	4914 F8FE83 54 FF F7 mvn #$F7, #$FF
		2495	4915 F8FE86 CPU08
		2496	4916 F8FE86 E2 30 sep #(PMFLAG.OR.PXFLAG)
		2497	4917 .LONGA off
		2498	4918 .LONGI off
		2499	4919 .MNLIST
		2500	4920 F8FE88 4B ?11: phk
		2501	4921 F8FE89 AB plb ; DBR = PBR = 0
		2502	4922 F8FE8A 8D 08 FC sta CRXFEOFF ; disabilita flash F00000 - F7FFFF
		2503	4923 F8FE8D 8D 06 FC sta CRFWEOFF
		2504	4924 F8FE90 5C F0 FF F8 jml _SysStart ; long jmp - bootstrap (banco $F8)
		2505	4925
		2506	4926 F8FE94 _Unexpected:
		2507	4927 F8FE94 40 rti
		2508	4928 F8FE95
		2509	4929 ; software interrupt generated by 'cop' istruction
		2510	4930 ;
		2511	4931 ; stack frame
		2512	4932 ; ---------
		2513	4933 ; \| PBR \| 0F
		2514	4934 ; ---------
		2515	4935 ; \| PCH \| 0E
		2516	4936 ; ---------
		2517	4937 ; \| PCL \| 0D
		2518	4938 ; ---------
		2519	4939 ; \| P \| 0C
		2520	4940 ; ---------
		2521	4941 ; \| B \| 0B
		2522	4942 ; ---------
		2523	4943 ; \| A \| 0A
		2524	4944 ; ---------
		2525	4945 ; \| XH \| 09
		2526	4946 ; ---------
		2527	4947 ; \| XL \| 08
		2528	4948 ; ---------
		2529	4949 ; \| YH \| 07
		2530	4950 ; ---------
		2531	4951 ; \| YL \| 06
		2532	4952 ; ---------
		2533	4953 ; \| DPH \| 05
		2534	4954 ; ---------
		2535	4955 ; \| DPL \| 04
		2536	4956 ; ---------
		2537	4957 ; \| DBR \| 03
		2538	4958 ; ---------
		2539	4959 ; \| CNTH \| 02
		2540	4960 ; --------- --> CNT parameters bytes count
		2541	4961 ; \| CNTL \| 01
		2542	4962 ; ---------
		2543	Tue Jul 17 11:11:08 2018 Page 42
		2544
		2545
		2546
		2547
		2548	4963 ;
		2549	4964 ; equates for access stack offset data
		2550	4965 000001 STKCNT .SET $01
		2551	4966 000006 STKYR .SET $06
		2552	4967 000008 STKXR .SET $08
		2553	4968 00000A STKCR .SET $0A
		2554	4969 00000B STKBR .SET $0B
		2555	4970 00000C STKSR .SET $0C
		2556	4971 00000D STKPCL .SET $0D
		2557	4972 00000F STKPBR .SET $0F
		2558	4973 00000F STKNVAR .SET $0F
		2559	4974
		2560	4975 ;USRCOP .SET $C0
		2561	4976
		2562	4977 ;EINVAL .EQU $01
		2563	4978
		2564	4979 F8FE95 _COPEntry:
		2565	4980 F8FE95 CPU16 ; A/MEM/X/Y -> 16 bit
		2566	4981 F8FE95 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2567	4982 .LONGA on
		2568	4983 .LONGI on
		2569	4984 .MNLIST
		2570	4985 F8FE97 48 pha ; save C in stack
		2571	4986 F8FE98 DA phx ; save X(16) in stack
		2572	4987 F8FE99 5A phy ; save Y(16) in stack
		2573	4988 F8FE9A 0B phd ; save DPR in stack
		2574	4989 F8FE9B 8B phb ; save DBR in stack
		2575	4990 F8FE9C A9 00 00 lda #0
		2576	4991 F8FE9F AA tax ; X = 0
		2577	4992 F8FEA0 48 pha ; params byte count in the stack ( = 0)
		2578	4993 F8FEA1 5B tcd ; set DPR = $0000
		2579	4994 F8FEA2 4B phk ; set DBR = PBR = $00
		2580	4995 F8FEA3 AB plb
		2581	4996 F8FEA4 A3 0D lda STKPCL,s ; load PC saved in stack
		2582	4997 F8FEA6 3A dec a ; pointer to signature byte
		2583	4998 F8FEA7 85 51 sta COPPtr ; save long pointer
		2584	4999 F8FEA9 CPU08 ; A/MEM/X/Y -> 8 bit
		2585	5000 F8FEA9 E2 30 sep #(PMFLAG.OR.PXFLAG)
		2586	5001 .LONGA off
		2587	5002 .LONGI off
		2588	5003 .MNLIST
		2589	5004 F8FEAB 8A txa
		2590	5005 F8FEAC EB xba ; B = 0
		2591	5006 F8FEAD A3 0F lda STKPBR,s ; PBR bank where COP was executed
		2592	5007 F8FEAF 85 53 sta COPPtr+2
		2593	5008 F8FEB1 A3 0C lda STKSR,s ; saved P in stack
		2594	5009 F8FEB3 AA tax
		2595	5010 F8FEB4 29 FE and #~PCFLAG ; clear carry in saved P
		2596	5011 F8FEB6 83 0C sta STKSR,s
		2597	5012 F8FEB8 89 04 bit #PIFLAG ; check if IRQ was enabled
		2598	5013 F8FEBA D0 01 bne ?04
		2599	5014 F8FEBC 58 cli ; enable IRQ
		2600	5015 F8FEBD DA ?04: phx ; saved P in stack
		2601	5016 F8FEBE A7 51 lda [COPPtr] ; fetch signature byte
		2602	5017 F8FEC0 85 54 sta COPIdx
		2603	5018 F8FEC2 CPU16 ; now C = $00XX
		2604	5019 F8FEC2 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2605	Tue Jul 17 11:11:08 2018 Page 43
		2606
		2607
		2608
		2609
		2610	5020 .LONGA on
		2611	5021 .LONGI on
		2612	5022 .MNLIST
		2613	5023 F8FEC4 0A asl a ; index * 4
		2614	5024 F8FEC5 0A asl a
		2615	5025 F8FEC6 AA tax
		2616	5026 F8FEC7 E0 00 02 cpx #$0200
		2617	5027 F8FECA 90 0B bcc ?05 ; range $00..$7F
		2618	5028 F8FECC BF 00 FA F8 lda >SYSTBLE_ADDR,x ; address of cop vector range $80..$FF
		2619	5029 F8FED0 A8 tay
		2620	5030 F8FED1 BF 02 FA F8 lda >SYSTBLE_ADDR+2,x ; A = bank of cop vector, B = valid/params
		2621	5031 F8FED5 80 06 bra ?06
		2622	5032 F8FED7 BC 00 FA ?05: ldy !SYSTBLE_ADDR,x ; address of cop vector range $00..$7F
		2623	5033 F8FEDA BD 02 FA lda !SYSTBLE_ADDR+2,x ; A = bank of cop vector, B = valid/params
		2624	5034 F8FEDD 8C ED FE ?06: sty ?08+1
		2625	5035 F8FEE0 CPU08
		2626	5036 F8FEE0 E2 30 sep #(PMFLAG.OR.PXFLAG)
		2627	5037 .LONGA off
		2628	5038 .LONGI off
		2629	5039 .MNLIST
		2630	5040 F8FEE2 30 38 bmi ?30 ; B<7> = 1 -> invalid function
		2631	5041 F8FEE4 8D EF FE sta !?08+3
		2632	5042 F8FEE7 EB xba ; A = bytes number of params
		2633	5043 F8FEE8 83 02 sta STKCNT+1,s ; take in account the 'phx' in ?04 !!
		2634	5044 F8FEEA 68 pla ; saved P in stack
		2635	5045 F8FEEB 4A lsr a ; pass carry to function
		2636	5046 F8FEEC 22 00 00 00 ?08: jsl $000000
		2637	5047 F8FEF0 90 0C bcc ?16 ; no error
		2638	5048 F8FEF2 83 06 sta STKYR,s ; return error in Y
		2639	5049 F8FEF4 A9 00 lda #0
		2640	5050 F8FEF6 83 07 sta STKYR+1,s
		2641	5051 F8FEF8 A3 0C lda STKSR,s ; saved P in stack
		2642	5052 F8FEFA 09 01 ora #PCFLAG ; set carry in saved P
		2643	5053 F8FEFC 83 0C sta STKSR,s
		2644	5054 ?16: ; epilogue code
		2645	5055 F8FEFE CPU16
		2646	5056 F8FEFE C2 30 rep #(PMFLAG.OR.PXFLAG)
		2647	5057 .LONGA on
		2648	5058 .LONGI on
		2649	5059 .MNLIST
		2650	5060 F8FF00 A3 01 lda STKCNT,s ; number of params bytes in the stack
		2651	5061 F8FF02 F0 11 beq ?20 ; no params -- skip stack cleaning
		2652	5062 F8FF04 18 clc
		2653	5063 F8FF05 3B tsc ; C = stack pointer
		2654	5064 F8FF06 69 0F 00 adc #STKNVAR ; add size of stack vars
		2655	5065 F8FF09 AA tax ; source pointer for data move
		2656	5066 F8FF0A 63 01 adc STKCNT,s ; add params bytes count
		2657	5067 F8FF0C A8 tay ; dest pointer for data move
		2658	5068 F8FF0D A9 0E 00 lda #STKNVAR-1 ; move bytes count
		2659	5069 F8FF10 44 00 00 mvp #0, #0 ; cleanup stack
		2660	5070 F8FF13 98 tya ; new stack pointer
		2661	5071 F8FF14 1B tcs
		2662	5072 F8FF15 68 ?20: pla ; skip STKCNT
		2663	5073 F8FF16 AB plb ; restore DBR
		2664	5074 F8FF17 2B pld ; restore DPR
		2665	5075 F8FF18 7A ply ; restore Y
		2666	5076 F8FF19 FA plx ; restore X
		2667	Tue Jul 17 11:11:08 2018 Page 44
		2668
		2669
		2670
		2671
		2672	5077 F8FF1A 68 pla ; restore C
		2673	5078 F8FF1B 40 rti ; restore P and return
		2674	5079
		2675	5080 F8FF1C FA ?30: plx
		2676	5081 F8FF1D 4C FE FE jmp ?16
		2677	5082
		2678	5083 F8FF20 _BRKEntry:
		2679	5084 F8FF20 CPU16 ; salva registri 16 bit
		2680	5085 F8FF20 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2681	5086 .LONGA on
		2682	5087 .LONGI on
		2683	5088 .MNLIST
		2684	5089 F8FF22 48 pha ; salva A
		2685	5090 F8FF23 DA phx ; salva X
		2686	5091 F8FF24 5A phy ; salva Y
		2687	5092 F8FF25 0B phd
		2688	5093 F8FF26 8B phb ; salva DBR
		2689	5094 F8FF27 4B phk ; DBR = 0 = PBR(K)
		2690	5095 F8FF28 AB plb ; DATA BANK 0
		2691	5096 F8FF29 CPU08
		2692	5097 F8FF29 E2 30 sep #(PMFLAG.OR.PXFLAG)
		2693	5098 .LONGA off
		2694	5099 .LONGI off
		2695	5100 .MNLIST
		2696	5101 F8FF2B 5C 06 00 FF jml BRKMON
		2697	5102 F8FF2F
		2698	5103 ; gestione interrupt non mascherabile linea NMI (RTI restore P and register size)
		2699	5104 F8FF2F _NMIEntry:
		2700	5105
		2701	5106 .EXTERN shutdown
		2702	5107
		2703	5108 F8FF2F CPU16 ; salva registri 16 bit
		2704	5109 F8FF2F C2 30 rep #(PMFLAG.OR.PXFLAG)
		2705	5110 .LONGA on
		2706	5111 .LONGI on
		2707	5112 .MNLIST
		2708	5113 F8FF31 48 pha ; salva A
		2709	5114 F8FF32 DA phx ; salva X
		2710	5115 F8FF33 5A phy ; salva Y
		2711	5116 F8FF34 0B phd
		2712	5117 F8FF35 8B phb ; salva DBR
		2713	5118 F8FF36 4B phk ; DBR = 0 = PBR(K)
		2714	5119 F8FF37 AB plb ; DATA BANK 0
		2715	5120 F8FF38 A9 00 00 lda #0 ; pagina 0
		2716	5121 F8FF3B 5B tcd
		2717	5122 F8FF3C CPU08 ; imposta registri 8 bit
		2718	5123 F8FF3C E2 30 sep #(PMFLAG.OR.PXFLAG)
		2719	5124 .LONGA off
		2720	5125 .LONGI off
		2721	5126 .MNLIST
		2722	5127
		2723	5128 F8FF3E AD 1D FD lda !VIA1+VIAIFR ; flag IFR VIA 1
		2724	5129 F8FF41 10 49 bpl ?100 ; no irq da VIA 1
		2725	5130 F8FF43 4A lsr a ; test CA2 (NMI KEYB)
		2726	5131 F8FF44 90 2C bcc ?50 ; no CA2
		2727	5132 F8FF46 AE 42 FD ldx KBFR+2
		2728	5133 F8FF49 E0 83 cpx #KB_CTRLBREAK
		2729	Tue Jul 17 11:11:08 2018 Page 45
		2730
		2731
		2732
		2733
		2734	5134 F8FF4B D0 08 bne ?02
		2735	5135 F8FF4D A8 tay
		2736	5136 F8FF4E A9 80 lda #$80
		2737	5137 F8FF50 04 4B tsb CtrlBrk
		2738	5138 F8FF52 98 tya
		2739	5139 F8FF53 80 15 bra ?40
		2740	5140 F8FF55 E0 84 ?02: cpx #KB_ALTSYSREQ
		2741	5141 F8FF57 D0 11 bne ?06
		2742	5142 F8FF59 A2 01 ldx #CA2IFRB
		2743	5143 F8FF5B 8E 1D FD stx VIA1+VIAIFR
		2744	5144 F8FF5E 8E 45 FD stx KBCLRNMI ; azzera linea INT
		2745	5145 F8FF61 A8 tay
		2746	5146 F8FF62 A9 40 lda #$40
		2747	5147 F8FF64 04 4B tsb CtrlBrk
		2748	5148 F8FF66 5C 09 00 FF jml ALTSYSMON
		2749	5149 F8FF6A ?06:
		2750	5150 F8FF6A A2 01 ?40: ldx #CA2IFRB
		2751	5151 F8FF6C 8E 1D FD stx VIA1+VIAIFR
		2752	5152 F8FF6F 8E 45 FD stx KBCLRNMI ; azzera linea INT
		2753	5153 F8FF72 4A ?50: lsr a
		2754	5154 F8FF73 4A lsr a
		2755	5155 F8FF74 4A lsr a
		2756	5156 F8FF75 90 15 bcc ?100
		2757	5157 F8FF77 A2 08 ldx #CB2IFRB ; trigger
		2758	5158 F8FF79 8E 1D FD stx VIA1+VIAIFR ; clear irq flag
		2759	5159 F8FF7C A9 01 lda #$01
		2760	5160 F8FF7E 24 4B bit CtrlBrk
		2761	5161 F8FF80 D0 0A bne ?100
		2762	5162 F8FF82 04 4B tsb CtrlBrk
		2763	5163
		2764	5164 F8FF84
		2765	5165 ?51: ;lda VIA1+VIAPRB
		2766	5166 ;cmp VIA1+VIAPRB
		2767	5167 ;bne ?51
		2768	5168 ;and #$10
		2769	5169 ;beq ?51
		2770	5170
		2771	5171 ; OFF command
		2772	5172 ;ldx #RTCEXTCTRLA
		2773	5173 ;stx RTCALE
		2774	5174 ;lda #$08 ; POWERON -> HIGH
		2775	5175 ;tsb RTCDATA
		2776	5176 F8FF84
		2777	5177 F8FF84 22 C3 20 F8 jsl shutdown
		2778	5178 F8FF88 A9 01 lda #$01
		2779	5179 F8FF8A 14 4B trb CtrlBrk
		2780	5180 F8FF8C
		2781	5181
		2782	5182 F8FF8C ?100:
		2783	5183 F8FF8C CPU16 ; ripristina registri 16 bit
		2784	5184 F8FF8C C2 30 rep #(PMFLAG.OR.PXFLAG)
		2785	5185 .LONGA on
		2786	5186 .LONGI on
		2787	5187 .MNLIST
		2788	5188 F8FF8E AB plb ; ripristina DBR
		2789	5189 F8FF8F 2B pld
		2790	5190 F8FF90 7A ply ; ripristina Y
		2791	Tue Jul 17 11:11:08 2018 Page 46
		2792
		2793
		2794
		2795
		2796	5191 F8FF91 FA plx ; ripristina X
		2797	5192 F8FF92 68 pla ; ripristina A
		2798	5193 F8FF93 40 rti
		2799	5194 F8FF94 LONG_OFF
		2800	5195 .LONGA off
		2801	5196 .LONGI off
		2802	5197 .MNLIST
		2803	5198
		2804	5199 ; gestione interrupt linea IRQ (RTI restore P and register size)
		2805	5200 F8FF94 _IRQEntry:
		2806	5201 F8FF94 CPU16 ; salva registri 16 bit
		2807	5202 F8FF94 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2808	5203 .LONGA on
		2809	5204 .LONGI on
		2810	5205 .MNLIST
		2811	5206 F8FF96 48 pha ; salva A
		2812	5207 F8FF97 DA phx ; salva X
		2813	5208 F8FF98 5A phy ; salva Y
		2814	5209 F8FF99 0B phd ; salva DP
		2815	5210 F8FF9A 8B phb ; salva DBR
		2816	5211 F8FF9B 4B phk ; DBR = 0 = PBR(K)
		2817	5212 F8FF9C AB plb ; DATA BANK 0
		2818	5213 F8FF9D A9 00 00 lda #0
		2819	5214 F8FFA0 5B tcd ; imposta pagina 0
		2820	5215 F8FFA1 CPU08 ; imposta registri 8 bit
		2821	5216 F8FFA1 E2 30 sep #(PMFLAG.OR.PXFLAG)
		2822	5217 .LONGA off
		2823	5218 .LONGI off
		2824	5219 .MNLIST
		2825	5220 F8FFA3 AE 47 FD ldx IRQVECTR ; legge vettore IRQ (x2)
		2826	5221 F8FFA6 FC 00 F0 jsr (intsr,x) ; esegue subroutine IntSr
		2827	5222 F8FFA9 CPU16 ; ripristina registri 16 bit
		2828	5223 F8FFA9 C2 30 rep #(PMFLAG.OR.PXFLAG)
		2829	5224 .LONGA on
		2830	5225 .LONGI on
		2831	5226 .MNLIST
		2832	5227 F8FFAB AB plb ; ripristina DBR
		2833	5228 F8FFAC 2B pld ; ripristina DP
		2834	5229 F8FFAD 7A ply ; ripristina Y
		2835	5230 F8FFAE FA plx ; ripristina X
		2836	5231 F8FFAF 68 pla ; ripristina A
		2837	5232 F8FFB0 40 rti
		2838	5233 F8FFB1 LONG_OFF
		2839	5234 .LONGA off
		2840	5235 .LONGI off
		2841	5236 .MNLIST
		2842	5237 F8FFB1
		2843	5238 ;----------------------------------------------------------
		2844	5239 ; ---- VETTORI CPU
		2845	5240 ;----------------------------------------------------------
		2846	5241 F8FFB1
		2847	5242 .SYSVECTRS
		2848	5243 F8FFE0
		2849	5244 ; vettori modo nativo
		2850	5245 F8FFE0 0000 .DW 0 ; FFE0
		2851	5246 F8FFE2 0000 .DW 0 ; FFE2
		2852	5247 F8FFE4 95FE .DW _COPEntry ; FFE4 -> COP
		2853	Tue Jul 17 11:11:08 2018 Page 47
		2854
		2855
		2856
		2857
		2858	5248 F8FFE6 20FF .DW _BRKEntry ; FFE6 -> BRK
		2859	5249 F8FFE8 94FE .DW _Unexpected ; FFE8 -> ABORT (non usato)
		2860	5250 F8FFEA 2FFF .DW _NMIEntry ; FFEA -> NMI
		2861	5251 F8FFEC 94FE .DW _Unexpected ; FFEC -> riservato
		2862	5252 F8FFEE 94FF .DW _IRQEntry ; FFEE -> IRQ
		2863	5253
		2864	5254 ; nel banco $F8
		2865	5255 F8FFF0 _SysStart:
		2866	5256 F8FFF0 4C 86 12 jmp !SysStart
		2867	5257 F8FFF3 00 .DB $00
		2868	5258 F8FFF4
		2869	5259 ; vettori modo emulazione
		2870	5260 F8FFF4 95FE .DW _COPEntry ; FFF4 -> COP
		2871	5261 F8FFF6 94FE .DW _Unexpected ; FFF6 -> riservato
		2872	5262 F8FFF8 94FE .DW _Unexpected ; FFF8 -> ABORT (non usato)
		2873	5263 F8FFFA 2FFF .DW _NMIEntry ; FFFA -> NMI
		2874	5264 F8FFFC 00FE .DW _RSTEntry ; FFFC -> RESET
		2875	5265 F8FFFE 94FF .DW _IRQEntry ; FFFE -> IRQ
		2876	5266
		2877	5267 F90000
		2878	5268 .END _RSTEntry
		2879
		2880
		2881	Lines Assembled : 4746 Errors : 0
		2882
		2883
		2884

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(root)/trunk/sources/lst/F8/start.lst – Rev 1