WebSVN – MB01 Project – Blame – /trunk/sources/lst/F8/sp2.lst

Rev	Author	Line No.	Line
1	-	1	Tue Jul 17 11:00:18 2018 Page 1
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		8
		9	2500 A.D. 65816 Macro Assembler #26960 - Version 5.02g
		10	-----------------------------------------------------
		11
		12	Input Filename : src\F8\sp2.asm
		13	Output Filename : obj\F8\sp2.obj
		14	Listing Has Been Relocated
		15
		16
		17	2605 .LIST on
		18	2606
		19	2607 F8FFB1 .INCLUDE inc\dirp00.inc
		20	2608 ;----------------------------------------------------------
		21	2609 ; DIRP00.ASM
		22	2610 ; PROGETTO: B1601
		23	2611 ;
		24	2612 ; Variabili in Direct Page $00
		25	2613 ;----------------------------------------------------------
		26	2614
		27	2615 ; sezione COMMON -- questo permette di includere il file in piu' file
		28	2616
		29	2617 .LIST on
		30	2618
		31	2619 DIRP00: .SECTION page0, ref_only, common ;Direct-Page 00
		32	2620
		33	2621 000000 .ABSOLUTE ;; inizia sempre da $00
		34	2622 000000 .ORG 0x00
		35	2623 000000
		36	2624 000000 0000 JiffyClk .DW ; contatore 10ms 32 bit
		37	2625 000002 0000 .DW
		38	2626 000004 SysTmr .DS SYSTMRCNT ; system timer 0 (10ms)
		39	2627 000008 SysTMF .DS SYSTMRCNT ; flag timer (80 -> start)
		40	2628 00000C 00 Bnk0Flag .DB ; <7>: flag test RAM banco 0 ok
		41	2629 ; <6>: flag warm reset
		42	2630 00000D 00 RTCFlag .DB
		43	2631
		44	2632 00000E diskstat .DS 2 ; flag device on ata bus #0 & #1
		45	2633 ; <7>: device ready
		46	2634 ; <6>: compact flash device (C.F.)
		47	2635 ; <5>: device identification ok
		48	2636 ; <4>: MBR loaded
		49	2637 ; <3>: valid signature in MBR
		50	2638 ; <2>: first partition found&active
		51	2639 ; <1>:
		52	2640 ; <0>: valid partition flag
		53	2641
		54	2642 ; <7>: device ready
		55	2643 ; <6>: USB device
		56	2644 ; <5>: compact flash device (C.F.)
		57	2645 ; <4>: device identification ok
		58	2646 ; <3>: MBR loaded
		59	2647 ; <2>: first partition found&active
		60	2648 ; <1>: always 1
		61	2649 ; <0>: valid partition flag
		62	2650 000010
		63	Tue Jul 17 11:00:18 2018 Page 2
		64
		65
		66
		67
		68	2651
		69	2652 00000E atadev .EQU diskstat
		70	2653
		71	2654 000010 usbdev .DS 2 ; flag flash disk on usb bus #0
		72	2655 ; <7>: device plugged and ready
		73	2656 ; <6>: always 1
		74	2657 ; <5>: device identification ok
		75	2658 ; <4>: MBR loaded
		76	2659 ; <3>: valid signature in MBR
		77	2660 ; <2>: first partition found&active
		78	2661 ; <1>:
		79	2662 ; <0>: valid partition flag
		80	2663
		81	2664 000012 diskmax .DS 16 ; disk max. sector's
		82	2665 000012 atasec .EQU diskmax
		83	2666 00001A usbsec .EQU diskmax+8
		84	2667
		85	2668
		86	2669 000022 atambr .DS 8 ; data for first partition found in mbr
		87	2670 ; first 3 bytes for start sector of partition
		88	2671 ; last byte for partition type
		89	2672 00002A usbmbr .DS 8
		90	2673
		91	2674 000032 ataprt .DS 8 ; total sec's of first partition
		92	2675 00003A usbprt .DS 8 ; total sec's of first partition
		93	2676
		94	2677
		95	2678 000042 00 usb0ch .DB ; usb0 (ch375/ch376) flag
		96	2679 ; <7>: module on
		97	2680 ; <6>: ch376 flag
		98	2681 ; <5:0>: chip version
		99	2682
		100	2683 000043 00 usb0st .DB ; usb0 status
		101	2684 ; <7>: usb0 host mode ok
		102	2685 ; <6>: flash disk attached flag
		103	2686 ; <5>: usb device attached
		104	2687
		105	2688 000044 00 fdcdrv .DB ; phisycal drive status (drive #0)
		106	2689 ; <7>: disk format established in bit 0&1
		107	2690 ; <6>: double step seek done
		108	2691 ; <5>: trust format bit's (set after ok r/w)
		109	2692 ; <4>: write protect bit (if disk in drive)
		110	2693 ; <3>: don't care
		111	2694 ; <2>: don't care
		112	2695 ; <1>: HD disk if set else DD disk
		113	2696 ; <0>: CBM format if set else IBM format
		114	2697
		115	2698 000045 00 vdrive .DB ; virtual drive status (ram disk, drive #1)
		116	2699 ; <7>: disk format established in bit 0&1
		117	2700 ; <6>: change disk simulation (after format)
		118	2701 ; <5>: don't care
		119	2702 ; <4>: write protect bit (under sw control)
		120	2703 ; <3>: don't care
		121	2704 ; <2>: don't care
		122	2705 ; <1>: HD disk if set else DD disk
		123	2706 ; <0>: CBM format if set else IBM format
		124	2707
		125	Tue Jul 17 11:00:18 2018 Page 3
		126
		127
		128
		129
		130	2708 000046 00 fdcctl .DB ; fdc controller status
		131	2709 ; <7>: drive is attached
		132	2710 ; <6>: drive need recalibration (restore)
		133	2711 ; <5>: FDC controller ok
		134	2712 ; <4>: motor on
		135	2713 ; <3>: dma is active
		136	2714 ; <2>: dma chip ok (post routine)
		137	2715 ; <1>: clock rate (1=HD,0=DD)
		138	2716 ; <0>: disk ready
		139	2717
		140	2718 000047 00 fdctrk .DB ; fd: current seek track
		141	2719 000048 00 fdcerr .DB ; fd: last error code
		142	2720 000049 00 ataerr .DB ; ata: last error code
		143	2721 00004A 00 ataxer .DB ; ata: last extended error code
		144	2722
		145	2723 00004B 00 CtrlBrk .DB ; flag CTRL+BREAK (NMI)
		146	2724
		147	2725 00004C 0000 MemTop .DW ; top memoria RAM
		148	2726 00004E 00 .DB ; banco top mem
		149	2727
		150	2728 00004F 00 DflTxtIn .DB ; device di default text input
		151	2729 000050 00 DflTxtOut .DB ; device di default text output
		152	2730
		153	2731 000051 COPPtr LP ; long pointer for COP decoding
		154	2732 000054 00 COPIdx .DB ; COP signature/index
		155	2733
		156	2734 000055 00 BiosEnt .DB ; flag accesso a bios setup
		157	2735
		158	2736 ; variabili utilizzate da ACIA
		159	2737 000056 spwrk .DS $30
		160	2738
		161	2739 ; bios mem
		162	2740 000086 0000 nsize .DW ; dimensione blocco da allocare
		163	2741 ;bsize .DW ; dimensione vera blocco free
		164	2742 000088 0000 splitsz .DW ; dimensione blocco splittato
		165	2743 00008A 0000 bfree .DW ; puntatore blocco free
		166	2744 00008C 0000 hdrptr .DW ; puntatore header heap
		167	2745
		168	2746 00008E 0000 pbrklv .DW ; current break level of current process
		169	2747 000090 0000 pbrkmin .DW ; minimum breal level of current process
		170	2748 000092 0000 pbrkmax .DW ; maximum breal level of current process
		171	2749 000094
		172	2750 ; bios temp. work area
		173	2751 000094 bwrktmp .DS $28
		174	2752
		175	2753 0000BC 00 coptmp .DB ; temp. used while cop
		176	2754
		177	2755 0000BD 00 tstser .DB ; check ser/usb test board post
		178	2756 ; <7>: VIA2 ok
		179	2757 ; <6>: PICRAM ok
		180	2758 ; <1>: UART 16C550 ok
		181	2759 ; <0>: R65C51 ok
		182	2760
		183	2761
		184	2762 ;crc16 .DW
		185	2763
		186	2764 0000BD .RELATIVE
		187	Tue Jul 17 11:00:18 2018 Page 4
		188
		189
		190
		191
		192	2765
		193	2766 .ENDS
		194	2767
		195	2768 [01] .IFDEF _ACIA_INC_
		196	2769 .INCLUDE INC\SP.INC
		197	2770 [00] .ENDIF
		198	2771
		199	2795 .LIST on
		200	2796
		201	2797 05C000 SOBUFADDR3 .EQU SPOUTBUFF3
		202	2798 05D000 SIBUFADDR3 .EQU SPINBUFF3
		203	2799 001000 SOBUFSIZ3 .EQU $1000
		204	2800 001000 SIBUFSIZ3 .EQU $1000
		205	2801
		206	2802 060000 SOBUFADDR4 .EQU SPOUTBUFF4
		207	2803 068000 SIBUFADDR4 .EQU SPINBUFF4
		208	2804 ;SOBUFSIZ4 .EQU $1000
		209	2805 ;SIBUFSIZ4 .EQU $1000
		210	2806 008000 SOBUFSIZ4 .EQU $8000
		211	2807 008000 SIBUFSIZ4 .EQU $8000
		212	2808
		213	2809 000200 NGUARD31 .EQU $0200 ; numero bytes di guardia buffer RX XON/XOFF
		214	2810 000100 NGUARD32 .EQU $0100 ; numero bytes di guardia buffer RX handshake
		215	2811 000800 NFREE31 .EQU $0800 ; minimo posto in coda RX per cancellare pausa remota
		216	2812 000400 NFREE32 .EQU $0400
		217	2813
		218	2814 ;---------------------------------------------------------------------------
		219	2815 ; direct page var's for test serial ports/usb handling
		220	2816 ;---------------------------------------------------------------------------
		221	2817
		222	2818 DPSP2: .SECTION page0, common, ref_only ;UART D.P.
		223	2819
		224	2820 000000 00 usbslv .DB ; <7>: plugged-in, <6>: plug-in pending
		225	2821 000001 00 usbum .DB ; <7>: pending message, <6>: connected
		226	2822 000002 00 usbcnt1 .DB ; timeout UM245 plug-in detection
		227	2823 000003 usbbuf .DS 8
		228	2824 00000B 00 usbtim .DB
		229	2825 00000C 00 usbcnt .DB
		230	2826 00000D 00 usbmst .DB
		231	2827 00000E 0000 usbsiz .DW
		232	2828 000010 usbptr LP
		233	2829 000013 00 usbtmp .DB
		234	2830 000014 00 usbcmp .DB
		235	2831
		236	2832 ; serial port 65C51
		237	2833 000015 00 spmode3 .DB ; <7>: 0=no handshake, 1=handshake
		238	2834 ; <6>: 0=software/1=hardware handshake
		239	2835 ; <5>: not used
		240	2836 ; <4>: not used
		241	2837 ; <3>: 0=odd parity, 1=even parity
		242	2838 ; <2>: 0=no parity, 1=parity as specified
		243	2839 ; by bit <3>
		244	2840 ; <1:0> : baud rate
		245	2841 ; 00 = 19200
		246	2842 ; 01 = 38400
		247	2843 ; 10 = 57600
		248	2844 ; 11 = 115200
		249	Tue Jul 17 11:00:18 2018 Page 5
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		251
		252
		253
		254	2845 000016
		255	2846 000016 00 splin3 .DB ; <7>: /CTS line level
		256	2847 ; <6>: /DSR line status
		257	2848 000017
		258	2849 000017 00 sppause3 .DB
		259	2850 000018 00 spout3 .DB
		260	2851 000019 00 spstat3 .DB ; staus
		261	2852 ; <7>: rx error (data discarded)
		262	2853 ; <6>: rx buffer overflow
		263	2854 ; <5>: remote disconnession (/DSR line = 1)
		264	2855 ; <4>: output buffer overflow
		265	2856 ; <3>: not used
		266	2857 ; <2>: framing error
		267	2858 ; <1>: parity error
		268	2859 ; <0>: overrun error
		269	2860
		270	2861 00001A 00 sptmp3 .DB
		271	2862
		272	2863 00001B 0000 ibuftail3 .DW
		273	2864 00001D 0000 ibufhead3 .DW
		274	2865 00001F 0000 obuftail3 .DW
		275	2866 000021 0000 obufhead3 .DW
		276	2867 000023 0000 ibufcnt3 .DW
		277	2868 000025 0000 obufcnt3 .DW
		278	2869 000027 0000 icntmin3 .DW
		279	2870 000029 0000 icntmax3 .DW
		280	2871
		281	2872 ; serial port 16C550
		282	2873 00002B 00 spmode4 .DB ; <7>: 0=no handshake, 1=handshake
		283	2874 ; <6>: 0=software/1=hardware handshake
		284	2875 ; <5>: not used
		285	2876 ; <4>: not used
		286	2877 ; <3>: 0=odd parity, 1=even parity
		287	2878 ; <2>: 0=no parity, 1=parity as specified
		288	2879 ; by bit <3>
		289	2880 ; <1:0> : baud rate
		290	2881 ; 00 = 19200
		291	2882 ; 01 = 38400
		292	2883 ; 10 = 57600
		293	2884 ; 11 = 115200
		294	2885 00002C
		295	2886 00002C 00 splin4 .DB ; <7>: /DSR line level
		296	2887 ; <6>: /CTS line status
		297	2888 00002D
		298	2889 00002D 00 sppause4 .DB
		299	2890 00002E 00 spout4 .DB
		300	2891 00002F 00 spstat4 .DB ; staus
		301	2892 ; <7>: rx error (data discarded)
		302	2893 ; <6>: rx buffer overflow
		303	2894 ; <5>: remote disconnession (/DSR line = 1)
		304	2895 ; <4>: output buffer overflow
		305	2896 ; <3>: break
		306	2897 ; <2>: framing error
		307	2898 ; <1>: parity error
		308	2899 ; <0>: overrun error
		309	2900
		310	2901 000030 00 sptmp4 .DB
		311	Tue Jul 17 11:00:18 2018 Page 6
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		314
		315
		316	2902
		317	2903 000031 0000 ibuftail4 .DW
		318	2904 000033 0000 ibufhead4 .DW
		319	2905 000035 0000 obuftail4 .DW
		320	2906 000037 0000 obufhead4 .DW
		321	2907 000039 0000 ibufcnt4 .DW
		322	2908 00003B 0000 obufcnt4 .DW
		323	2909 00003D 0000 icntmin4 .DW
		324	2910 00003F 0000 icntmax4 .DW
		325	2911
		326	2912 000041 00 spcnt4 .DB
		327	2913 000042 00 uartlsr .DB
		328	2914 000043 00 uartiir .DB
		329	2915
		330	2916 000044 usb0name .DS 36
		331	2917
		332	2918 .ENDS
		333	2919
		334	2923 .LIST on
		335	2924
		336	2925 .CODEF8
		337	2926 F80ABC
		338	2927 .LONGA off
		339	2928 .LONGI off
		340	2929
		341	2930 ; set serial port #2 - 65C51
		342	2931 ; A=mode
		343	2932 F80ABC spset2:
		344	2933 F80ABC 78 sei ; disable interrupt
		345	2934 F80ABD 0B phd
		346	2935 F80ABE F4 00 05 pea #DP05ADDR
		347	2936 F80AC1 2B pld
		348	2937 F80AC2 85 15 sta spmode3 ; save mode
		349	2938 F80AC4 AA tax
		350	2939 F80AC5 8D 29 FC sta !ACIASR ; software reset
		351	2940 F80AC8 A9 02 lda #ACIACMDOFF ; disable all
		352	2941 F80ACA 8D 2A FC sta !ACIACMD
		353	2942 F80ACD AD 28 FC lda !ACIADR ; clear flags
		354	2943 F80AD0 AD 29 FC lda !ACIASR
		355	2944 F80AD3 29 40 and #01000000B ; get /DSR status
		356	2945 F80AD5 F0 04 beq ?dsrl
		357	2946 F80AD7 04 16 tsb splin3 ; /DSR high
		358	2947 F80AD9 80 04 bra ?cts
		359	2948 F80ADB A9 40 ?dsrl: lda #01000000B
		360	2949 F80ADD 14 16 trb splin3 ; /DSR low
		361	2950 F80ADF A0 80 ?cts: ldy #$80
		362	2951 F80AE1 A9 08 lda #00001000B ; check /CTS line level: PA<3>
		363	2952 F80AE3 2C 1F FC bit !VIA2+VIAPRANH
		364	2953 F80AE6 F0 05 beq ?ctsl ; /CTS is low
		365	2954 F80AE8 98 tya
		366	2955 F80AE9 04 16 tsb splin3 ; /CTS is high
		367	2956 F80AEB 80 03 bra ?br
		368	2957 F80AED 98 ?ctsl: tya
		369	2958 F80AEE 14 16 trb splin3 ; /CTS is low
		370	2959 F80AF0 8A ?br: txa ; <1:0> = baud rate select
		371	2960 F80AF1 29 03 and #00000011B
		372	2961 F80AF3 85 1A sta sptmp3
		373	Tue Jul 17 11:00:18 2018 Page 7
		374
		375
		376
		377
		378	2962 F80AF5 AD 1F FC lda !VIA2+VIAPRANH
		379	2963 F80AF8 29 F8 and #11111000B ; /RTS low
		380	2964 F80AFA 05 1A ora sptmp3
		381	2965 F80AFC 8D 1F FC sta !VIA2+VIAPRANH
		382	2966 F80AFF A9 10 lda #00010000B ; 8 bits, 1 stop bit, divisor = 1/16
		383	2967 F80B01 8D 2B FC sta !ACIACTRL
		384	2968 F80B04 8A txa ; mode
		385	2969 F80B05 29 0C and #00001100B ; mask on bits 3 & 2 (parity mode)
		386	2970 F80B07 0A asl a ; shift <3:2> to <6:5>
		387	2971 F80B08 0A asl a
		388	2972 F80B09 0A asl a
		389	2973 F80B0A 09 05 ora #00000101B ; enable all int., /DTR=low
		390	2974 F80B0C 85 1A sta sptmp3 ; byte for command register
		391	2975 F80B0E 64 17 stz sppause3 ; init work area
		392	2976 F80B10 64 18 stz spout3
		393	2977 F80B12 64 19 stz spstat3
		394	2978 F80B14 24 15 bit spmode3
		395	2979 F80B16 CPU16 ; init buffer's pointer's
		396	2980 F80B16 C2 30 rep #(PMFLAG.OR.PXFLAG)
		397	2981 .LONGA on
		398	2982 .LONGI on
		399	2983 .MNLIST
		400	2984 F80B18 70 08 bvs ?hw ; hardware handshake
		401	2985 F80B1A A9 00 02 lda #NGUARD31
		402	2986 F80B1D A0 00 08 ldy #NFREE31
		403	2987 F80B20 80 06 bra ?do
		404	2988 F80B22 A9 00 01 ?hw: lda #NGUARD32
		405	2989 F80B25 A0 00 04 ldy #NFREE32
		406	2990 F80B28 85 29 ?do: sta icntmax3
		407	2991 F80B2A 84 27 sty icntmin3
		408	2992 F80B2C 38 sec
		409	2993 F80B2D A9 00 10 lda #SIBUFSIZ3
		410	2994 F80B30 E5 29 sbc icntmax3
		411	2995 F80B32 85 29 sta icntmax3
		412	2996 F80B34 64 1B stz ibuftail3
		413	2997 F80B36 64 1D stz ibufhead3
		414	2998 F80B38 64 23 stz ibufcnt3
		415	2999 F80B3A 64 1F stz obuftail3
		416	3000 F80B3C 64 21 stz obufhead3
		417	3001 F80B3E 64 25 stz obufcnt3
		418	3002 F80B40 CPU08
		419	3003 F80B40 E2 30 sep #(PMFLAG.OR.PXFLAG)
		420	3004 .LONGA off
		421	3005 .LONGI off
		422	3006 .MNLIST
		423	3007 F80B42 24 15 bit spmode3
		424	3008 F80B44 10 06 bpl ?ok ; no handshake
		425	3009 F80B46 50 04 bvc ?ok ; software handshake
		426	3010 F80B48 24 16 bit splin3 ; check /DSR line
		427	3011 F80B4A 50 00 bvc ?ok ; remote terminal is connected
		428	3012 ;lda #$20
		429	3013 ;tsb spstat3 ; remote terminal not connected now
		430	3014 F80B4C AD 28 FC ?ok: lda .ABS.ACIADR ; discard any pending received data
		431	3015 F80B4F AD 29 FC lda .ABS.ACIASR ; read current interrupt status
		432	3016 F80B52 A5 1A lda sptmp3 ; enable interrupts
		433	3017 F80B54 8D 2A FC sta .ABS.ACIACMD
		434	3018 F80B57 2B pld
		435	Tue Jul 17 11:00:18 2018 Page 8
		436
		437
		438
		439
		440	3019 F80B58 58 cli
		441	3020 F80B59 60 rts
		442	3021
		443	3022 ; reset serial port #2 - 65C51
		444	3023 F80B5A spres2:
		445	3024 F80B5A 8D 29 FC sta !ACIASR ; software reset
		446	3025 F80B5D A9 02 lda #ACIACMDOFF ; disable all
		447	3026 F80B5F 8D 2A FC sta !ACIACMD
		448	3027 F80B62 AD 28 FC lda !ACIADR ; clear flags
		449	3028 F80B65 AD 29 FC lda !ACIASR
		450	3029 F80B68 60 rts
		451	3030 F80B69
		452	3031 ; send A to serial port 65C51
		453	3032 F80B69 spput2:
		454	3033 F80B69 78 sei ; disable interrupt
		455	3034 F80B6A 0B phd
		456	3035 F80B6B F4 00 05 pea #DP05ADDR
		457	3036 F80B6E 2B pld
		458	3037 F80B6F 86 1A stx sptmp3 ; save X reg.
		459	3038 F80B71 A0 00 ldy #0 ; Y = 0
		460	3039 F80B73 INDEX16
		461	3040 F80B73 C2 10 rep #PXFLAG
		462	3041 .LONGI on
		463	3042 .MNLIST
		464	3043 F80B75 A6 25 ldx obufcnt3
		465	3044 F80B77 E0 00 10 cpx #SOBUFSIZ3 ; output buffer is full?
		466	3045 F80B7A 90 07 bcc ?str ; no, store byte
		467	3046 F80B7C 24 16 bit splin3
		468	3047 F80B7E 50 2D bvc ?done ; exit with CF=1, Y=0: output buffer is full
		469	3048 F80B80 88 dey
		470	3049 F80B81 80 2A bra ?done ; exit with CF=1, Y=$FF: remote terminal off
		471	3050 F80B83 E8 ?str: inx ; update count
		472	3051 F80B84 86 25 stx obufcnt3
		473	3052 F80B86 A6 1F ldx obuftail3 ; output buffer tail pointer
		474	3053 F80B88 9F 00 C0 05 sta >SOBUFADDR3,x ; store byte in output buffer
		475	3054 F80B8C E8 inx ; update tail pointer
		476	3055 F80B8D E0 00 10 cpx #SOBUFSIZ3
		477	3056 F80B90 90 01 bcc ?upd
		478	3057 F80B92 BB tyx ; circular queue
		479	3058 F80B93 86 1F ?upd: stx obuftail3
		480	3059
		481	3060 ; here at least one byte to send so check if tx interrupt is enabled
		482	3061 ;
		483	3062 F80B95 EB xba ; save A
		484	3063 F80B96 AD 2A FC lda !ACIACMD
		485	3064 F80B99 89 04 bit #00000100B ; check CMD<2>
		486	3065 F80B9B D0 0E bne ?xba ; tx interrupt enabled
		487	3066 F80B9D 24 17 bit sppause3
		488	3067 F80B9F 70 0A bvs ?xba ; local pause is on, can't enable tx interrupt
		489	3068 F80BA1 A9 08 lda #00001000B ; first clear CMD<3>
		490	3069 F80BA3 1C 2A FC trb !ACIACMD
		491	3070 F80BA6 A9 04 lda #00000100B ; then set CMD<2>
		492	3071 F80BA8 0C 2A FC tsb !ACIACMD ; re-enable tx interrupt
		493	3072 F80BAB EB ?xba: xba ; return A = sent data
		494	3073 F80BAC 18 clc ; no error
		495	3074 F80BAD ?done: INDEX08
		496	3075 F80BAD E2 10 sep #PXFLAG
		497	Tue Jul 17 11:00:18 2018 Page 9
		498
		499
		500
		501
		502	3076 .LONGI off
		503	3077 .MNLIST
		504	3078 F80BAF A6 1A ldx sptmp3 ; restore X reg.
		505	3079 F80BB1 2B pld
		506	3080 F80BB2 58 cli
		507	3081 F80BB3 60 rts
		508	3082
		509	3083 F80BB4 spget2:
		510	3084 F80BB4 78 sei ; disable interrupt
		511	3085 F80BB5 0B phd
		512	3086 F80BB6 F4 00 05 pea #DP05ADDR
		513	3087 F80BB9 2B pld
		514	3088 F80BBA 38 sec ; assume error
		515	3089 F80BBB 86 1A stx sptmp3 ; save X reg.
		516	3090 F80BBD A5 19 lda spstat3 ; rx pending error?
		517	3091 F80BBF 30 47 bmi ?done ; yes, exit
		518	3092 F80BC1 A9 00 lda #0 ; assume no data available
		519	3093 F80BC3 A8 tay ; Y = 0
		520	3094 F80BC4 INDEX16
		521	3095 F80BC4 C2 10 rep #PXFLAG
		522	3096 .LONGI on
		523	3097 .MNLIST
		524	3098 F80BC6 A6 23 ldx ibufcnt3 ; available new data?
		525	3099 F80BC8 F0 3E beq ?done ; input queue is empty (exit with CF=1, A=0)
		526	3100 F80BCA CA dex ; update count
		527	3101 F80BCB 86 23 stx ibufcnt3
		528	3102 F80BCD A6 1D ldx ibufhead3 ; head input buffer pointer
		529	3103 F80BCF BF 00 D0 05 lda >SIBUFADDR3,x ; get byte from queue
		530	3104 F80BD3 E8 inx ; update head pointer
		531	3105 F80BD4 E0 00 10 cpx #SIBUFSIZ3
		532	3106 F80BD7 90 01 bcc ?upd
		533	3107 F80BD9 BB tyx ; circular queue
		534	3108 F80BDA 86 1D ?upd: stx ibufhead3
		535	3109 F80BDC 24 17 bit sppause3 ; remote pause is on?
		536	3110 F80BDE 10 27 bpl ?ok ; no
		537	3111 F80BE0 A6 23 ldx ibufcnt3
		538	3112 F80BE2 E4 27 cpx icntmin3 ; can clear remote pause?
		539	3113 F80BE4 B0 21 bcs ?ok ; no
		540	3114 F80BE6 24 15 bit spmode3 ; handshake is on?
		541	3115 F80BE8 10 1D bpl ?ok ; no
		542	3116 F80BEA EB xba ; save data
		543	3117 F80BEB 70 10 bvs ?hw ; hardware handshake
		544	3118 F80BED A9 11 lda #SPXON ; software handshake: send an XON
		545	3119 F80BEF 85 18 sta spout3 ; XON is deffered
		546	3120 F80BF1 A9 0C lda #00001100B ; re-enable tx interrupt
		547	3121 F80BF3 1C 2A FC trb !ACIACMD
		548	3122 F80BF6 A9 04 lda #00000100B
		549	3123 F80BF8 0C 2A FC tsb !ACIACMD
		550	3124 F80BFB 80 09 bra ?xba
		551	3125 F80BFD A9 04 ?hw: lda #$04 ; hardware handshake: set RTS=0
		552	3126 F80BFF 1C 1F FC trb .ABS.VIA2+VIAPRANH
		553	3127 F80C02 A9 80 lda #$80
		554	3128 F80C04 14 17 trb sppause3 ; clear remote pause flag
		555	3129 F80C06 EB ?xba: xba ; recover data
		556	3130 F80C07 18 ?ok: clc
		557	3131 F80C08 ?done: INDEX08
		558	3132 F80C08 E2 10 sep #PXFLAG
		559	Tue Jul 17 11:00:18 2018 Page 10
		560
		561
		562
		563
		564	3133 .LONGI off
		565	3134 .MNLIST
		566	3135 F80C0A A6 1A ldx sptmp3 ; restore X reg.
		567	3136 F80C0C 2B pld
		568	3137 F80C0D 58 cli
		569	3138 F80C0E 60 rts ; CF=1 & A=0 mean: no data available
		570	3139
		571	3140 ;------------------
		572	3141
		573	3142 ; set serial port 16C550
		574	3143 ; A=mode
		575	3144 F80C0F spset3:
		576	3145 F80C0F 78 sei ; disable interrupt
		577	3146 F80C10 0B phd
		578	3147 F80C11 F4 00 05 pea #DP05ADDR
		579	3148 F80C14 2B pld
		580	3149 F80C15 85 2B sta spmode4 ; save mode
		581	3150 F80C17 9C 23 FC stz !UART_LCR
		582	3151 F80C1A 9C 21 FC stz !UART_IER ; disable all UART interrupts
		583	3152 F80C1D 9C 24 FC stz !UART_MCR ; /RTS and /DTR high
		584	3153 F80C20 9C 22 FC stz !UART_FCR ; disable FIFO
		585	3154 F80C23 AE 20 FC ldx .ABS.UART_RXTX ; clear any pending interrupt
		586	3155 F80C26 AE 25 FC ldx .ABS.UART_LSR
		587	3156 F80C29 AE 22 FC ldx .ABS.UART_IIR
		588	3157 F80C2C A2 80 ldx #$80 ; set DLAB = 1 in LCR
		589	3158 F80C2E 8E 23 FC stx .ABS.UART_LCR
		590	3159 F80C31 A8 tay ; save mode
		591	3160 F80C32 29 03 and #00000011B ; baud rate select
		592	3161 F80C34 AA tax
		593	3162 F80C35 BF A8 0C F8 lda >?div,x ; select divisor
		594	3163 F80C39 8D 20 FC sta !UART_DLL ; set low latch
		595	3164 F80C3C 9C 21 FC stz !UART_DLH ; set high latch
		596	3165 F80C3F 98 tya ; mode
		597	3166 F80C40 29 0C and #00001100B ; mask on bits 3 & 2 (parity mode)
		598	3167 F80C42 0A asl a ; shift <3:2> to <4:3>
		599	3168 F80C43 09 03 ora #00000011B ; 8N1 (8 bits data, 1 stop bit)
		600	3169 F80C45 8D 23 FC sta !UART_LCR
		601	3170 F80C48 AD 26 FC lda !UART_MSR ; get /DSR & /CTS status
		602	3171 F80C4B AA tax
		603	3172 F80C4C 0A asl a
		604	3173 F80C4D 0A asl a ; <7>: /DSR, <6>: /CTS
		605	3174 F80C4E 29 C0 and #11000000B
		606	3175 F80C50 49 C0 eor #11000000B
		607	3176 F80C52 85 2C sta splin4 ; update line status
		608	3177 F80C54 64 2D stz sppause4 ; init work area
		609	3178 F80C56 64 2F stz spstat4
		610	3179 F80C58 A9 01 lda #1 ; set tx count = 1
		611	3180 F80C5A 85 41 sta spcnt4
		612	3181 F80C5C CPU16 ; init buffer's pointer's
		613	3182 F80C5C C2 30 rep #(PMFLAG.OR.PXFLAG)
		614	3183 .LONGA on
		615	3184 .LONGI on
		616	3185 .MNLIST
		617	3186 F80C5E A9 00 01 lda #NGUARD32
		618	3187 F80C61 A0 00 04 ldy #NFREE32
		619	3188 F80C64 85 3F sta icntmax4
		620	3189 F80C66 84 3D sty icntmin4
		621	Tue Jul 17 11:00:18 2018 Page 11
		622
		623
		624
		625
		626	3190 F80C68 38 sec
		627	3191 F80C69 A9 00 80 lda #SIBUFSIZ4
		628	3192 F80C6C E5 3F sbc icntmax4
		629	3193 F80C6E 85 3F sta icntmax4
		630	3194 F80C70 64 31 stz ibuftail4
		631	3195 F80C72 64 33 stz ibufhead4
		632	3196 F80C74 64 39 stz ibufcnt4
		633	3197 F80C76 64 35 stz obuftail4
		634	3198 F80C78 64 37 stz obufhead4
		635	3199 F80C7A 64 3B stz obufcnt4
		636	3200 F80C7C CPU08
		637	3201 F80C7C E2 30 sep #(PMFLAG.OR.PXFLAG)
		638	3202 .LONGA off
		639	3203 .LONGI off
		640	3204 .MNLIST
		641	3205 F80C7E A9 03 lda #00000011B ; set /RTS = /DTR low
		642	3206 F80C80 8D 24 FC sta !UART_MCR
		643	3207 F80C83 A9 20 lda #$20
		644	3208 F80C85 24 2B bit spmode4
		645	3209 F80C87 D0 0E bne ?nof ; no fifo
		646	3210 F80C89 A9 01 lda #1
		647	3211 F80C8B 8D 22 FC sta !UART_FCR
		648	3212 F80C8E A9 87 lda #10000111B ; enable fifo, reset rx/tx fifo, trigger level = 8
		649	3213 F80C90 8D 22 FC sta !UART_FCR ; rx fifo trigger = 8
		650	3214 F80C93 A9 10 lda #16 ; set tx count = 16 in FIFO mode
		651	3215 F80C95 85 41 sta spcnt4
		652	3216 F80C97 AD 25 FC ?nof: lda !UART_LSR ; again reset all interrupts
		653	3217 F80C9A AD 26 FC lda !UART_MSR
		654	3218 F80C9D AD 22 FC lda !UART_IIR
		655	3219 F80CA0 A9 0F lda #00001111B ; enable all interrupts
		656	3220 F80CA2 8D 21 FC sta !UART_IER
		657	3221 F80CA5 2B pld
		658	3222 F80CA6 58 cli
		659	3223 F80CA7 60 rts
		660	3224
		661	3225 ; 19.200, 38.400, 57.600, 115.200
		662	3226 F80CA8 06 03 02 01 ?div: .DB 6, 3, 2, 1
		663	3227
		664	3228 F80CAC spres3:
		665	3229 ;stz !UART_LCR
		666	3230 F80CAC 9C 21 FC stz !UART_IER ; clear all interrupts
		667	3231 ;stz !UART_MCR ; /RTS and /DTR high
		668	3232 F80CAF A9 87 lda #10000111B ; enable fifo, reset rx/tx fifo
		669	3233 F80CB1 9C 22 FC stz !UART_FCR ; rx fifo trigger = 8
		670	3234 F80CB4 AD 25 FC lda !UART_LSR
		671	3235 F80CB7 AD 26 FC lda !UART_MSR
		672	3236 F80CBA 60 rts
		673	3237
		674	3238 ; send A to serial port 16C550
		675	3239 F80CBB spput3:
		676	3240 F80CBB 78 sei ; disable interrupt
		677	3241 F80CBC 0B phd
		678	3242 F80CBD F4 00 05 pea #DP05ADDR
		679	3243 F80CC0 2B pld
		680	3244 F80CC1 86 30 stx sptmp4 ; save X reg.
		681	3245 F80CC3 A0 00 ldy #0 ; Y = 0
		682	3246 F80CC5 INDEX16
		683	Tue Jul 17 11:00:18 2018 Page 12
		684
		685
		686
		687
		688	3247 F80CC5 C2 10 rep #PXFLAG
		689	3248 .LONGI on
		690	3249 .MNLIST
		691	3250 F80CC7 A6 3B ldx obufcnt4
		692	3251 F80CC9 E0 00 80 cpx #SOBUFSIZ4 ; output buffer is full?
		693	3252 F80CCC 90 17 bcc ?str ; no, store byte
		694	3253 F80CCE 24 2C bit splin4 ; test /DSR line status
		695	3254 F80CD0 30 09 bmi ?ofl ; remote terminal disconnected
		696	3255 F80CD2 EB xba ; save A
		697	3256 F80CD3 A9 02 lda #00000010B ; enable TX interrupt...
		698	3257 F80CD5 0C 21 FC tsb !UART_IER ; ... hoping that ISR can make room in output buffer
		699	3258 F80CD8 EB xba
		700	3259 F80CD9 80 24 bra ?done ; exit with CF=1, Y=0: output buffer is full
		701	3260 F80CDB 88 ?ofl: dey ; /DSR high
		702	3261 F80CDC EB xba
		703	3262 F80CDD A9 02 lda #00000010B
		704	3263 F80CDF 1C 21 FC trb !UART_IER ; disable tx interrupt
		705	3264 F80CE2 EB xba
		706	3265 F80CE3 80 1A bra ?done ; exit with CF=1, Y=$FF: remote terminal offline
		707	3266 F80CE5 E8 ?str: inx ; update count
		708	3267 F80CE6 86 3B stx obufcnt4
		709	3268 F80CE8 A6 37 ldx obufhead4 ; output buffer head pointer
		710	3269 F80CEA 9F 00 00 06 sta >SOBUFADDR4,x ; store byte in output buffer
		711	3270 F80CEE E8 inx ; update head pointer
		712	3271 F80CEF E0 00 80 cpx #SOBUFSIZ4
		713	3272 F80CF2 90 01 bcc ?upd
		714	3273 F80CF4 BB tyx ; circular queue
		715	3274 F80CF5 86 37 ?upd: stx obufhead4
		716	3275 F80CF7 EB xba
		717	3276 ;lda #00000010B
		718	3277 ;trb !UART_IER ; re-enable tx interrupt
		719	3278 F80CF8 A9 02 lda #00000010B
		720	3279 F80CFA 0C 21 FC tsb !UART_IER ; re-enable tx interrupt
		721	3280 F80CFD EB xba ; return A = sent data
		722	3281 F80CFE 18 clc ; no error
		723	3282 F80CFF ?done: INDEX08
		724	3283 F80CFF E2 10 sep #PXFLAG
		725	3284 .LONGI off
		726	3285 .MNLIST
		727	3286 F80D01 A6 30 ldx sptmp4 ; restore X reg.
		728	3287 F80D03 2B pld
		729	3288 F80D04 58 cli
		730	3289 F80D05 60 rts
		731	3290
		732	3291 F80D06 spget3:
		733	3292 F80D06 78 sei ; disable interrupt
		734	3293 F80D07 0B phd
		735	3294 F80D08 F4 00 05 pea #DP05ADDR
		736	3295 F80D0B 2B pld
		737	3296 F80D0C 38 sec ; assume error
		738	3297 F80D0D 86 30 stx sptmp4 ; save X reg.
		739	3298 F80D0F A5 2F lda spstat4 ; rx pending error?
		740	3299 F80D11 30 3A bmi ?done ; yes, exit (CF = 1, A = error code)
		741	3300 F80D13 A9 00 lda #0 ; assume no data available
		742	3301 F80D15 A8 tay ; Y = 0
		743	3302 F80D16 INDEX16
		744	3303 F80D16 C2 10 rep #PXFLAG
		745	Tue Jul 17 11:00:18 2018 Page 13
		746
		747
		748
		749
		750	3304 .LONGI on
		751	3305 .MNLIST
		752	3306 F80D18 A6 39 ldx ibufcnt4 ; available new data?
		753	3307 F80D1A F0 31 beq ?done ; input queue is empty (exit with CF=1, A=0)
		754	3308 F80D1C CA dex ; update count
		755	3309 F80D1D 86 39 stx ibufcnt4
		756	3310 F80D1F A6 31 ldx ibuftail4 ; tail input buffer pointer
		757	3311 F80D21 BF 00 80 06 lda >SIBUFADDR4,x ; get byte from queue
		758	3312 F80D25 E8 inx ; update tail pointer
		759	3313 F80D26 E0 00 80 cpx #SIBUFSIZ4
		760	3314 F80D29 90 01 bcc ?upd
		761	3315 F80D2B BB tyx ; circular queue
		762	3316 F80D2C 86 31 ?upd: stx ibuftail4
		763	3317 F80D2E 24 2B bit spmode4 ; handshake is on?
		764	3318 F80D30 10 1A bpl ?ok ; no, exit
		765	3319 F80D32 24 2D bit sppause4 ; remote pause is on?
		766	3320 F80D34 10 16 bpl ?ok ; no, exit
		767	3321 F80D36 A6 39 ldx ibufcnt4
		768	3322 F80D38 E4 3D cpx icntmin4 ; can clear remote pause?
		769	3323 F80D3A B0 10 bcs ?ok ; no, exit
		770	3324 F80D3C EB xba ; save data
		771	3325 F80D3D A9 02 lda #00000010B ; hardware handshake...
		772	3326 F80D3F 0C 24 FC tsb !UART_MCR ; ...set /RTS=0
		773	3327 F80D42 A9 80 lda #$80
		774	3328 F80D44 14 2D trb sppause4 ; clear remote pause flag
		775	3329 F80D46 A9 02 lda #00000010B ; set IER<1>
		776	3330 F80D48 0C 21 FC tsb !UART_IER ; re-enable tx interrupt
		777	3331 F80D4B EB xba ; recover data
		778	3332 F80D4C 18 ?ok: clc ; no error
		779	3333 F80D4D ?done: CPU08
		780	3334 F80D4D E2 30 sep #(PMFLAG.OR.PXFLAG)
		781	3335 .LONGA off
		782	3336 .LONGI off
		783	3337 .MNLIST
		784	3338 F80D4F A6 30 ldx sptmp4 ; restore X reg.
		785	3339 F80D51 2B pld
		786	3340 F80D52 58 cli
		787	3341 F80D53 60 rts ; CF=1 & A=0 mean: no data available
		788	3342
		789	3343 ;------------------
		790	3344
		791	3345 F80D54 lspget2:
		792	3346 .PUBLIC lspget2
		793	3347 F80D54 8B phb ; save DBR
		794	3348 F80D55 A0 00 ldy #0 ; set DBR = $00
		795	3349 F80D57 5A phy
		796	3350 F80D58 AB plb
		797	3351 F80D59 9B txy
		798	3352 F80D5A D0 05 bne ?get2
		799	3353 F80D5C 20 06 0D jsr spget3
		800	3354 F80D5F AB plb
		801	3355 F80D60 6B rtl
		802	3356 F80D61 20 B4 0B ?get2: jsr spget2
		803	3357 F80D64 AB plb
		804	3358 F80D65 6B rtl
		805	3359 F80D66
		806	3360 F80D66 lspput2:
		807	Tue Jul 17 11:00:18 2018 Page 14
		808
		809
		810
		811
		812	3361 .PUBLIC lspput2
		813	3362 F80D66 8B phb ; save DBR
		814	3363 F80D67 A0 00 ldy #0 ; set DBR = $00
		815	3364 F80D69 5A phy
		816	3365 F80D6A AB plb
		817	3366 F80D6B 9B txy
		818	3367 F80D6C D0 05 bne ?put2
		819	3368 F80D6E 20 BB 0C jsr spput3
		820	3369 F80D71 AB plb
		821	3370 F80D72 6B rtl
		822	3371 F80D73 20 69 0B ?put2: jsr spput2
		823	3372 F80D76 AB plb
		824	3373 F80D77 6B rtl
		825	3374
		826	3375 F80D78 lspset2:
		827	3376 .PUBLIC lspset2
		828	3377 F80D78 8B phb ; save DBR
		829	3378 F80D79 A0 00 ldy #0 ; set DBR = $00
		830	3379 F80D7B 5A phy
		831	3380 F80D7C AB plb
		832	3381 F80D7D 9B txy
		833	3382 F80D7E D0 05 bne ?set2
		834	3383 F80D80 20 0F 0C jsr spset3
		835	3384 F80D83 AB plb
		836	3385 F80D84 6B rtl
		837	3386 F80D85 20 BC 0A ?set2: jsr spset2
		838	3387 F80D88 AB plb
		839	3388 F80D89 6B rtl
		840	3389
		841	3390 F80D8A lspres2:
		842	3391 .PUBLIC lspres2
		843	3392 F80D8A 8B phb ; save DBR
		844	3393 F80D8B A0 00 ldy #0 ; set DBR = $00
		845	3394 F80D8D 5A phy
		846	3395 F80D8E AB plb
		847	3396 F80D8F 9B txy
		848	3397 F80D90 D0 05 bne ?res2
		849	3398 F80D92 20 AC 0C jsr spres3
		850	3399 F80D95 AB plb
		851	3400 F80D96 6B rtl
		852	3401 F80D97 20 5A 0B ?res2: jsr spres2
		853	3402 F80D9A AB plb
		854	3403 F80D9B 6B rtl
		855	3404
		856	3405 F80D9C test0:
		857	3406 F80D9C 78 sei
		858	3407 F80D9D 0B phd
		859	3408 F80D9E F4 00 05 pea #DP05ADDR
		860	3409 F80DA1 2B pld
		861	3410 F80DA2 85 30 sta sptmp4
		862	3411 F80DA4 A9 00 lda #0
		863	3412 F80DA6 8D 22 FC sta !UART_FCR
		864	3413 F80DA9
		865	3414 F80DA9 A5 30 lda sptmp4
		866	3415 F80DAB 3A ?00: dec a
		867	3416 F80DAC D0 FD bne ?00
		868	3417 F80DAE
		869	Tue Jul 17 11:00:18 2018 Page 15
		870
		871
		872
		873
		874	3418 F80DAE A9 40 lda #'@'
		875	3419 F80DB0 A2 0F ldx #15
		876	3420 F80DB2 EB xba
		877	3421 F80DB3 A9 20 ?01: lda #$20
		878	3422 F80DB5 2C 25 FC bit !UART_LSR
		879	3423 F80DB8 EA nop
		880	3424 F80DB9 EA nop
		881	3425 F80DBA EA nop
		882	3426 F80DBB EA nop
		883	3427 F80DBC F0 F5 beq ?01
		884	3428
		885	3429 F80DBE A5 30 lda sptmp4
		886	3430 F80DC0 3A ?02: dec a
		887	3431 F80DC1 D0 FD bne ?02
		888	3432 F80DC3
		889	3433 F80DC3 EB xba
		890	3434 F80DC4 8D 20 FC sta !UART_RXTX
		891	3435 F80DC7 1A inc a
		892	3436 F80DC8 EB xba
		893	3437 F80DC9
		894	3438 F80DC9 A5 30 lda sptmp4
		895	3439 F80DCB 3A ?02a: dec a
		896	3440 F80DCC D0 FD bne ?02a
		897	3441
		898	3442 F80DCE CA dex
		899	3443 F80DCF D0 E2 bne ?01
		900	3444
		901	3445 F80DD1 A9 20 ?03: lda #$20
		902	3446 F80DD3 2C 25 FC bit !UART_LSR
		903	3447 F80DD6 EA nop
		904	3448 F80DD7 EA nop
		905	3449 F80DD8 EA nop
		906	3450 F80DD9 EA nop
		907	3451 F80DDA F0 F5 beq ?03
		908	3452
		909	3453 F80DDC A5 30 lda sptmp4
		910	3454 F80DDE 3A ?02b: dec a
		911	3455 F80DDF D0 FD bne ?02b
		912	3456 F80DE1
		913	3457 F80DE1 A9 0D lda #$0D
		914	3458 F80DE3 8D 20 FC sta !UART_RXTX
		915	3459 F80DE6 A5 30 lda sptmp4
		916	3460 F80DE8 2B pld
		917	3461 F80DE9 58 cli
		918	3462 F80DEA 00 00 brk
		919	3463
		920	3464 F80DEC test1:
		921	3465 F80DEC 78 sei
		922	3466 F80DED 0B phd
		923	3467 F80DEE F4 00 05 pea #DP05ADDR
		924	3468 F80DF1 2B pld
		925	3469 F80DF2 85 30 sta sptmp4
		926	3470 F80DF4 A9 01 lda #1
		927	3471 F80DF6 8D 22 FC sta !UART_FCR
		928	3472 F80DF9
		929	3473 F80DF9 A5 30 lda sptmp4
		930	3474 F80DFB 3A ?00: dec a
		931	Tue Jul 17 11:00:18 2018 Page 16
		932
		933
		934
		935
		936	3475 F80DFC D0 FD bne ?00
		937	3476 F80DFE
		938	3477 F80DFE A9 40 lda #'@'
		939	3478 F80E00 A2 0F ldx #15
		940	3479 F80E02 EB xba
		941	3480 F80E03 A9 20 ?01: lda #$20
		942	3481 F80E05 2C 25 FC bit !UART_LSR
		943	3482 F80E08 EA nop
		944	3483 F80E09 EA nop
		945	3484 F80E0A EA nop
		946	3485 F80E0B EA nop
		947	3486 F80E0C F0 F5 beq ?01
		948	3487
		949	3488 F80E0E A5 30 lda sptmp4
		950	3489 F80E10 3A ?02: dec a
		951	3490 F80E11 D0 FD bne ?02
		952	3491 F80E13
		953	3492 F80E13 EB ?0l: xba
		954	3493 F80E14 8D 20 FC sta !UART_RXTX
		955	3494 F80E17 1A inc a
		956	3495 F80E18 EB xba
		957	3496 F80E19
		958	3497 F80E19 A5 30 lda sptmp4
		959	3498 F80E1B 3A ?02a: dec a
		960	3499 F80E1C D0 FD bne ?02a
		961	3500
		962	3501 F80E1E CA dex
		963	3502 F80E1F D0 F2 bne ?0l
		964	3503 F80E21
		965	3504 F80E21 A9 0D lda #$0D
		966	3505 F80E23 8D 20 FC sta !UART_RXTX
		967	3506 F80E26 A5 30 lda sptmp4
		968	3507 F80E28 2B pld
		969	3508 F80E29 58 cli
		970	3509 F80E2A 00 00 brk
		971	3510
		972	3511 F80E2C test2:
		973	3512 F80E2C 78 sei
		974	3513 F80E2D 0B phd
		975	3514 F80E2E F4 00 05 pea #DP05ADDR
		976	3515 F80E31 2B pld
		977	3516 F80E32 A0 00 ldy #0
		978	3517 F80E34 A9 01 lda #1
		979	3518 F80E36 8D 22 FC sta !UART_FCR
		980	3519 F80E39 A9 40 ?00: lda #'@'
		981	3520 F80E3B A2 0F ldx #15
		982	3521 F80E3D EB xba
		983	3522 F80E3E A9 20 ?01: lda #$20
		984	3523 F80E40 2C 25 FC bit !UART_LSR
		985	3524 F80E43 EA nop
		986	3525 F80E44 EA nop
		987	3526 F80E45 EA nop
		988	3527 F80E46 EA nop
		989	3528 F80E47 F0 F5 beq ?01
		990	3529
		991	3530 F80E49 EB ?ll: xba
		992	3531 F80E4A 8D 20 FC sta !UART_RXTX
		993	Tue Jul 17 11:00:18 2018 Page 17
		994
		995
		996
		997
		998	3532 F80E4D 1A inc a
		999	3533 F80E4E EB xba
		1000	3534 F80E4F CA dex
		1001	3535 F80E50 D0 F7 bne ?ll
		1002	3536 F80E52
		1003	3537 F80E52 A9 0D lda #$0D
		1004	3538 F80E54 8D 20 FC sta !UART_RXTX
		1005	3539 F80E57 88 dey
		1006	3540 F80E58 D0 DF bne ?00
		1007	3541 F80E5A 2B pld
		1008	3542 F80E5B 58 cli
		1009	3543 F80E5C 00 00 brk
		1010	3544
		1011	3545 ;==========================================
		1012	3546 ; UM245R
		1013	3547
		1014	3548 F80E5E umgetcmd:
		1015	3549 .PUBLIC umgetcmd
		1016	3550
		1017	3551 F80E5E A9 40 lda #$40
		1018	3552 F80E60 14 01 trb usbum ; clear bit <6>: fifo data not available
		1019	3553 F80E62 24 01 bit usbum
		1020	3554 F80E64 30 1D bmi ?cmd ; already connected: check command
		1021	3555 F80E66
		1022	3556 ; check connession request
		1023	3557 F80E66 A2 07 ldx #7
		1024	3558 F80E68 B5 03 ?chk1: lda usbbuf,x
		1025	3559 F80E6A DF B7 0E F8 cmp >?usbconn,x
		1026	3560 F80E6E F0 06 beq ?nxt
		1027	3561 F80E70 A9 55 ?nack: lda #$55 ; NACK
		1028	3562 F80E72 8D 2F FC sta !UM245R
		1029	3563 F80E75 6B rtl
		1030	3564 F80E76 CA ?nxt: dex
		1031	3565 F80E77 10 EF bpl ?chk1
		1032	3566 F80E79 A9 AA lda #$AA ; ACK
		1033	3567 F80E7B 8D 2F FC sta !UM245R
		1034	3568 F80E7E A9 80 lda #$80
		1035	3569 F80E80 04 01 tsb usbum
		1036	3570 F80E82 6B rtl
		1037	3571 F80E83 A2 00 ?cmd: ldx #(?usbtab2 - ?usbtab1 - 1)
		1038	3572 F80E85 A5 03 lda usbbuf
		1039	3573 F80E87 DF BF 0E F8 ?cmdl: cmp >?usbtab1,x
		1040	3574 F80E8B F0 05 beq ?cmd2
		1041	3575 F80E8D CA dex
		1042	3576 F80E8E 10 F7 bpl ?cmdl
		1043	3577 F80E90 30 DE bmi ?nack ; not found
		1044	3578 F80E92 A5 04 ?cmd2: lda usbbuf+1
		1045	3579 F80E94 DF C0 0E F8 cmp >?usbtab2,x
		1046	3580 F80E98 D0 D6 bne ?nack ; not found
		1047	3581 F80E9A 8A txa
		1048	3582 F80E9B 0A asl a
		1049	3583 F80E9C AA tax
		1050	3584 F80E9D A9 01 lda #CA2IFRB ; disable CA2 interrupt
		1051	3585 F80E9F 8D 1E FC sta !VIA2+VIAIER
		1052	3586 F80EA2 8D 1D FC sta !VIA2+VIAIFR
		1053	3587 F80EA5 20 1B 10 jsr usbsndack
		1054	3588 F80EA8 FC B5 0E jsr (?umjmp,x)
		1055	Tue Jul 17 11:00:18 2018 Page 18
		1056
		1057
		1058
		1059
		1060	3589 F80EAB 78 sei
		1061	3590 F80EAC A9 81 lda #SETFRB.OR.CA2IFRB ; enable CA2 interrupt
		1062	3591 F80EAE 8D 1E FC sta !VIA2+VIAIER
		1063	3592 F80EB1 8D 1D FC sta !VIA2+VIAIFR
		1064	3593 F80EB4 6B rtl
		1065	3594
		1066	3595 F80EB5 ?umjmp:
		1067	3596 F80EB5 C10E .DW usbgetfmw
		1068	3597
		1069	3598 F80EB7 ?usbconn:
		1070	3599 F80EB7 87 E9 5D 93 B7 .DB $87, $E9, $5D, $93, $B7, $57, $7D, $3B
		1071	57 7D 3B
		1072	3600
		1073	3601 F80EBF ?usbtab1:
		1074	3602 F80EBF 99 .DB $99
		1075	3603
		1076	3604 F80EC0 ?usbtab2:
		1077	3605 F80EC0 51 .DB $51
		1078	3606
		1079	3607
		1080	3608 ; get firmware (512K)
		1081	3609 F80EC1 usbgetfmw:
		1082	3610 F80EC1 58 cli
		1083	3611 F80EC2 64 10 stz usbptr
		1084	3612 F80EC4 64 11 stz usbptr+1
		1085	3613 F80EC6 A9 70 lda #$70
		1086	3614 F80EC8 85 12 sta usbptr+2 ; put firmware in bank $30
		1087	3615 F80ECA 64 0E stz usbsiz ; full 64K bank
		1088	3616 F80ECC 64 0F stz usbsiz+1
		1089	3617 F80ECE A9 08 lda #$08 ; 8 banks
		1090	3618 F80ED0 85 13 sta usbtmp
		1091	3619 F80ED2 A9 08 ?lp: lda #$08
		1092	3620 F80ED4 38 sec
		1093	3621 F80ED5 E5 13 sbc usbtmp
		1094	3622 F80ED7 48 pha
		1095	3623 F80ED8 4B phk
		1096	3624 F80ED9 F4 3F 0F pea #!?fmt1
		1097	3625 F80EDC A9 05 lda #5
		1098	3626 F80EDE 48 pha
		1099	3627 F80EDF BPRINTF
		1100	3628 F80EDF 02 11 cop $11
		1101	3629 .MNLIST
		1102	3630 F80EE1 20 8A 0F jsr usbgetblk
		1103	3631 F80EE4 B0 4E bcs ?err ; error
		1104	3632 F80EE6 20 1B 10 jsr usbsndack
		1105	3633 F80EE9 SCNPRINT
		1106	3634 F80EE9 02 01 cop $01
		1107	3635 .MNLIST
		1108	3636 F80EEB 64 6F 6E 65 2E .DB 'done.', 13, 0
		1109	0D 00
		1110	3637 F80EF2 E6 12 inc usbptr+2
		1111	3638 F80EF4 C6 13 dec usbtmp
		1112	3639 F80EF6 D0 DA bne ?lp
		1113	3640
		1114	3641 F80EF8 A9 70 lda #$70
		1115	3642 F80EFA 85 12 sta usbptr+2
		1116	3643 F80EFC 64 14 stz usbcmp
		1117	Tue Jul 17 11:00:18 2018 Page 19
		1118
		1119
		1120
		1121
		1122	3644 F80EFE A9 08 lda #$08 ; 8 banks
		1123	3645 F80F00 85 13 sta usbtmp
		1124	3646 F80F02 A9 08 ?lp2: lda #$08
		1125	3647 F80F04 38 sec
		1126	3648 F80F05 E5 13 sbc usbtmp
		1127	3649 F80F07 48 pha
		1128	3650 F80F08 4B phk
		1129	3651 F80F09 F4 71 0F pea #!?fmt3
		1130	3652 F80F0C A9 05 lda #5
		1131	3653 F80F0E 48 pha
		1132	3654 F80F0F BPRINTF
		1133	3655 F80F0F 02 11 cop $11
		1134	3656 .MNLIST
		1135	3657 F80F11
		1136	3658 ;jsr usbcmpblk
		1137	3659 ;bcs ?err ; error
		1138	3660 ;bit usbcmp
		1139	3661 ;bpl ?ok
		1140	3662 ;jsr usbsndnack
		1141	3663 ;bra ?err
		1142	3664 ?ok: ;jsr usbsndack
		1143	3665
		1144	3666 F80F11 20 DE 0F jsr usbputbank
		1145	3667 F80F14 B0 1E bcs ?err
		1146	3668
		1147	3669 F80F16 SCNPRINT
		1148	3670 F80F16 02 01 cop $01
		1149	3671 .MNLIST
		1150	3672 F80F18 64 6F 6E 65 2E .DB 'done.', 13, 0
		1151	0D 00
		1152	3673 F80F1F E6 12 inc usbptr+2
		1153	3674 F80F21 C6 13 dec usbtmp
		1154	3675 F80F23 D0 DD bne ?lp2
		1155	3676 F80F25
		1156	3677 .COMMENT @
		1157	3678 ; send back for check
		1158	3679 lda #$08 ; 8 banks
		1159	3680 sta usbtmp
		1160	3681 lda #$70
		1161	3682 sta usbptr+2
		1162	3683 ?lp1: lda #$08
		1163	3684 sec
		1164	3685 sbc usbtmp
		1165	3686 pha
		1166	3687 phk
		1167	3688 pea #!?fmt2
		1168	3689 lda #5
		1169	3690 pha
		1170	3691 BPRINTF
		1171	3692 ;jsr usbputblk
		1172	3693 jsr usbputbank
		1173	3694 ;jsr usbrx
		1174	3695 bcs ?err
		1175	3696 ;bne ?err ; NACK
		1176	3697 SCNPRINT
		1177	3698 .DB 'done.', 13, 0
		1178	3699 inc usbptr+2
		1179	Tue Jul 17 11:00:18 2018 Page 20
		1180
		1181
		1182
		1183
		1184	3700 dec usbtmp
		1185	3701 bne ?lp1
		1186	3702 @
		1187	3703
		1188	3704 ; wait final ACK
		1189	3705 F80F25 20 26 10 jsr usbrx
		1190	3706 F80F28 B0 0A bcs ?err
		1191	3707 F80F2A D0 08 bne ?err ; NACK
		1192	3708 F80F2C SCNPRINT
		1193	3709 F80F2C 02 01 cop $01
		1194	3710 .MNLIST
		1195	3711 F80F2E 4F 4B 2E 0D 00 .DB 'OK.', 13, 0
		1196	3712 F80F33 60 rts
		1197	3713 F80F34 ?err:
		1198	3714 F80F34 SCNPRINT
		1199	3715 F80F34 02 01 cop $01
		1200	3716 .MNLIST
		1201	3717 F80F36 65 72 72 6F 72 .DB 'error.', 13, 0
		1202	2E 0D 00
		1203	3718 F80F3E 60 rts
		1204	3719
		1205	3720 F80F3F 67 65 74 20 66 ?fmt1: .DB 'get firmware bank %bu...', 0
		1206	69 72 6D 77 61
		1207	72 65 20 62 61
		1208	6E 6B 20 25 62
		1209	75 2E 2E 2E 00
		1210	3721 F80F58 73 65 6E 64 20 ?fmt2: .DB 'send back bank %bu...', 0
		1211	62 61 63 6B 20
		1212	20 20 20 62 61
		1213	6E 6B 20 25 62
		1214	75 2E 2E 2E 00
		1215	3722 F80F71 76 65 72 66 2E ?fmt3: .DB 'verf. firmw. bank %bu...', 0
		1216	20 66 69 72 6D
		1217	77 2E 20 62 61
		1218	6E 6B 20 25 62
		1219	75 2E 2E 2E 00
		1220	3723
		1221	3724 ; get block: size in usbsiz, dest in usbptr
		1222	3725 F80F8A usbgetblk:
		1223	3726 F80F8A A0 00 ldy #0
		1224	3727 F80F8C INDEX16
		1225	3728 F80F8C C2 10 rep #PXFLAG
		1226	3729 .LONGI on
		1227	3730 .MNLIST
		1228	3731 F80F8E A6 0E ldx usbsiz
		1229	3732 F80F90 A9 01 lda #CA2IFRB ; check CA2 flag
		1230	3733 F80F92 2C 1F FC ?lp: bit !VIA2+VIAPRANH ; check /TXE
		1231	3734 F80F95 70 17 bvs ?err ; /TXE is high: disconnession?
		1232	3735 F80F97 2C 1D FC bit VIA2+VIAIFR ; check CA2 flag
		1233	3736 F80F9A F0 F6 beq ?lp
		1234	3737 F80F9C 8D 1D FC sta !VIA2+VIAIFR ; clear CA2 flag
		1235	3738 F80F9F EB xba
		1236	3739 F80FA0 AD 2F FC lda !UM245R
		1237	3740 F80FA3 97 10 sta [usbptr],y
		1238	3741 F80FA5 EB xba
		1239	3742 F80FA6 C8 iny
		1240	3743 F80FA7 CA dex
		1241	Tue Jul 17 11:00:18 2018 Page 21
		1242
		1243
		1244
		1245
		1246	3744 F80FA8 D0 E8 bne ?lp
		1247	3745 F80FAA 18 clc
		1248	3746 F80FAB INDEX08
		1249	3747 F80FAB E2 10 sep #PXFLAG
		1250	3748 .LONGI off
		1251	3749 .MNLIST
		1252	3750 F80FAD 60 rts
		1253	3751 F80FAE ?err: CPU08SEC
		1254	3752 F80FAE E2 31 sep #(PMFLAG.OR.PXFLAG.OR.PCFLAG)
		1255	3753 .LONGA off
		1256	3754 .LONGI off
		1257	3755 .MNLIST
		1258	3756 F80FB0 60 rts
		1259	3757
		1260	3758 ; cmp block: size in usbsiz, dest in usbptr
		1261	3759 F80FB1 usbcmpblk:
		1262	3760 F80FB1 A0 00 ldy #0
		1263	3761 F80FB3 INDEX16
		1264	3762 F80FB3 C2 10 rep #PXFLAG
		1265	3763 .LONGI on
		1266	3764 .MNLIST
		1267	3765 F80FB5 A6 0E ldx usbsiz
		1268	3766 F80FB7 A9 01 lda #CA2IFRB ; check CA2 flag
		1269	3767 F80FB9 2C 1F FC ?lp: bit !VIA2+VIAPRANH ; check /TXE
		1270	3768 F80FBC 70 1D bvs ?err ; /TXE is high: disconnession?
		1271	3769 F80FBE 2C 1D FC bit VIA2+VIAIFR ; check CA2 flag
		1272	3770 F80FC1 F0 F6 beq ?lp
		1273	3771 F80FC3 8D 1D FC sta !VIA2+VIAIFR ; clear CA2 flag
		1274	3772 F80FC6 EB xba
		1275	3773 F80FC7 AD 2F FC lda !UM245R
		1276	3774 F80FCA D7 10 cmp [usbptr],y
		1277	3775 F80FCC F0 04 beq ?02
		1278	3776 F80FCE A9 80 lda #$80
		1279	3777 F80FD0 85 14 sta usbcmp
		1280	3778 F80FD2 EB ?02: xba
		1281	3779 F80FD3 C8 iny
		1282	3780 F80FD4 CA dex
		1283	3781 F80FD5 D0 E2 bne ?lp
		1284	3782 F80FD7 18 clc
		1285	3783 F80FD8 INDEX08
		1286	3784 F80FD8 E2 10 sep #PXFLAG
		1287	3785 .LONGI off
		1288	3786 .MNLIST
		1289	3787 F80FDA 60 rts
		1290	3788 F80FDB ?err: CPU08SEC
		1291	3789 F80FDB E2 31 sep #(PMFLAG.OR.PXFLAG.OR.PCFLAG)
		1292	3790 .LONGA off
		1293	3791 .LONGI off
		1294	3792 .MNLIST
		1295	3793 F80FDD 60 rts
		1296	3794
		1297	3795 ; put a full: source in usbptr
		1298	3796 F80FDE usbputbank:
		1299	3797 F80FDE 78 sei
		1300	3798 F80FDF A0 00 ldy #0
		1301	3799 F80FE1 AD 1F FC ?lp: lda !VIA2+VIAPRANH ; check /TXE
		1302	3800 F80FE4 CD 1F FC cmp !VIA2+VIAPRANH
		1303	Tue Jul 17 11:00:18 2018 Page 22
		1304
		1305
		1306
		1307
		1308	3801 F80FE7 D0 F8 bne ?lp
		1309	3802 F80FE9 0A asl a
		1310	3803 F80FEA 30 F5 bmi ?lp
		1311	3804 F80FEC B7 10 lda [usbptr],y
		1312	3805 F80FEE 8F 2F FC 00 sta >UM245R
		1313	3806 F80FF2 C8 iny
		1314	3807 F80FF3 D0 EC bne ?lp
		1315	3808 ;jsr usbrx
		1316	3809 ;bcs ?rts
		1317	3810 ;bne ?err ; NACK
		1318	3811 F80FF5 E6 11 inc usbptr+1
		1319	3812 F80FF7 D0 E8 bne ?lp
		1320	3813 F80FF9 18 clc
		1321	3814 F80FFA 58 ?rts: cli
		1322	3815 F80FFB 60 rts
		1323	3816 F80FFC 38 ?err: sec
		1324	3817 F80FFD 58 cli
		1325	3818 F80FFE 60 rts
		1326	3819
		1327	3820 ; put block: size in usbsiz, dest in usbptr
		1328	3821 F80FFF usbputblk:
		1329	3822 F80FFF A0 00 ldy #0
		1330	3823 F81001 INDEX16
		1331	3824 F81001 C2 10 rep #PXFLAG
		1332	3825 .LONGI on
		1333	3826 .MNLIST
		1334	3827 F81003 A6 0E ldx usbsiz
		1335	3828 ; bra ?lp
		1336	3829 ;?lp0: bit !VIA2+VIAPRANH ; check /TXE
		1337	3830 ; bvs ?lp
		1338	3831 ; bvc ?lp0
		1339	3832 F81005 2C 1F FC ?lp: bit !VIA2+VIAPRANH ; check /TXE
		1340	3833 ;cmp !VIA2+VIAPRANH
		1341	3834 ;bne ?lp
		1342	3835 ;asl a
		1343	3836 ;bmi ?lp ; /TXE is high
		1344	3837 F81008 70 FB bvs ?lp
		1345	3838 F8100A B7 10 lda [usbptr],y
		1346	3839 F8100C 8D 2F FC sta !UM245R
		1347	3840 F8100F C8 iny
		1348	3841 F81010 CA dex
		1349	3842 F81011 D0 F2 bne ?lp
		1350	3843 F81013 18 clc
		1351	3844 F81014 INDEX08
		1352	3845 F81014 E2 10 sep #PXFLAG
		1353	3846 .LONGI off
		1354	3847 .MNLIST
		1355	3848 F81016 60 rts
		1356	3849
		1357	3850 ; send nack
		1358	3851 F81017 usbsndnack:
		1359	3852 F81017 A9 55 lda #$55
		1360	3853 F81019 80 02 bra usbsnd
		1361	3854
		1362	3855 ; send ack
		1363	3856 F8101B usbsndack:
		1364	3857 F8101B A9 AA lda #$AA
		1365	Tue Jul 17 11:00:18 2018 Page 23
		1366
		1367
		1368
		1369
		1370	3858
		1371	3859 ; send a byte
		1372	3860 F8101D usbsnd:
		1373	3861 F8101D 2C 1F FC ?lp: bit !VIA2+VIAPRANH ; check /TXE
		1374	3862 F81020 70 FB bvs ?lp ; /TXE is high
		1375	3863 F81022 8D 2F FC sta !UM245R
		1376	3864 F81025 60 rts
		1377	3865
		1378	3866 F81026 usbrx:
		1379	3867 F81026 A9 01 lda #CA2IFRB ; check CA2 flag
		1380	3868 F81028 2C 1F FC ?lp: bit !VIA2+VIAPRANH ; check /TXE
		1381	3869 F8102B 70 0F bvs ?err ; /TXE is high: disconnession?
		1382	3870 F8102D 2C 1D FC bit VIA2+VIAIFR ; check CA2 flag
		1383	3871 F81030 F0 F6 beq ?lp
		1384	3872 F81032 8D 1D FC sta !VIA2+VIAIFR ; clear CA2 flag
		1385	3873 F81035 AD 2F FC lda !UM245R
		1386	3874 F81038 C9 AA cmp #$AA
		1387	3875 F8103A 18 clc
		1388	3876 F8103B 60 rts
		1389	3877 F8103C 38 ?err: sec
		1390	3878 F8103D 60 rts
		1391
		1392
		1393	Lines Assembled : 3788 Errors : 0
		1394
		1395
		1396

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(root)/trunk/sources/lst/F8/sp2.lst – Rev 1