Subversion Repositories MB01 Project

;----------------------------------------------------------

; CHIPS.INC

; PROGETTO: B1601

;

; CHIPS I/O

;----------------------------------------------------------

; il file puo' essere incluso solo all'interno di GLOBAL.INC

.IFNDEF		_GLOBAL_INC_

.EXIT		"ERROR: This file cannot be included."

.ENDIF

;----------------------------------------------------------

; registro di controllo

CRBIT0		.EQU	$00FC00

CR0OFF		.EQU	$00FC00

CR0ON		.EQU	$00FC01

CRBIT1		.EQU	$00FC02

CR1OFF		.EQU	$00FC02

CR1ON		.EQU	$00FC03

CRBIT2		.EQU	$00FC04

CR2OFF		.EQU	$00FC04

CR2ON		.EQU	$00FC05

CRFWE		.EQU	$00FC06

CRFWEOFF	.EQU	$00FC06

CRFWEON		.EQU	$00FC07

CRXFE		.EQU	$00FC08

CRXFEOFF	.EQU	$00FC08

CRXFEON		.EQU	$00FC09

CRXME		.EQU	$00FC0A

CRXMEOFF	.EQU	$00FC0A

CRXMEON		.EQU	$00FC0B

CREME		.EQU	$00FC0C

CREMEOFF	.EQU	$00FC0C

CREMEON		.EQU	$00FC0D

CRHIM		.EQU	$00FC0E

CRHIMOFF	.EQU	$00FC0E

CRHIMON		.EQU	$00FC0F

; registri VIA 65C22

VIA0		.EQU	$00FD00		; IRQ 2

VIA1		.EQU	$00FD10		; NMI

; bit I/O VIA 0 - IRQ 2

; PA0 -> XM16 - linea A16 memoria DMA con DMA attivo

; PA1 -> /DME - enable DMA

; PA2 -> DMA direction: 1->to mem, 0-> from mem

; PA3 ->

; PA4 -> /XTC - impulso TC DMA/FDC (impulso negativo)

; PA5 -> /FFSR - set flip flop reset (impulso negativo) - vedere PIA0-PB4

; PA6 -> RSTRM - enable terminazione RS485 120 ohm su linee RX/TX

; PA7 -> /CLRX - reset macchina (impulso negativo)

; PB0 -> /WD - enable wait chip DMA

; PB1 -> /WF - enable wait chip FDC

; PB2 -> /WS - enable wait chip ACIA

; PB3 -> /WA0 - enable wait slot ATA 0

; PB4 -> /WA1 - enable wait slot ATA 1

; PB5 -> /WV - enable wait chip VDC

; PB6 <- onda quadra 1KHZ per timer T2

; PB7 -> /WT - enable wait chip CTC

; CA1 <- TMF1 (da CTC) fronte negativo - vedere anche PIA0-PB6

; CA2 <- INT da controller tastiera - fronte negativo

; CB1 <- INT da controller FDC - fronte positivo - vedere anche PIA0-PB7

; CB2 <- TMF0 (da CTC) fronte negativo - vedere anche PIA0-PB5

; bit I/O VIA 1 - NMI

; PA0 -> /VDE - enable output RGB da chip VDC

; PA1 -> /S16M - enable dot clock VDC a 16MHZ (CGA)

; PA2 -> HPOL - HSYNC VDC positivo

; PA3 -> VPOL - VSYNC VDC positivo

; PA4 -> /KBRES - reset controller tastiera (impulso negativo)

; PA5 -> PCTS1 - inversione livello /CTS1 su ACIA

; PA6 -> PCTS2 - inversione livello /CTS2 su ACIA

; PA7 -> /RS485 - enable RS485 su canale 2 ACIA

; PB0 -> /KFRW0 - enable write file register KFR sincronizzato con PHI0

; PB1 -> DMA clock select: 0->4MHz - 1->5MHz

; PB2 -> /VDCSX - abilita impulso di selezione su /CS0 o CS1 VDC

;		  altrimenti /CS0 a livello 0 oppure CS1 a livello 1

; PB3 -> /VDCS0 - sincronizza write registri VDC con PHI0 invece di PHI2

; PB4 <- TRIGGER POWER - impulso negativo da pulsante ON/OFF

; PB5 -> /MW0 - enable write RAM/FLASH sincronizzato con PHI0

; PB6 <- onda quadra 1KHZ per timer T2

; PB7 -> onda quadra 1KHZ da timer T1

; CA1 <- impulso ATA 0 INT - fronte positivo (non genera NMI)

; CA2 <- impulso NMI da controller tastiera - fronte negativo

; CB1 <- impulso ATA 1 INT - fronte positivo (non genera NMI)

; CB2 <- TRIGGER POWER - impulso negativo da pulsante ON/OFF

VIAPRB		.EQU	$0

VIAPRA		.EQU	$1

VIADDRB		.EQU	$2

VIADDRA		.EQU	$3

VIAT1CL		.EQU	$4

VIAT1CH		.EQU	$5

VIAT1LL		.EQU	$6

VIAT1LH		.EQU	$7

VIAT2CL		.EQU	$8

VIAT2CH		.EQU	$9

VIASR		.EQU	$A

VIAACR		.EQU	$B

VIAPCR		.EQU	$C

VIAIFR		.EQU	$D

VIAIER		.EQU	$E

VIAPRANH	.EQU	$F

; bit IER/IFR

SETFRB		.EQU	10000000B

T1IFRB		.EQU	01000000B

T2IFRB		.EQU	00100000B

CB1IFRB		.EQU	00010000B

CB2IFRB		.EQU	00001000B

SRIFRB		.EQU	00000100B

CA1IFRB		.EQU	00000010B

CA2IFRB		.EQU	00000001B

VIA4		.EQU	$00FC60		; IRQ 5

; VIA4 - IRQ5

; PB0..PB7 (OUT)	high address emulator (256 banks x 2K)

; New FDC/DMA/BOARD

VIA3		.EQU	$00FDC0		; IRQ 3

; VIA3 - IRQ3

; PA0, PA1, PA2 (OUT)	MA17..MA19 1MB banked ram (cpu accesss)

; PA3..PA7 (input)	PA3 not used

;		 	PA4 <- HRQ1

;			PA5 <- HRQ0

;		 	PA6 <- DMRQ1

;			PA7 <- DMRQ0

;

; PB0..PB6 out, PB7 input

;			PB0..PB2 -> MA16..MA18 1Mb ram (DMA access)

;			PB3 -> /S1M enable ram 1Mb

;			PB4 -> ATA (select ATA port while DMA)

;			PB5 -> /FDC (select FDC DMA)

;			PB6 -> /ALT enable 1Mb ram while FDC DMA

;			PB7, CB2 <- CH365/376 interrupt line (negative edge)

;

; CA1			<- negative edge ATA 0 interrupt

; CA2			<- negative edge ATA 1 interrupt

; CB1			<- negative edge /EOP DMA 0 (ATA)

; CB2			<- negative edge CH375/6 interrupt

.IFDEF		_CH375_INC_

; ch375/376 usb host chip

usb0dat		.EQU	$00FDD0

usb0cmd		.EQU	$00FDD1

CMD_GET_IC_VER		.EQU	$01	; get chip version

CMD_RESET_ALL		.EQU	$05	; reset ch375/ch376

CMD_CHECK_EXIST		.EQU	$06	; check for chip

CMD_READ_VAR8		.EQU	$0A	; ch376 only

VAR_DISK_STATUS		.EQU	$2B

CMD_PREFIX		.EQU	$0B	; command need one more byte

PFX_SET_PKT_P_SEC	.EQU	$39

CMD_SET_USB_MODE 	.EQU	$15	; set chip usb mode

SET_USB_HOST		.EQU	$06	; set usb host mode

SET_USB_RES		.EQU	$07	; reset usb bus host mode

CMD_GET_STATUS		.EQU	$22	; get interrupt status

CMD_RD_USB_DATA		.EQU	$28	; read data block

CMD_DISK_MOUNT		.EQU	$31	; init disk (ch376 only)

CMD_DISK_CAPACITY	.EQU	$3E	; get disk size (ch376 only)

CMD_DISK_INIT		.EQU	$51	; init disk (ch375)

CMD_DISK_SIZE		.EQU	$53	; get disk size (ch375)

CMD_DISK_READ		.EQU	$54

CMD_DISK_RD_GO		.EQU	$55

CMD_RET_SUCCESS		.EQU	$51	; return data for some command's

CMD_DISK_INQUIRY	.EQU	$58	; device string

CMD_DISK_READY		.EQU	$59

CMD_DISK_R_SENSE	.EQU	$5A

; ch375/ch376 interrupt status

USB_INT_SUCCESS		.EQU	$14

USB_INT_CONNECT		.EQU	$15

USB_INT_DISCONNECT 	.EQU	$16

USB_INT_BUF_OVER	.EQU	$17

USB_INT_DISK_READ	.EQU	$1D

USB_INT_DISK_ERR	.EQU	$1F

; ch376 only status

ERR_DISK_DISCON		.EQU	$82

ERR_LARGE_SECTOR	.EQU	$84

ERR_TYPE_ERROR		.EQU	$92

ERR_BPB_ERROR		.EQU	$A1

ERR_DISK_FULL		.EQU	$B1

ERR_FDT_OVER		.EQU	$B2

ERR_FILE_CLOSE		.EQU	$B4

ERR_OPEN_DIR		.EQU	$41

ERR_MISS_FILE		.EQU	$42

ERR_FOUND_NAME		.EQU	$43

ERR_MISS_DIR		.EQU	$B3

ERR_LONG_BUF_OVER	.EQU	$48

ERR_LONG_NAME_ERR	.EQU	$49

ERR_NAME_EXIST		.EQU	$4A

; ch376: VAR_DISK_STATUS values

DEF_DISK_UNKNOWN	.EQU	$00

DEF_DISK_DISCONN	.EQU	$01

DEF_DISK_CONNECT	.EQU	$02

DEF_DISK_MOUNTED	.EQU	$03

DEF_DISK_READY		.EQU	$10

DEF_DISK_OPEN_ROOT	.EQU	$12

DEF_DISK_OPEN_DIR	.EQU	$13

DEF_DISK_OPEN_FILE	.EQU	$14

.ENDIF

; addon serial test board

.IFDEF		_ADDSER_INC_

VIA2		.EQU	$00FC10		; IRQ 3

; VIA2 - IRQ3

; PA0, PA1 (OUT)	baude-rate 65C51

;		 		00 -> 19200

;		 		01 -> 38400

;				10 -> 57600

;				11 -> 115200

; PA2 (OUT)		/RTS for 65C51

; PA3, CB2 (IN)		/CTS input (65C51)

; PA4, CB1 (IN)		BUSY from emulator

; PA5 (IN)		Sense interrupt to PIC

; PA6 (IN)		/TXE from UM245R

; PA7, CA2 (IN)		/RXF from UM245R (negative edge)

; PB0..PB7 (OUT)	high address emulator (256 banks x 2K)

; CA1 (IN)		interrupt from PIC (negative edge)

; ACIA R65C51 at $FC28 (INT 4)

ACIADR		.EQU	$00FC28	; ACIA TX/RX data register

ACIASR		.EQU	$00FC29	; ACIA Status

ACIACMD		.EQU	$00FC2A	; ACIA Command register

ACIACTRL	.EQU	$00FC2B	; ACIA Control register

ACIADSR		.EQU	01000000B

ACIADCD		.EQU	00100000B

ACIATDRE	.EQU	00010000B

ACIARDRF	.EQU	00001000B

ACIACMDTIC	.EQU	11110011B

ACIACMDTXEI	.EQU	00000100B

ACIACMDTXDI	.EQU	00001000B

ACIACMDRXDI	.EQU	00000010B

;ACIACMDDTR	.EQU	00000001B

ACIAENABLE	.EQU	00001001B

ACIACMDOFF	.EQU	00000010B

;ACIASRMASK	.EQU	(.NOT.(ACIATDRE .OR. ACIARDRF))

;ACIASRDSRDCD	.EQU	(ACIASRDSR .OR. ACIASRDCD)

; UM245R data port at $FC2F

UM245R		.EQU	$00FC2F

; uart 16C550 at $FF20

UART_RXTX	.EQU	$00FC20	; DLAB=0

UART_IER	.EQU	$00FC21	; DLAB=0

UART_DLL	.EQU	$00FC20	; divisor latch low, DLAB=1

UART_DLH	.EQU	$00FC21	; divisor latch high, DLAB=1

UART_IIR	.EQU	$00FC22	; Int. Ident. Reg., read only

UART_FCR	.EQU	$00FC22	; FIFO Ctrl Reg., write only

UART_LCR	.EQU	$00FC23	; Line Ctrl Reg.

UART_MCR	.EQU	$00FC24	; Modem Ctrl Reg.

UART_LSR	.EQU	$00FC25	; Line Status Reg.

UART_MSR	.EQU	$00FC26	; Modem Status Reg.

UART_SCP	.EQU	$00FC27	; scratchpad reg.

.ENDIF

;----------------------------------------------------------

.IFDEF		_ATA_INC_

; register address for ata #0

ATAERROR	.EQU	$FDA1		; error reg. READ

ATAFEAT		.EQU	$FDA1		; feature reg. WRITE

ATASCTCNT	.EQU	$FDA2		; sector count

ATALBAL		.EQU	$FDA3		; LBA LOW

ATALBAM		.EQU	$FDA4		; LBA MID

ATALBAH		.EQU	$FDA5		; LBA HIGH

ATADEV		.EQU	$FDA6		; device reg.

ATAST		.EQU	$FDA7		; status reg. READ

ATACMD		.EQU	$FDA7		; command reg. WRITE

ATADATA		.EQU	$FDA8		; dummy data register latch (16 bit)

ATAPORT		.EQU	$FDAA		; data register latch (16 bit access)

					; high byte at $FDAB

ATAALTST	.EQU	$FDAE		; alt. status reg. READ

ATACTRL		.EQU	$FDAE		; device control reg. WRITE

ATAOFS		.EQU	$10		; offset ata #1 address

; bit registro di stato

ATABSY		.EQU	10000000B	; busy bit

ATADRDY		.EQU	01000000B	; ready bit

ATADFB		.EQU	00100000B	; device fault bit

ATADRQ		.EQU	00001000B	; data request bit

ATAERRB		.EQU	00000001B	; error bit

; bit registro di errore

ATA_ABRT	.EQU	00000100B	; flag ABORT

; bit registro $0E - device control (ATACTRL)

CTRLSRST	.EQU	00000100B	; software reset (ATACTRL)

.ENDIF

;----------------------------------------------------------

; registri PIA, PIA 1

PIA0		.EQU	$00FD28

PIA1		.EQU	$00FD38		; LCD

; bit I/O PIA 0

; PA0-PA7 -> MA13-MA20 linee indirizzo memoria estesa (256 pagine di 8K)

; PB0-PB3 -> SA13-SA16 linee indirizzo buffer DMA per macchina 65C02

; PB4 <- /FSR livello 0 al reset (Flip Flop)

; PB5 <- TMF0 (da CTC) fronte negativo

; PB6 <- TMF1 (da CTC) fronte negativo

; PB7 <- INT da FDC fronte negativo

; CA2 -> /ENQ0 - enable buzzer

; CB2 -> /SMODE - enable mode one shot per buzzer

; bit I/O PIA 1 - controller LCD

; PA0 -> RS

; PA1 -> R/W

; PA2 -> E

; PB0-PB7 -> DB0 - DB7

PIAPRA		.EQU	$0

PIADDRA		.EQU	$0

PIACRA		.EQU	$1

PIAPRB		.EQU	$2

PIADDRB		.EQU	$2

PIACRB		.EQU	$3

; NOTA: inizializzare CRA, CRB -> 00000000

; Accesso a porta:    CRA, CRB -> 00000100

;----------------------------------------------------------

.IFDEF _KFR_INC_

; registri controller tastiera

KBFR		.EQU	$00FD40		; KB file register

KBSTATUS	.EQU	$00FD44		; KB status - read

KBDRQ		.EQU	$00FD44		; write - richiesta servizio

KBCLRNMI	.EQU	$00FD45		; write - azzera flag NMI

KBCLRIRQ	.EQU	$00FD46		; write - azzera flag INT

; bit di KBSTATUS

; 7: DRQ attivo - controller busy

; 6: RA5 da controller

; 5: flag NMI da controller

; 4: flag IRQ da controller

; 3, 2 e 1: 0

; 0; RA4 da controller

.ENDIF

;----------------------------------------------------------

IRQVECTR	.EQU	$00FD47		; registro vettore IRQ (sola lettura)

;----------------------------------------------------------

; registri CTC 82C54

CTC0		.EQU	$00FD48

CTCCNT0		.EQU	0

CTCCNT1		.EQU	1

CTCCNT2		.EQU	2

CTCCTRL		.EQU	3

;----------------------------------------------------------

.IFDEF		_RTC_INC_

; registri RTC DS1687

RTCALE		.EQU	$00FD4C		; registro address (senza /CS)

RTCDATA		.EQU	$00FD4D		; registro data

RTCCTRLA	.EQU	$0A		; registro controllo A

RTCEXTCTRLA	.EQU	$4A		; registro controllo esteso 4A (banco 1)

RTCCTRLB	.EQU	$0B		; registro controllo B

RTCEXTCTRLB	.EQU	$4B		; registro controllo esteso 4B (banco 1)

RTCSTATUS	.EQU	$0C		; registro di stato principale

RTCSTATUS2	.EQU	$0D		; registro di stato secondario

RTCSECS		.EQU	$00		; registro secondi

RTCMIN		.EQU	$02		; registro minuti

RTCHOURS	.EQU	$04		; registro ore

RTCDAY		.EQU	$06		; registro giorno

RTCDDATE	.EQU	$07		; registro data

RTCMONTH	.EQU	$08		; registro mese

RTCYEAR		.EQU	$09		; registro anno

RTCCENTURY	.EQU	$48		; registro secolo (banco 1)

RTCALMSECS	.EQU	$01		; registro allarme secondi

RTCALMMIN	.EQU	$03		; registro allarme minuti

RTCALMHOURS	.EQU	$05		; registro allarme ore

RTCALMDATE	.EQU	$49		; registro allarme data (banco 1)

RTCRAM0E	.EQU	$0E		; registro RAM $0E

RTCRAM0F	.EQU	$0F		; registro RAM $0F

RTCURAM		.EQU	$10		; user RAM da $10 a $3F (48 bytes)

RTCURAMLAST	.EQU	$3F

; saved configuration in RTC ram bank 0 & 1

RTCSHID		.EQU	$3B		; default hidden sector's (for fdisk)

RTCHUSE		.EQU	$3C		; flag use hash in fat driver

RTCHLOG2	.EQU	$3D		; hash hlog2 value (how much sector's)

RTCRDFG		.EQU	$3E		; flag ram disk valid configuration ($55)

					; new device or after clear mem = $FF

RTCRD		.EQU	$3F		; saved configuration for ram disk

RTCURAM0	.EQU	$40		; user RAM da $40 a $7F (64 bytes)

RTCURAM0LAST	.EQU	$7F		; solo banco 0

RTCEXTRAMADDR	.EQU	$50		; registro address EXT RAM (128 bytes) banco 1

RTCEXTRAMDATA	.EQU	$53		; registro data EXT RAM (128 bytes) banco 1

RTCSMI2		.EQU	$4E		; SMI recovery stack ADDR - 2

RTCSMI3		.EQU	$4F		; SMI recovery stack ADDR - 3

RTCTYPE		.EQU	$40		; RTC MODEL ($47 per DS1687) - banco 1

RTCSERIAL	.EQU	$41		; S/N RTC - 6 bytes da $41 a $46 - banco 1

RTCCRC		.EQU	$47		; CRC del serial number

; bit di RTCFlag

RTC_TVAL	.EQU	10000000B	; bit time valido

RTC_VBAT	.EQU	01000000B

RTC_VBAUX	.EQU	00100000B

.ENDIF

;----------------------------------------------------------

; registri MOS8563

VDCAddr		.EQU	$00FD4E

VDCStatus	.EQU	$00FD4E

VDCData		.EQU	$00FD4F

;----------------------------------------------------------

.IFDEF		_ACIA_INC_

; registri ACIA R65C52

ACIA		.EQU	$00FD50

ACIAIER		.EQU	$FD50		; INT enable reg. 1 (write)

ACIAISR		.EQU	$FD50		; INT status reg. 1 (read)

ACIACR		.EQU	$FD51		; Control register 1 (write)

ACIACSR		.EQU	$FD51		; Control status reg. 1 (read)

ACIAFR		.EQU	$FD51		; Format register 1 (write)

ACIACDR		.EQU	$FD52		; Compare data reg. 1 (write)

ACIAACR		.EQU	$FD52		; Aux. Control reg. 1 (write)

ACIATDR		.EQU	$FD53		; TX Data reg. (write)

ACIARDR		.EQU	$FD53		; RX Data reg. (read)

ACIAIER1	.EQU	0		; INT enable reg. 1 (write)

ACIAISR1	.EQU	0		; INT status reg. 1 (read)

ACIACR1		.EQU	1		; Control register 1 (write)

ACIAFR1		.EQU	1		; Format register 1 (write)

ACIACSR1	.EQU	1		; Control status reg. 1 (read)

ACIACDR1	.EQU	2		; Compare data reg. 1 (write)

ACIAACR1	.EQU	2		; Aux. Control reg. 1 (write)

ACIATDR1	.EQU	3		; TX Data reg. 1 (write)

ACIARDR1	.EQU	3		; RX Data reg. 1 (read)

ACIAIER2	.EQU	4		; INT enable reg. 2 (write)

ACIAISR2	.EQU	4		; INT status reg. 2 (read)

ACIACR2		.EQU	5		; Control register 2 (write)

ACIAFR2		.EQU	5		; Format register 2 (write)

ACIACSR2	.EQU	5		; Control status reg. 2 (read)

ACIACDR2	.EQU	6		; Compare data reg. 2 (write)

ACIAACR2	.EQU	6		; Aux. Control reg. 2 (write)

ACIATDR2	.EQU	7		; TX Data reg. 2 (write)

ACIARDR2	.EQU	7		; RX Data reg. 2 (read)

.ENDIF

;----------------------------------------------------------

.IFDEF		_DMA_INC_

; registri UM8388

FDCC		.EQU	$00FD58

; NOTA - INT azzerato con una operazione IO sul CHIP

FDCDOR		.EQU	$00FDDA 	; (solo scrittura)

FDCMSR		.EQU	$00FDDC 	; (solo lettura)

FDCDATA		.EQU	$00FDDD

FDCDIR		.EQU	$00FDDF 	; (solo lettura)

FDCCCR		.EQU	$00FDDF 	; (solo scrittura)

; registri 82C37 - DMA 1 (FDC)

DMAC		.EQU	$00FD90

DMAADDR0	.EQU	0

DMACNT0		.EQU	1

DMAADDR1	.EQU	2

DMACNT1		.EQU	3

DMAADDR2	.EQU	4

DMACNT2		.EQU	5

DMAADDR3	.EQU	6

DMACNT3		.EQU	7

DMASR		.EQU	$00FD98		; read STATUS REG

DMAWCMD		.EQU	$00FD98		; write COMMAND REG.

DMARQR		.EQU	$00FD99		; read/write REQUEST REG

DMAWMSKB	.EQU	$00FD9A		; write MASK BIT REG

DMARCMD		.EQU	$00FD9A		; read COMMAND REG.

DMAMODE		.EQU	$00FD9B		; read/write MODE REG.

DMARSETFF	.EQU	$00FD9C		; read - set FF (no data)

DMAWCLRFF	.EQU	$00FD9C		; write  - clear FF (no data)

DMARTMP		.EQU	$00FD9D		; read - read temp. register

DMAWMCLR	.EQU	$00FD9D		; write - MASTER CLEAR (no data)

DMARCNT		.EQU	$00FD9E		; read - clr mode reg. cnt. (no data)

DMAWMASKOFF	.EQU	$00FD9E		; write - clr mask register (no data)

DMAMASK		.EQU	$00FD9F		; read/write - mask register

DMAC0		.EQU	$00FD80

DMA0SR		.EQU	$00FD88		; read STATUS REG

DMA0WCMD	.EQU	$00FD88		; write COMMAND REG.

DMA0RQR		.EQU	$00FD89		; read/write REQUEST REG

DMA0WMSKB	.EQU	$00FD8A		; write MASK BIT REG

DMA0RCMD	.EQU	$00FD8A		; read COMMAND REG.

DMA0MODE	.EQU	$00FD8B		; read/write MODE REG.

DMA0RSETFF	.EQU	$00FD8C		; read - set FF (no data)

DMA0WCLRFF	.EQU	$00FD8C		; write  - clear FF (no data)

DMA0RTMP	.EQU	$00FD8D		; read - read temp. register

DMA0WMCLR	.EQU	$00FD8D		; write - MASTER CLEAR (no data)

DMA0RCNT	.EQU	$00FD8E		; read - clr mode reg. cnt. (no data)

DMA0WMASKOFF	.EQU	$00FD8E		; write - clr mask register (no data)

DMA0MASK	.EQU	$00FD8F		; read/write - mask register

.ENDIF

;----------------------------------------------------------

.IFDEF		_VBB_INC_

; registri R6545 / HD6445

CRTAddr		.EQU	$00FC70

CRTStatus	.EQU	$00FC70

CRTData		.EQU	$00FC71

PIAVBB		.EQU	$00FC74		; PIA VIDEO BOARD

URLVBB		.EQU	$00FC72		; registro underline write only 4 bit

.ENDIF