WebSVN – MB01 Project – Blame – /trunk/gal/20140501-MB01-TEST_DMA/PLD/#0166.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0166.PLD)
		2
		3	1 \|\| FILE: #0166.PLD
		4	2 \|\| PROJ: 20170501
		5	3 \|\| FD-02 FDC/ATA/DMA BOARD
		6	4 \|\|
		7	5 \|\| PART: G22V10-#0050
		8	6 \|\|
		9	7 \|\| DEV : GAL22V10
		10	8 \|\|
		11	9 \|\| DESC: RAM ACCESS CONTROL
		12	10 \|\|
		13	11 \|
		14	12 \|GAL22V10
		15	13 \|
		16	14 \|\| input signal description
		17	15 \|\| GEN = gate enable
		18	16 \|\| /DMA = dma enable
		19	17 \|\| DIR = dma data bus direction (1 => read, 0 => write)
		20	18 \|\| /S1M = enable 1Mb ram bank (otherwise 128k)
		21	19 \|\| ATA = dma ata port select (0 => port 0, 1 => port 1)
		22	20 \|\| /FDC = enable dma for fdc operation (otherwise ata)
		23	21 \|\| /ALT = enable dma1 to use 1Mb ram bank (otherwise use 128Kb)
		24	22 \|\|
		25	23 \|\| INPUT
		26	24 \| 1:MA0, 2:CX2, 3:GEN, 4:OE0, 5:OE1, 6:DMA, 7:RW, 8:DIR,
		27	25 \| 9:S1M, 10:ATA, 11:FDC, 13:ALT,
		28	26 \|\| OUTPUT
		29	27 \| 14:CEL, 15:CEH, 16:CER, 17:ENL, 18:ENH, 19:BE0,
		30	28 \| 20:BE1, 21:MDIR, 22:AEN, 23:A16E
		31	29 \|
		32	30 \| ACTIVE-LOW: CEL, CEH, CER, ENL, ENH, BE0, BE1, A16E
		33	31 \|
		34	32 \|
		35	33 \| SIGNATURE: "0166 "
		36	34 \|
		37	35 \|\| --------------------------------------------------------
		38	36 \|\| common signals when dma disabled (DMA = 1 => cpu access)
		39	37 \|\|
		40	38 \| RAM0 = CX2' & DMA & OE0 \|\| cpu access ram (dma0 = off)
		41	39 \| RAM1 = CX2' & DMA & OE1 \|\| cpu access ram (dma1 = off)
		42	40 \| MLC0 = RAM0 & S1M' & MA0' \|\| cpu access 1Mb even ram
		43	41 \| MLC1 = RAM1 & S1M' & MA0' \|\| cpu access 1Mb even ram
		44	42 \| MHC0 = RAM0 & S1M' & MA0 \|\| cpu access 1Mb odd ram
		45	43 \| MHC1 = RAM1 & S1M' & MA0 \|\| cpu access 1Mb odd ram
		46	44 \| MLCA = MLC0 # MLC1 \|\| cpu access 1Mb even ram
		47	45 \| MHCA = MHC0 # MHC1 \|\| cpu access 1Mb odd ram
		48	46 \| MLCS = MLCA & GEN \|\| cpu select 1Mb even ram
		49	47 \| MHCS = MHCA & GEN \|\| cpu select 1Mb odd ram
		50	48 \| MMC0 = RAM0 & S1M \|\| cpu access 128Kb ram
		51	49 \| MMC1 = RAM1 & S1M \|\| cpu access 128Kb ram
		52	50 \| MMCS = (MMC0 # MMC1) & GEN \|\| cpu select 128Kb ram
		53	51 \|\|
		54	52 \| CDIR = RW & DMA & OE0 & OE1 \|\| cpu bus direction to 1Mb ram
		55	53 \|\|
		56	54 \|\| common signals when dma enabled (DMA = 0)
		57	55 \| D0ON = DMA' & OE0' & OE1 & FDC \|\| dma0 master
		58
		59
		60	58 \| D1MBL = D1MB & MA0' \|\| dma1 access 1Mb even ram
		61	59 \| D1MBH = D1MB & MA0 \|\| dma1 access 1Mb odd ram
		62	60 \| D128K = D1ON & ALT \|\| dma1 access 128kb ram
		63	61 \|\|
		64	62 \| D0DIR = DIR & DMA' & FDC \|\| dma0 bus direction to 1Mb ram
		65	63 \| D1DIR = DIR' & DMA' & FDC' \|\| dma1 bus direction to 1Mb ram
		66	64 \|\|
		67	65 \|\| output signals
		68	66 \| CEL = MLCS # D0ON # D1MBL \|\| select even ram 1Mb
		69	67 \| CEH = MHCS # D0ON # D1MBH \|\| select odd ram 1Mb
		70	68 \| CER = MMCS # D128K \|\| select ram 128Kb
		71	69 \| ENL = MLCA # D1MBL \|\| data bus to 1Mb even ram
		72	70 \| ENH = MHCA # D1MBH \|\| data bus to 1Mb even ram
		73	71 \| BE0 = D0ON & ATA' \|\| ata0 data bus to 1Mb ram
		74	72 \| BE1 = D0ON & ATA \|\| ata1 data bus to 1Mb ram
		75	73 \| AEN = DMA' \|\| cpu address enable
		76	74 \| A16E = D1ON \|\| enable extern A16 line for dma1
		77	75 \| MDIR = CDIR # D0DIR # D1DIR \|\| bus direction to 1Mb ram
		78
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		82
		83
		84	I202 7/29/17 6:18 am (Saturday)
		85
		86
		87	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0166.PLA)
		88
		89
		90
		91	RESOLVED EXPRESSIONS (Reduction 0)
		92
		93
		94
		95
		96	124 MA0' CX2' GEN OE1 DMA S1M'
		97
		98	126 OE0' OE1 DMA' FDC
		99
		100	CEH 112 MA0 CX2' GEN OE0 DMA S1M'
		101	113 MA0 CX2' GEN OE1 DMA S1M'
		102	114 MA0 OE0 OE1' DMA' FDC' ALT'
		103	115 OE0' OE1 DMA' FDC
		104
		105	ENL 84 MA0' OE0 OE1' DMA' FDC' ALT'
		106	85 MA0' CX2' OE0 DMA S1M'
		107	86 MA0' CX2' OE1 DMA S1M'
		108
		109
		110	68 MA0 CX2' OE0 DMA S1M'
		111	69 MA0 CX2' OE1 DMA S1M'
		112
		113
		114	100 CX2' GEN OE1 DMA S1M
		115	101 OE0 OE1' DMA' FDC' ALT
		116
		117
		118
		119	BE1 35 OE0' OE1 DMA' ATA FDC
		120
		121
		122
		123
		124
		125
		126	23 DMA' DIR' FDC'
		127
		128
		129
		130
		131	SIGNAL ASSIGNMENT
		132	Rows
		133
		134
		135
		136
		137	2. CX2 4 - - - High
		138	3. GEN 8 - - - High
		139	4. OE0 12 - - - High
		140	5. OE1 16 - - - High
		141
		142	7. RW 24 - - - High
		143	8. DIR 28 - - - High
		144	9. S1M 32 - - - High
		145	10. ATA 36 - - - High
		146	11. FDC 40 - - - High
		147	13. ALT 42 - - - High
		148	14. CEL 39 122 9 4 Low (Three-state)
		149	15. CEH 35 111 11 4 Low (Three-state)
		150	16. CER 31 98 13 3 Low (Three-state)
		151	17. ENL 27 83 15 3 Low (Three-state)
		152	18. ENH 23 66 17 3 Low (Three-state)
		153	19. BE0 19 49 17 1 Low (Three-state)
		154	20. BE1 15 34 15 1 Low (Three-state)
		155	21. MDIR 10 21 13 3 High (Three-state)
		156	22. AEN 6 10 11 1 High (Three-state)
		157	23. A16E 3 1 9 1 Low (Three-state)
		158	25. - - 0 1 0
		159	26. - - 131 1 0
		160	---- ----
		161	132 24 (18%)
		162
		163
		164	I200 No fatal errors found in source code (device phase).
		165	I201 No warnings.
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		169
		170	*
		171	QP24* QF5828* QV1024*
		172
		173
		174
		175	L0440 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		176	L0484 11 11 11 11 11 11 11 11 11 11 10 11 11 11 11 11 11 11 11 11 11 11 *
		177	L0924 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		178	L0968 11 11 11 11 11 11 01 11 01 11 01 11 01 11 11 11 11 11 11 11 11 11 *
		179	L1012 11 11 11 11 11 11 11 11 11 11 10 11 11 11 10 11 11 11 11 11 10 11 *
		180	L1056 11 11 11 11 11 11 11 11 11 11 10 11 11 11 01 11 11 11 11 11 01 11 *
		181	L1496 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		182	L1540 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 01 11 01 11 *
		183	L2156 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		184	L2200 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 10 11 01 11 *
		185	L2904 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		186	L2948 01 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
		187	L2992 01 11 10 11 11 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		188	L3036 01 11 10 11 11 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		189	L3652 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		190	L3696 10 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
		191	L3740 10 11 10 11 11 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		192	L3784 10 11 10 11 11 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		193	L4312 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		194	L4356 11 11 10 11 01 11 01 11 11 11 01 11 11 11 11 11 01 11 11 11 11 11 *
		195	L4400 11 11 10 11 01 11 11 11 01 11 01 11 11 11 11 11 01 11 11 11 11 11 *
		196	L4444 11 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 01 *
		197	L4884 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		198	L4928 01 11 10 11 01 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		199	L4972 01 11 10 11 01 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		200	L5016 01 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
		201	L5060 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 11 11 01 11 *
		202	L5368 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		203	L5412 10 11 10 11 01 11 01 11 11 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		204	L5456 10 11 10 11 01 11 11 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		205	L5500 10 11 11 11 11 11 01 11 10 11 10 11 11 11 11 11 11 11 11 11 10 10 *
		206	L5544 11 11 11 11 11 11 10 11 01 11 10 11 11 11 11 11 11 11 11 11 01 11 *
		207	L5808 01 11 11 01 01 01 01 01 01 01 *
		208	CB4F2*
		209
		210	I202 7/29/17 6:18 am (Saturday)
		211	I203 Memory usage 8K
		212	I204 Elapsed time 1 second
		213

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