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||	FILE:	#0166.PLD
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||	PROJ:	20170501
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||		FD-02 FDC/ATA/DMA BOARD
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||
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||	PART:	G22V10-#0050
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||
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||	DEV :	GAL22V10
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||
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|| 	DESC:	RAM ACCESS CONTROL
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||
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|
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|GAL22V10
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|
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|| input signal description
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|| GEN  = gate enable
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|| /DMA = dma enable
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|| DIR  = dma data bus direction (1 => read, 0 => write)
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|| /S1M = enable 1Mb ram bank (otherwise 128k)
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|| ATA  = dma ata port select (0 => port 0, 1 => port 1)
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|| /FDC = enable dma for fdc operation (otherwise ata)
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|| /ALT = enable dma1 to use 1Mb ram bank (otherwise use 128Kb)
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||
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|| INPUT
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|  1:MA0, 2:CX2, 3:GEN, 4:OE0, 5:OE1, 6:DMA, 7:RW, 8:DIR,
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|  9:S1M, 10:ATA, 11:FDC, 13:ALT,
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|| OUTPUT
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|  14:CEL, 15:CEH, 16:CER, 17:ENL, 18:ENH, 19:BE0,
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|  20:BE1, 21:MDIR, 22:AEN, 23:A16E
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|
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| ACTIVE-LOW: CEL, CEH, CER, ENL, ENH, BE0, BE1, A16E
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|
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|
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| SIGNATURE: "0166    "
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|
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|| --------------------------------------------------------
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|| common signals when dma disabled (DMA = 1 => cpu access)
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||
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|  RAM0  = CX2' & DMA & OE0		|| cpu access ram (dma0 = off)
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|  RAM1  = CX2' & DMA & OE1		|| cpu access ram (dma1 = off)
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|  MLC0  = RAM0 & S1M' & MA0'		|| cpu access 1Mb even ram
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|  MLC1  = RAM1 & S1M' & MA0'		|| cpu access 1Mb even ram
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|  MHC0  = RAM0 & S1M' & MA0		|| cpu access 1Mb odd  ram
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|  MHC1  = RAM1 & S1M' & MA0		|| cpu access 1Mb odd  ram
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|  MLCA  = MLC0 # MLC1			|| cpu access 1Mb even ram
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|  MHCA  = MHC0 # MHC1			|| cpu access 1Mb odd  ram
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|  MLCS  = MLCA & GEN			|| cpu select 1Mb even ram
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|  MHCS  = MHCA & GEN			|| cpu select 1Mb odd  ram
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|  MMC0  = RAM0 & S1M 			|| cpu access 128Kb ram
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|  MMC1  = RAM1 & S1M			|| cpu access 128Kb ram
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|  MMCS  = (MMC0 # MMC1) & GEN		|| cpu select 128Kb ram
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||
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|  CDIR  = RW & DMA & OE0 & OE1		|| cpu bus direction to 1Mb ram
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||
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|| common signals when dma enabled (DMA = 0)
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|  D0ON  = DMA' & OE0' & OE1  & FDC	|| dma0 master
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|  D1ON  = DMA' & OE0  & OE1' & FDC'	|| dma1 master
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|  D1MB  = D1ON & ALT'			|| dma1 access 1Mb ram
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|  D1MBL = D1MB & MA0'			|| dma1 access 1Mb even ram
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|  D1MBH = D1MB & MA0			|| dma1 access 1Mb odd  ram
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|  D128K = D1ON & ALT			|| dma1 access 128kb ram
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||
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|  D0DIR = DIR  & DMA' & FDC		|| dma0 bus direction to 1Mb ram
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|  D1DIR = DIR' & DMA' & FDC'		|| dma1 bus direction to 1Mb ram
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||
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|| output signals
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|  CEL   = MLCS # D0ON # D1MB		|| select even ram 1Mb
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|  CEH   = MHCS # D0ON # D1MB		|| select odd  ram 1Mb
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|  CER   = MMCS # D128K			|| select ram 128Kb
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|  ENL   = MLCA # D1MBL			|| data bus to 1Mb even ram
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|  ENH   = MHCA	# D1MBH			|| data bus to 1Mb even ram
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|  BE0   = D0ON & ATA'			|| ata0 data bus to 1Mb ram
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|  BE1   = D0ON & ATA			|| ata1 data bus to 1Mb ram
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|  AEN   = DMA'				|| cpu address enable
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|  A16E  = D1ON				|| enable extern A16 line for dma1
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|  MDIR  = CDIR # D0DIR # D1DIR		|| bus direction to 1Mb ram