WebSVN – MB01 Project – Blame – /trunk/gal/20140501-MB01-TEST_DMA/PLD/#0165B.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0165B.PLD)
		2
		3	1 \|\| FILE: #0165.PLD
		4	2 \|\| PROJ: 20170501
		5	3 \|\| FD-02 FDC/ATA/DMA BOARD
		6	4 \|\|
		7	5 \|\| PART: G26CV12-#0165
		8	6 \|\|
		9	7 \|\| DEV : GAL26CV12
		10	8 \|\|
		11	9 \|\| DESC: DECODER I/O
		12	10 \|\|
		13	11 \|
		14	12 \|GAL26CV12
		15	13 \|
		16	14 \|\| GEN = gate enable
		17	15 \|\| /MGE = ram gate enable (/OE0 nor /OE 1)
		18	16 \|\| INPUT
		19	17 \| 1:A1, 2:-, 3:A3, 4:A4, 5:A5, 6:A6, 8:IO, 9:RW, 10:PHI2,
		20	18 \| 11:CX2, 12:MGE, 13:PHI0, 14:DMA, 28:GEN,
		21	19 \|\| OUTPUT
		22	20 \| 15:CE0, 16:CE1, 17:AT0, 18:AT1, 19:CE2, 20:DBE, 22:DDE, 23:CE3,
		23	21 \| 24:MRD, 25:MWE, 26:IOR, 27:IOW
		24	22 \|
		25	23 \| ACTIVE-LOW: CE0, CE1, AT0, AT1, CE2, DBE, DDE, MRD, MWE, IOR, IOW
		26	24 \|
		27	25 \|
		28	26 \| SIGNATURE: "0165B "
		29	27 \|
		30	28 \|\| --------------------------------------------------------
		31	29 \|\| common signals when dma disblad (DMA = 1 => cpu access)
		32	30 \|\|
		33	31 \| SCX2 = CX2' & DMA \|\| ram select when cpu access
		34	32 \| FDD0 = IO' & A6 & A5' & A4 \|\| select FDD0-FDDF
		35	33 \| FDC = FDD0 & A3 & DMA \|\| fdc select FDD8-FDDF
		36	34 \| DM0 = IO' & A6' & A5' & A4' & DMA \|\| dma0 select FD80-FD8F
		37	35 \| DM1 = IO' & A6' & A5' & A4 & DMA \|\| dma1 select FD90-FD9F
		38	36 \| ATA0 = IO' & A6' & A5 & A4' & DMA \|\| ata0 select FDA0-FDAF
		39	37 \| ATA1 = IO' & A6' & A5 & A4 & DMA \|\| ata1 select FDB0-FDBF
		40	38 \|\| VIA = IO' & A6 & A5' & A4' \|\| via select FDC0-FDCF (always)
		41	39 \|\| USB = FDD0 & A3' & A2' & A1' \|\| usb select FDD0-FDD1 (always)
		42	40 \|\|
		43	41 \| FDCR = FDC & RW & GEN & PHI2 \|\| cpu read fdc 02 sync
		44	42 \| FDCW = FDC & RW' & PHI2 \|\| cpu write fdc 02 sync
		45	43 \| DM0R = DM0 & RW & PHI2 \|\| cpu read dma0 02 sync
		46	44 \| DM0W = DM0 & RW' & PHI2 \|\| cpu write dma0 00 sync
		47	45 \| DM1R = DM1 & RW & PHI2 \|\| cpu read dma1 02 sync
		48	46 \| DM1W = DM1 & RW' & PHI2 \|\| cpu write dma1 00 sync
		49	47 \| IORD = FDCR # DM0R # DM1R \|\| cpu read fdc, dma0, dma1
		50	48 \| IOWE = FDCW # DM0W # DM1W \|\| cpu write fdc, dma0, dma1
		51	49 \|\|
		52	50 \| MEMR = SCX2 & MGE' & RW & PHI2 \|\| cpu read ram
		53	51 \| MEMW = SCX2 & MGE' & RW' & PHI0 \|\| cpu write ram (00 sync)
		54	52 \|\|
		55	53 \|\| global data bus enable for cpu access
		56	54 \|\| DBEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1 # VIA # USB
		57	55 \| DBEE = SCX2 # IO'
		58
		59
		60	58 \|\| local shared dma data bus enable for cpu access
		61	59 \| DDEE = SCX2 # FDC # DM0 # DM1 # ATA0 # ATA1
		62	60 \|\|
		63	61 \|\| output signals
		64	62 \| CE0 = DM0 \|\| dma0 FD80-FD8F
		65	63 \| CE1 = DM1 \|\| dma1 FD90-FD9F
		66	64 \| AT0 = ATA0 \|\| ata0 FDA0-FDAF
		67	65 \| AT1 = ATA1 \|\| ata1 FDA0-FDAF
		68	66 \| CE2 = FDC \|\| fdc FDD8-FDDF
		69	67 \| CE3 = FDC \|\| fdc FDD8-FDDF (positive)
		70	68 \| IOR = DMA ?? IORD \|\| i/o read strobe 3-states
		71	69 \| IOW = DMA ?? IOWE \|\| i/o write strobe 3-states
		72	70 \| MWE = DMA ?? MEMW \|\| write ram strobe 3-states
		73	71 \| MRD = DMA ?? MEMR \|\| read ram strobe 3-states
		74	72 \|\| DBE = DBEE & GEN \|\| global data bus enable
		75	73 \|\| DDE = DDEE & GEN \|\| local data bus enable
		76	74 \| DBE = DBEE \|\| global data bus enable
		77	75 \| DDE = DDEE \|\| local data bus enable
		78
		79
		80
		81
		82
		83
		84	I202 2/17/18 12:31 pm (Saturday)
		85
		86
		87	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0165B.PLA)
		88
		89
		90
		91	RESOLVED EXPRESSIONS (Reduction 0)
		92
		93
		94
		95
		96
		97
		98	50 A4' A5' A6' IO' DMA
		99
		100	52 A4 A5' A6' IO' DMA
		101
		102	54 CX2' DMA
		103
		104	CE1 104 A4 A5' A6' IO' DMA
		105
		106	AT0 95 A4' A5 A6' IO' DMA
		107
		108
		109
		110
		111
		112
		113
		114
		115	11 A3 A4 A5' A6 IO' RW PHI2 DMA GEN
		116
		117	13 A4 A5' A6' IO' RW PHI2 DMA
		118
		119	IOW 1 DMA
		120	2 A3 A4 A5' A6 IO' RW' PHI2 DMA
		121	3 A4' A5' A6' IO' RW' PHI2 DMA
		122	4 A4 A5' A6' IO' RW' PHI2 DMA
		123
		124	MWE 19 DMA
		125	20 RW' CX2' MGE' PHI0 DMA
		126
		127	MRD 28 DMA
		128
		129
		130	DBE 62 CX2' DMA
		131
		132
		133
		134
		135	SIGNAL ASSIGNMENT
		136	Rows
		137
		138
		139
		140
		141	2. - 4 - - -
		142	3. A3 8 - - - High
		143	4. A4 12 - - - High
		144	5. A5 16 - - - High
		145
		146	8. IO 24 - - - High
		147	9. RW 28 - - - High
		148	10. PHI2 32 - - - High
		149	11. CX2 36 - - - High
		150	12. MGE 40 - - - High
		151	13. PHI0 44 - - - High
		152	14. DMA 48 - - - High
		153	15. CE0 51 112 9 1 Low (Three-state)
		154	16. CE1 47 103 9 1 Low (Three-state)
		155	17. AT0 43 94 9 1 Low (Three-state)
		156	18. AT1 39 85 9 1 Low (Three-state)
		157	19. CE2 35 74 11 1 Low (Three-state)
		158	20. DBE 31 61 13 2 Low (Three-state)
		159	22. DDE 27 48 13 6 Low (Three-state)
		160	23. CE3 22 37 11 1 High (Three-state)
		161	24. MRD 19 28 9 2 Low (Three-state)
		162	25. MWE 15 19 9 2 Low (Three-state)
		163	26. IOR 11 10 9 4 Low (Three-state)
		164	27. IOW 7 1 9 4 Low (Three-state)
		165	28. GEN 2 - - - High
		166	29. - - 0 1 0
		167	30. - - 121 1 0
		168	---- ----
		169	122 26 (21%)
		170
		171
		172	I200 No fatal errors found in source code (device phase).
		173	I201 No warnings.
		174
		175
		176
		177
		178	*
		179	QP28* QF6432* QV1024*
		180
		181
		182
		183	L0156 1111111111111011101110111011101101111111111111110111*
		184	L0208 1111111111110111101110111011101101111111111111110111*
		185	L0520 1111111111111111111111111111111111111111111111110111*
		186	L0572 1101111101110111101101111011011101111111111111110111*
		187	L0624 1111111111111011101110111011011101111111111111110111*
		188	L0676 1111111111110111101110111011011101111111111111110111*
		189	L0988 1111111111111111111111111111111111111111111111110111*
		190	L1040 1111111111111111111111111111101111111011101101110111*
		191	L1456 1111111111111111111111111111111111111111111111110111*
		192	L1508 1111111111111111111111111111011101111011101111110111*
		193	L1924 1111111111111111111111111111111111111111111111111111*
		194	L1976 1111111101110111101101111011111111111111111111110111*
		195	L2496 1111111111111111111111111111111111111111111111111111*
		196	L2548 1111111101110111101101111011111111111111111111110111*
		197	L2600 1111111111111011101110111011111111111111111111110111*
		198	L2652 1111111111111011011110111011111111111111111111110111*
		199	L2704 1111111111110111101110111011111111111111111111110111*
		200	L2756 1111111111110111011110111011111111111111111111110111*
		201	L2808 1111111111111111111111111111111111111011111111110111*
		202	L3172 1111111111111111111111111111111111111111111111111111*
		203	L3224 1111111111111111111111111111111111111011111111110111*
		204	L3276 1111111111111111111111111011111111111111111111111111*
		205	L3848 1111111111111111111111111111111111111111111111111111*
		206	L3900 1111111101110111101101111011111111111111111111110111*
		207	L4420 1111111111111111111111111111111111111111111111111111*
		208	L4472 1111111111110111011110111011111111111111111111110111*
		209	L4888 1111111111111111111111111111111111111111111111111111*
		210	L4940 1111111111111011011110111011111111111111111111110111*
		211	L5356 1111111111111111111111111111111111111111111111111111*
		212	L5408 1111111111110111101110111011111111111111111111110111*
		213	L5824 1111111111111111111111111111111111111111111111111111*
		214	L5876 1111111111111011101110111011111111111111111111110111*
		215	L6344 0101010111010101010101010011000000110001001101100011*
		216	L6396 010101000010001000000010000000100000*
		217	CD9AA*
		218
		219	I202 2/17/18 12:31 pm (Saturday)
		220	I203 Memory usage 9K
		221	I204 Elapsed time 1 second
		222

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