WebSVN – MB01 Project – Blame – /trunk/gal/20130517-MB01-VGA/PLD/#9006.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#9006.PLD)
		2
		3	1 \|\| FILE: #9006.PLD
		4	2 \|\| PROJ: 20130517
		5	3 \|\| PART: G16V8-#9006
		6	4 \|\|
		7	5 \|\| DEV : GAL16V8
		8	6 \|\|
		9	7 \|\| DESC: DPRAM CONTROL
		10	8 \|\|
		11	9 \|
		12	10 \|GAL16V8A
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:A10, 2:A11, 3:A12, 4:CX1, 5:RW, 6:PHI2, 7:RES, 8:WP, 9:REN, 11:X,
		16	14 \|\| OUTPUT
		17	15 \| 12:RAMN, 13:CE0, 14:CE1, 15:CE2, 16:Y, 17:VRMN, 18:RS, 19:INH
		18	16 \|
		19	17 \|\|
		20	18 \| ACTIVE-LOW: CE0, CE1, CE2, RAMN, VRMN
		21	19 \|
		22	20 \| PROPERTY: "SIMPLE"
		23	21 \|
		24	22 \| SIGNATURE: "9006 "
		25	23 \|
		26	24 \|\| --------------------------------------------------------
		27	25 \|\| RAM0, RAM1, RAM2
		28	26 \| RAM0 = (CX1' & A12' & A11')
		29	27 \| RAM1 = (CX1' & A12' & A11)
		30	28 \| RAM2 = (CX1' & A12 & A11' & A10')
		31	29 \| VRAM = (RAM0 # RAM1 # RAM2)
		32	30 \| CE0R = (RAM0 & RW & PHI2)
		33	31 \| CE0W = (RAM0 & RW' & REN')
		34	32 \| CE1R = (RAM1 & RW & PHI2)
		35	33 \| CE1W = (RAM1 & RW' & REN')
		36	34 \| CE2R = (RAM2 & RW & PHI2)
		37	35 \| CE2W = (RAM2 & RW' & REN')
		38	36 \| CE0 = (CE0R # CE0W)
		39	37 \| CE1 = (CE1R # CE1W)
		40	38 \| CE2 = (CE2R # CE2W)
		41	39 \| INH = (VRAM & RW' & REN')
		42	40 \| RAMN = ((VRAM & RW & PHI2) # (VRAM & RW' & WP))
		43	41 \| Y = X
		44	42 \| VRMN = (VRAM & RW')
		45	43 \| RS = RES
		46
		47
		48
		49	I201 No warnings.
		50
		51
		52
		53	I203 Memory usage 85K
		54	I204 Elapsed time 1 second
		55	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#9006.PLA)
		56
		57	I289 Simple GAL architecture selected.
		58
		59
		60
		61
		62
		63
		64
		65	49 A11' A12' CX1' RW PHI2
		66
		67	RAMN 56 A10' A11' A12 CX1' RW' WP
		68	57 A10' A11' A12 CX1' RW PHI2
		69
		70	59 A11' A12' CX1' RW PHI2
		71	60 A11 A12' CX1' RW' WP
		72	61 A11 A12' CX1' RW PHI2
		73
		74	INH 0 A10' A11' A12 CX1' RW' REN'
		75	1 A11' A12' CX1' RW' REN'
		76
		77
		78	CE1 40 A11 A12' CX1' RW' REN'
		79	41 A11 A12' CX1' RW PHI2
		80
		81	CE2 32 A10' A11' A12 CX1' RW' REN'
		82	33 A10' A11' A12 CX1' RW PHI2
		83
		84	Y 24 X
		85
		86
		87	17 A11' A12' CX1' RW'
		88
		89
		90	RS 8 RES
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		98
		99	1. A10 2 - - - High (Clock)
		100	2. A11 0 - - - High
		101	3. A12 4 - - - High
		102
		103	5. RW 12 - - - High
		104	6. PHI2 16 - - - High
		105	7. RES 20 - - - High
		106	8. WP 24 - - - High
		107	9. REN 28 - - - High
		108	11. X 30 - - - High (Enable)
		109	12. RAMN 27 56 8 6 Low
		110	13. CE0 23 48 8 2 Low
		111	14. CE1 19 40 8 2 Low
		112	15. CE2 1 32 8 2 Low
		113	16. Y 0 24 8 1 High
		114	17. VRMN 15 16 8 3 Low
		115	18. RS 10 8 8 1 High
		116	19. INH 6 0 8 3 High
		117	---- ----
		118	64 20 (31%)
		119
		120
		121	I200 No fatal errors found in source code (device phase).
		122	I201 No warnings.
		123
		124
		125	OrCAD DEVICE
		126	Type: GAL16V8
		127
		128
		129
		130	L0000 10 10 01 11 10 11 10 11 11 11 11 11 11 11 10 11 *
		131	L0032 10 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
		132	L0064 01 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
		133	L0256 11 11 11 11 11 11 11 11 11 11 01 11 11 11 11 11 *
		134	L0512 10 10 01 11 10 11 10 11 11 11 11 11 11 11 11 11 *
		135	L0544 10 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 *
		136	L0576 01 11 10 11 10 11 10 11 11 11 11 11 11 11 11 11 *
		137	L0768 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 01 *
		138	L1024 10 10 01 11 10 11 10 11 11 11 11 11 11 11 10 11 *
		139	L1056 10 10 01 11 10 11 01 11 01 11 11 11 11 11 11 11 *
		140	L1280 01 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
		141	L1312 01 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
		142	L1536 10 11 10 11 10 11 10 11 11 11 11 11 11 11 10 11 *
		143	L1568 10 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
		144	L1792 10 10 01 11 10 11 10 11 11 11 11 11 01 11 11 11 *
		145	L1824 10 10 01 11 10 11 01 11 01 11 11 11 11 11 11 11 *
		146	L1856 10 11 10 11 10 11 10 11 11 11 11 11 01 11 11 11 *
		147	L1888 10 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
		148	L1920 01 11 10 11 10 11 10 11 11 11 11 11 01 11 11 11 *
		149	L1952 01 11 10 11 10 11 01 11 01 11 11 11 11 11 11 11 *
		150	L2048 11 01 00 00 00 11 10 01 00 11 00 00 00 11 00 00 *
		151	L2080 00 11 01 10 00 10 00 00 00 10 00 00 00 10 00 00 *
		152	L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
		153	L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		154	L2176 11 11 11 11 11 11 11 11 10 *
		155	C5399*
		156
		157	I202 5/30/13 6:53 pm (Thursday)
		158	I203 Memory usage 6K
		159	I204 Elapsed time 1 second
		160

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