WebSVN – MB01 Project – Blame – /trunk/gal/20120601-MB01-65816/PLD/#0053L.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0053L.PLD)
		2
		3	1 \|\| FILE: #0053.PLD
		4	2 \|\| PROJ: 20120601
		5	3 \|\| PART: G26CV12-#0053
		6	4 \|\|
		7	5 \|\| DEV : GAL26CV12
		8	6 \|\|
		9	7 \|\| DESC: MASTER DECODER
		10	8 \|\|
		11	9 \|
		12	10 \|GAL26CV12
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:A9, 2:A10, 3:A11, 4:A12, 5:A13, 6:A14, 8:A15, 9:A16, 10:A17,
		16	14 \| 11:A18, 12:A19, 13:A20, 14:A21, 15:A22, 16:A23, 17:VMA, 18:RW,
		17	15 \| 24:HIM, 25:X0E, 26:X1E, 27:XFE, 28:FWE,
		18	16 \|\| OUTPUT
		19	17 \| 19:FE, 20:CS0, 22:ME, 23:CSF
		20	18 \|
		21	19 \| ACTIVE-LOW: FE, CS0, ME, CSF
		22	20 \|
		23	21 \|
		24	22 \| SIGNATURE: "0053L "
		25	23 \|
		26	24 \|\| VERSONE DEBUG/LOADER
		27	25 \|
		28	26 \|\| --------------------------------------------------------
		29	27 \|\| HIM -> MAPPA AREA 00FE00 - 00FFFF IN RAM INVECE CHE IN FLASH
		30	28 \|\| X0E -> ABILITA EXTERN MEMORY (/CX0) IN BANCO 1 AREA 010000 - 011FFF (8K)
		31	29 \|\| X1E -> ABILITA EXTERN MEMORY (/CX1) IN BANCO 1 AREA 012000 - 013FFF (8K)
		32	30 \|\| XFE -> ABILITA FLASH MEMORY BANCHI F0/F7 AREA F00000 - F7FFFF
		33	31 \|\| FWE -> ABILITA WRITE FLASH MEMORY
		34	32 \|\| --------------------------------------------------------
		35	33 \|\|
		36	34 \|\| /FE -> ABILITA FLASH MEMORY F00000 - F7FFFF (512K)
		37	35 \|\| /ME -> ABILITA BANCHI RAM DA 4MB (ESCLUSO CSX, BK0)
		38	36 \|\| BLOCCO F80000 - FFFFFF ABILITATO SE:
		39	37 \|\| HIM = 1 AND XFE = 1 AND RW = 0
		40	38 \|\| HIM = 0 AND RW = 1
		41	39 \|\| /CS0 -> PRIMO BLOCCO 128K IN 00000 - 01FFFF (ESCLUSO IO)
		42	40 \|\| /CSF -> BLOCCO FLASH IN F80000 - FFFFFF (512K)
		43	41 \|\| READ ONLY IF HIM = 1 AND XFE = 1
		44	42 \|\| MAPPA 00FE00 - 00FFFF IN F8FE00 - F8FFFF SE HIM=0 E RW=1
		45	43 \|\| --------------------------------------------------------
		46	44 \|\|
		47	45 \|\| ABILITAZIONE RAM RANGE 020000 - FFFFFF
		48	46 \|\| B4MH -> BLOCCO 4MB 800000 - BFFFFF
		49	47 \| B4MH = (VMA' & A23 & A22' )
		50	48 \|\| B2MH -> BLOCCO 2MB C00000 - DFFFFF
		51	49 \| B2MH = (VMA' & A23 & A22 & A21' )
		52	50 \|\| B1MH -> BLOCCO 1MB E00000 - EFFFFF
		53	51 \| B1MH = (VMA' & A23 & A22 & A21 & A20' )
		54	52 \|\| B5KA -> BLOCCO 512KB F00000 - F7FFFF (RAM SOLO SE XFE=0)
		55	53 \| B5KA = (VMA' & A23 & A22 & A21 & A20 & A19' & XFE')
		56	54 \|\| B5KB -> BLOCCO 512KB F00000 - F7FFFF (RAM SOLO SE XFE=1, FWE=0, RW=0)
		57	55 \| B5KB = (VMA' & A23 & A22 & A21 & A20 & A19' & XFE & FWE' & RW')
		58
		59
		60	58 \| B6KW = (B6K & HIM' & RW' & FWE)
		61	59 \| B6RM = (B6KR # B6KW)
		62	60 \|\|
		63	61 \|\| B4ML -> BLOCCO 4MB 400000 - 7FFFFF
		64	62 \| B4ML = (VMA' & A23' & A22 )
		65	63 \|\| B2ML -> BLOCCO 2MB 200000 - 3FFFFF
		66	64 \| B2ML = (VMA' & A23' & A22' & A21 )
		67	65 \|\| B1ML -> BLOCCO 1MB 100000 - 1FFFFF
		68	66 \| B1ML = (VMA' & A23' & A22' & A21' & A20 )
		69	67 \|\| B5KL -> BLOCCO 512KB 080000 - 0FFFFF
		70	68 \| B5KL = (VMA' & A23' & A22' & A21' & A20' & A19 )
		71	69 \|\|
		72	70 \|\| /ME -> ABILITAZIONE RAM RANGE 080000 - F7FFFF
		73	71 \| MXH = (B4MH # B2MH # B1MH # B5KA # B5KB)
		74	72 \| MXL = (B4ML # B2ML # B1ML # B5KL)
		75	73 \| ME = (MXL # MXH # B6RM)
		76	74 \|\|
		77	75 \|\| --------------------------------------------------------
		78	76 \|\|
		79	77 \| BANK0 = (A23' & A22' & A21' & A20' & A19' & A18' & A17' & A16' & VMA')
		80	78 \| BANK1 = (A23' & A22' & A21' & A20' & A19' & A18' & A17' & A16 & VMA')
		81	79 \|\| --------------------------------------------------------
		82	80 \|\|
		83	81 \|\| B0M -> ABILITAZIONE RAM RANGE 000000 - 00FFFF (BANCO 0)
		84	82 \|\|
		85	83 \|\| BLOCCO 32K
		86	84 \| RB0 = (BANK0 & A15' )
		87	85 \|\| BLOCCO 16K
		88	86 \| RB1 = (BANK0 & A15 & A14' )
		89	87 \|\| BLOCCO 8K
		90	88 \| RB2 = (BANK0 & A15 & A14 & A13' )
		91	89 \|\| BLOCCO 4K
		92	90 \| RB3 = (BANK0 & A15 & A14 & A13 & A12' )
		93	91 \|\| BLOCCO 2K
		94	92 \| RB4 = (BANK0 & A15 & A14 & A13 & A12 & A11' )
		95	93 \|\| BLOCCO 1K
		96	94 \| RB5 = (BANK0 & A15 & A14 & A13 & A12 & A11 & A10')
		97	95 \|\| ULTIMO BLOCCO 512B (00FE00 - 00FFFF)
		98	96 \| RB7 = (BANK0 & A15 & A14 & A13 & A12 & A11 & A10 & A9)
		99	97 \|\| RB7A -> RANGE 00FE00 - 00FFFF IN RAM SOLO SE HIM=1
		100	98 \| RB7A = (RB7 & HIM)
		101	99 \|\| RB7B -> RANGE 00FE00 - 00FFFF IN RAM SOLO SE RW=0
		102	100 \| RB7B = (RB7 & RW')
		103	101 \|\|
		104	102 \| B0M = (RB0 # RB1 # RB2 # RB3 # RB4 # RB5 # RB7A # RB7B)
		105	103 \|\| --------------------------------------------------------
		106	104 \|\|
		107	105 \|\| B1M -> ABILITAZIONE RAM RANGE 010000 - 01FFFF (BANCO 1)
		108	106 \|\|
		109	107 \|\| B32KH -> BLOCCO 32KB 018000 - 01FFFF
		110	108 \| B32KH = (BANK1 & A15)
		111	109 \|\| B16KH -> BLOCCO 16KB 014000 - 017FFF
		112	110 \| B16KH = (BANK1 & A15' & A14)
		113	111 \|\| B08KL -> BLOCCO 8KB 010000 - 011FFF
		114	112 \| B08KL = (BANK1 & A15' & A14' & A13' & X0E')
		115	113 \|\| B08KH -> BLOCCO 8KB 012000 - 013FFF
		116	114 \| B08KH = (BANK1 & A15' & A14' & A13 & X1E')
		117
		118
		119	117 \|\| --------------------------------------------------------
		120	118 \|\|
		121	119 \|\| /CS0 -> ABILITAZIONE RAM RANGE 000000 - 01FFFF (BANCHI 0 & 1)
		122	120 \| CS0 = (B0M # B1M)
		123	121 \|\| --------------------------------------------------------
		124	122 \|\|
		125	123 \|\| FS0 -> ABILITA FLASH RANGE F00000 - F7FFFF SOLO SE XFE=1
		126	124 \|\| FS0R -> ABILITA FLASH RANGE F00000 - F7FFFF SOLO LETTURA
		127	125 \| FS0R = (A23 & A22 & A21 & A20 & A19' & VMA' & RW & XFE)
		128	126 \|\| FS0W -> ABILITA FLASH RANGE F00000 - F7FFFF SOLO SCRITTURA (FWE=1)
		129	127 \| FS0W = (A23 & A22 & A21 & A20 & A19' & VMA' & RW' & XFE & FWE)
		130	128 \|\|
		131	129 \|\| /FE -> ABILITAZIONE FLASH RANGE F00000 - F7FFFF
		132	130 \| FE = (FS0R # FS0W)
		133	131 \|\| --------------------------------------------------------
		134	132 \|\|
		135	133 \|\| FS1 -> ABILITA FLASH RANGE F80000 - FFFFFF
		136	134 \|\| FS1R -> ABILITA FLASH RANGE F80000 - FFFFFF SOLO LETTURA
		137	135 \|\| FS1R = (A23 & A22 & A21 & A20 & A19 & VMA' & RW & HIM')
		138	136 \|\| FS1W -> ABILITA FLASH RANGE F80000 - FFFFFF SOLO SCRITTURA (FWE=1)
		139	137 \| FS1W = (A23 & A22 & A21 & A20 & A19 & VMA' & RW' & FWE & HIM)
		140	138 \|\| FS2R -> MAPPA RANGE 00FE00 - 00FFFF IN F8FE00 - F8FFFF (HIM=0, RW=1)
		141	139 \| FS2R = (RB7 & RW & HIM')
		142	140 \|\|
		143	141 \|\| /CSF -> ABILITAZIONE FLASH RANGE F80000 - FFFFFF
		144	142 \| CSF = (FS2R # FS1W)
		145
		146
		147	I200 No fatal errors found in source code (logic phase).
		148	I201 No warnings.
		149
		150
		151
		152	I203 Memory usage 133K
		153	I204 Elapsed time 1 second
		154
		155
		156
		157
		158	RESOLVED EXPRESSIONS (Reduction 0)
		159
		160	Signal name Row Terms
		161
		162
		163
		164
		165	52 A19 A20 A21 A22 A23 VMA' RW
		166
		167	54 A20' A21 A22 A23 VMA'
		168
		169	56 A21' A22 A23 VMA'
		170	57 A21 A22' A23' VMA'
		171	58 A22' A23 VMA'
		172	59 A22 A23' VMA'
		173
		174	CS0 62 A9 A10 A11 A12 A13 A14 A15 A16' A17' A18' A19'
		175	A20' A21' A22' A23' VMA' RW'
		176	63 A9 A10 A11 A12 A13 A14 A15 A16' A17' A18' A19'
		177	A20' A21' A22' A23' VMA' HIM
		178	64 A10' A11 A12 A13 A14 A15 A16' A17' A18' A19' A20'
		179	A21' A22' A23' VMA'
		180
		181	A22' A23' VMA'
		182	66 A12' A13 A14 A15 A16' A17' A18' A19' A20' A21' A22'
		183	A23' VMA'
		184	67 A13' A14' A15' A16 A17' A18' A19' A20' A21' A22' A23'
		185	VMA' X0E'
		186	68 A13 A14' A15' A16 A17' A18' A19' A20' A21' A22' A23'
		187	VMA' X1E'
		188	69 A13' A14 A15 A16' A17' A18' A19' A20' A21' A22' A23'
		189	VMA'
		190	70 A14' A15 A16' A17' A18' A19' A20' A21' A22' A23' VMA'
		191	71 A14 A15' A16 A17' A18' A19' A20' A21' A22' A23' VMA'
		192	72 A15' A16' A17' A18' A19' A20' A21' A22' A23' VMA'
		193	73 A15 A16 A17' A18' A19' A20' A21' A22' A23' VMA'
		194
		195	FE 75 A19' A20 A21 A22 A23 VMA' RW' XFE FWE
		196	76 A19' A20 A21 A22 A23 VMA' RW XFE
		197
		198	CSF 38 A9 A10 A11 A12 A13 A14 A15 A16' A17' A18' A19'
		199	A20' A21' A22' A23' VMA' RW HIM'
		200	39 A19 A20 A21 A22 A23 VMA' RW' HIM FWE
		201
		202
		203
		204
		205	Rows
		206	Pin Signal name Column -------------- Activity
		207	Beg Avail Used
		208
		209
		210
		211
		212	4. A12 12 - - - High
		213	5. A13 16 - - - High
		214	6. A14 20 - - - High
		215	8. A15 24 - - - High
		216
		217	10. A17 32 - - - High
		218	11. A18 36 - - - High
		219	12. A19 40 - - - High
		220	13. A20 44 - - - High
		221	14. A21 48 - - - High
		222	15. A22 50 112 9 0 High (Registered)
		223	16. A23 46 103 9 0 High (Registered)
		224	17. VMA 42 94 9 0 High (Registered)
		225	18. RW 38 85 9 0 High (Registered)
		226	19. FE 35 74 11 2 Low (Three-state)
		227	20. CS0 31 61 13 12 Low (Three-state)
		228	22. ME 27 48 13 11 Low (Three-state)
		229	23. CSF 23 37 11 2 Low (Three-state)
		230	24. HIM 18 28 9 0 High (Registered)
		231	25. X0E 14 19 9 0 High (Registered)
		232	26. X1E 10 10 9 0 High (Registered)
		233	27. XFE 6 1 9 0 High (Registered)
		234	28. FWE 2 - - - High
		235	29. - - 0 1 0
		236	30. - - 121 1 0
		237	---- ----
		238	122 27 (22%)
		239
		240
		241	I200 No fatal errors found in source code (device phase).
		242	I201 No warnings.
		243
		244
		245	OrCAD DEVICE
		246	Type: GAL26CV12
		247
		248
		249	F0*
		250	L1924 1111111111111111111111111111111111111111111111111111*
		251
		252
		253
		254	L2548 1110110111111111111111111111111111111110101001010101*
		255	L2600 1101111111111111111011111111111111111110011001010101*
		256	L2652 1111111011111111111111111111111111111111101001010101*
		257	L2704 1111111111111111111111111111111111111101011001010101*
		258	L2756 1111111111111111111111111111111111111111011010101010*
		259	L2808 1111111111111111111111111111111111111111111010010101*
		260	L2860 1111111111111111111111111111111111111111111001101010*
		261	L2912 1111111111111111111111111111111111111111111011011001*
		262	L2964 1111111111111111111111111111111111111111111011100110*
		263	L3016 1111111111111111111111111111111111111111111011011110*
		264	L3068 1111111111111111111111111111111111111111111011101101*
		265	L3172 1111111111111111111111111111111111111111111111111111*
		266	L3224 0111011101110111011101110111101110111010101010101010*
		267	L3276 0111011101110111010101110111101110111011101010101010*
		268	L3328 1111101101110111011101110111101110111011101010101010*
		269	L3380 1111111110110111011101110111101110111011101010101010*
		270	L3432 1111111111111011011101110111101110111011101010101010*
		271	L3484 1111111111111110101110111011011110111011101010101010*
		272	L3536 1111111111101111011110111011011110111011101010101010*
		273	L3588 1111111111111111101101110111101110111011101010101010*
		274	L3640 1111111111111111111110110111101110111011101010101010*
		275	L3692 1111111111111111111101111011011110111011101010101010*
		276	L3744 1111111111111111111111111011101110111011101010101010*
		277	L3796 1111111111111111111111110111011110111011101010101010*
		278	L3848 1111111111111111111111111111111111111111111111111111*
		279	L3900 1101110111111111111111111111111111111110101001010101*
		280	L3952 1111110111111111111111111111111111111101101001010101*
		281	L6344 1111111101010101111111110011000000110000001101010011*
		282	L6396 001101001100001000000010000000100000*
		283	CAE1D*
		284
		285	I202 5/27/13 9:23 am (Monday)
		286	I203 Memory usage 12K
		287	I204 Elapsed time 1 second
		288

Subversion Repositories MB01 Project

(root)/trunk/gal/20120601-MB01-65816/PLD/#0053L.LST – Rev 1