WebSVN – MB01 Project – Blame – /trunk/gal/20120600-MB01-MOTHERBOARD/PLD/#0155B.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0155B.PLD)
		2
		3	1 \|\| FILE: #0155.PLD
		4	2 \|\| PROJ: 20120600
		5	3 \|\| PART: G16V8-#0155
		6	4 \|\|
		7	5 \|\| DEV : GAL16V8
		8	6 \|\|
		9	7 \|\| DESC: DECODER ATA 0/1
		10	8 \|\|
		11	9 \|
		12	10 \|GAL16V8
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:A0, 2:A1, 3:A2, 4:A3, 5:RW, 6:PHI2, 7:ATA, 8:EN, 9:WA, 11:PHI0,
		16	14 \|\| OUTPUT
		17	15 \| 12:HWO, 13:HWC, 14:GA, 15:IOR, 16:IOW, 17:CS0, 18:CS1, 19:HRD
		18	16 \|
		19	17 \| ACTIVE-LOW: HWC, HWO, HRD, CS0, CS1, GA, IOR, IOW
		20	18 \|
		21	19 \| PROPERTY:"SIMPLE"
		22	20 \|
		23	21 \| SIGNATURE: "0155 "
		24	22 \|
		25	23 \|\| --------------------------------------------------------
		26	24 \|\| INDIRIZZO I/O ATA
		27	25 \| IOA = (ATA')
		28	26 \|\| --------------------------------------------------------
		29	27 \|\| ATAA => XXX0 - XXX7
		30	28 \| ATAA = (IOA & A3')
		31	29 \|\| ATAB => XXXE - XXXF
		32	30 \| ATAB = (IOA & A3 & A2 & A1)
		33	31 \|\| REGISTRO HIGH DATA ATA => XXXC
		34	32 \| HDA0 = (IOA & A3 & A2 & A1' & A0')
		35	33 \|\| REGISTRO DATI 16 BIT ATA => XXX0
		36	34 \| RDR0 = (ATAA & A2' & A1' & A0')
		37	35 \|\| --------------------------------------------------------
		38	36 \|\| CONTROLLO ATA
		39	37 \|\| CS0 => XXX0 - XXX7
		40	38 \| CS0 = ((ATAA & PHI2 & WA) # (ATAA & EN & WA'))
		41	39 \|\| CS1 => XXXE - XXXF
		42	40 \| CS1 = ((ATAB & PHI2 & WA) # (ATAB & EN & WA'))
		43	41 \| ATAX = (ATAA # ATAB)
		44	42 \| GA = ATAX
		45	43 \|\| --------------------------------------------------------
		46	44 \|\| SEGNALI ATA IOR, IOW
		47	45 \|\| IOR, IOW SINCRONIZZATI CON PHI2 (WA = 1)
		48	46 \| RD1 = (ATAX & WA & RW & PHI2)
		49	47 \| WR1 = (ATAX & WA & RW' & PHI0)
		50	48 \|\| IOR, IOW SINCRONIZZATI CON EN (WA = 0)
		51	49 \| RD2 = (ATAX & WA' & RW & EN)
		52	50 \| WR2 = (ATAX & WA' & RW' & EN)
		53	51 \| IOR = (RD1 # RD2)
		54	52 \| IOW = (WR1 # WR2)
		55	53 \|\| --------------------------------------------------------
		56	54 \|\| CONTROLLO REGISTRO HIGH ATA
		57	55 \|\| HWC => WRITE XXXC (comando clock)
		58
		59
		60	58 \| HRD = (HDA0 & RW)
		61	59 \|\| HWO => WRITE REG. ATA XXX0 (8 bit alti)
		62	60 \| HWO = (RDR0 & RW')
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		69	I202 6/10/13 6:04 pm (Monday)
		70
		71
		72	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0155B.PLA)
		73
		74	I289 Simple GAL architecture selected.
		75
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		82	17 A3' ATA' EN WA'
		83
		84	CS1 8 A1 A2 A3 PHI2 ATA' WA
		85
		86
		87	GA 40 A1 A2 A3 ATA'
		88
		89
		90	IOR 32 A1 A2 A3 RW PHI2 ATA' WA
		91
		92	34 A3' RW PHI2 ATA' WA
		93	35 A3' RW ATA' EN WA'
		94
		95	IOW 24 A1 A2 A3 RW' ATA' EN WA'
		96	25 A1 A2 A3 RW' ATA' WA PHI0
		97	26 A3' RW' ATA' EN WA'
		98	27 A3' RW' ATA' WA PHI0
		99
		100	HWC 48 A0' A1' A2 A3 RW' ATA' PHI0
		101
		102	HRD 0 A0' A1' A2 A3 RW ATA'
		103
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		108
		109	Rows
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		113
		114	2. A1 0 - - - High
		115	3. A2 4 - - - High
		116	4. A3 8 - - - High
		117	5. RW 12 - - - High
		118
		119	7. ATA 20 - - - High
		120	8. EN 24 - - - High
		121	9. WA 28 - - - High
		122	11. PHI0 30 - - - High (Enable)
		123	12. HWO 27 56 8 1 Low
		124	13. HWC 23 48 8 1 Low
		125	14. GA 19 40 8 2 Low
		126	15. IOR 1 32 8 4 Low
		127	16. IOW 1 24 8 4 Low
		128	17. CS0 15 16 8 2 Low
		129	18. CS1 11 8 8 2 Low
		130	19. HRD 7 0 8 1 Low
		131	---- ----
		132	64 17 (27%)
		133
		134
		135	I200 No fatal errors found in source code (device phase).
		136	I201 No warnings.
		137
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		140
		141	*
		142	QP20* QF2194* QV1024*
		143
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		145
		146	L0288 01 11 01 11 01 11 11 11 11 11 10 11 01 11 10 11 *
		147	L0512 11 11 11 11 10 11 11 11 01 11 10 11 11 11 01 11 *
		148	L0544 11 11 11 11 10 11 11 11 11 11 10 11 01 11 10 11 *
		149	L0768 01 11 01 11 01 11 10 11 11 11 10 11 01 11 10 11 *
		150	L0800 01 11 01 11 01 11 10 11 11 11 10 11 11 11 01 01 *
		151	L0832 11 11 11 11 10 11 10 11 11 11 10 11 01 11 10 11 *
		152	L0864 11 11 11 11 10 11 10 11 11 11 10 11 11 11 01 01 *
		153	L1024 01 11 01 11 01 11 01 11 01 11 10 11 11 11 01 11 *
		154	L1056 01 11 01 11 01 11 01 11 11 11 10 11 01 11 10 11 *
		155	L1088 11 11 11 11 10 11 01 11 01 11 10 11 11 11 01 11 *
		156	L1120 11 11 11 11 10 11 01 11 11 11 10 11 01 11 10 11 *
		157	L1280 01 11 01 11 01 11 11 11 11 11 10 11 11 11 11 11 *
		158	L1312 11 11 11 11 10 11 11 11 11 11 10 11 11 11 11 11 *
		159	L1536 10 10 01 11 01 11 10 11 11 11 10 11 11 11 11 01 *
		160	L1792 10 10 10 11 10 11 10 11 11 11 10 11 11 11 11 11 *
		161	L2048 00 00 00 00 00 11 00 00 00 11 00 01 00 11 01 01 *
		162	L2080 00 11 01 01 00 10 00 00 00 10 00 00 00 10 00 00 *
		163	L2112 00 10 00 00 00 00 00 00 11 11 11 11 11 11 11 11 *
		164	L2144 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		165	L2176 11 11 11 11 11 11 11 11 10 *
		166	C47AD*
		167
		168	I202 6/10/13 6:04 pm (Monday)
		169	I203 Memory usage 7K
		170	I204 Elapsed time 1 second
		171

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