WebSVN – MB01 Project – Blame – /trunk/gal/20120600-MB01-MOTHERBOARD/PLD/#0151.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0151.PLD)
		2
		3	1 \|\| FILE: #0151.PLD
		4	2 \|\| PROJ: 20120600
		5	3 \|\| PART: G20V8-#0151
		6	4 \|\|
		7	5 \|\| DEV : GAL20V8
		8	6 \|\|
		9	7 \|\| DESC: DECODER I/O WAIT
		10	8 \|\|
		11	9 \|
		12	10 \|GAL20V8A
		13	11 \|
		14	12 \|\| INPUT
		15	13 \| 1:A0, 2:A1, 3:A2, 4:A3, 5:A4, 6:A5, 7:A6, 8:A7,
		16	14 \| 9:IO1, 10:-, 11:WA0, 13:WA1, 14:WV, 23:WT,
		17	15 \|\| OUTPUT
		18	16 \| 15:ATA0, 16:ATA1, 17:DMA, 18:FDC, 19:VDC, 20:IOX, 21:PIA, 22:WAIT
		19	17 \|
		20	18 \| ACTIVE-LOW: ATA0, ATA1, DMA, FDC, VDC, IOX, PIA, WAIT
		21	19 \|
		22	20 \| PROPERTY: "SIMPLE"
		23	21 \|
		24	22 \| SIGNATURE: "0151 "
		25	23 \|
		26	24 \|\| --------------------------------------------------------
		27	25 \|\| ATA 0/1
		28	26 \|\| ATA0A => FE20 - FE27 (ATA 0)
		29	27 \| ATA0A = (IO1' & A7' & A6' & A5 & A4' & A3')
		30	28 \|\| ATA0B => FE2E - FF2F (ATA 0)
		31	29 \| ATA0B = (IO1' & A7' & A6' & A5 & A4' & A3 & A2 & A1)
		32	30 \|\| ATA0C => FE2C (ATA 0)
		33	31 \| ATA0C = (IO1' & A7' & A6' & A5 & A4' & A3 & A2 & A1' & A0')
		34	32 \|\| ATA1A => FE30 - FE37 (ATA 1)
		35	33 \| ATA1A = (IO1' & A7' & A6' & A5 & A4 & A3')
		36	34 \|\| ATA1B => FE3E - FE3F (ATA 1)
		37	35 \| ATA1B = (IO1' & A7' & A6' & A5 & A4 & A3 & A2 & A1)
		38	36 \|\| ATA1C => FE3C (ATA 1)
		39	37 \| ATA1C = (IO1' & A7' & A6' & A5 & A4 & A3 & A2 & A1' & A0')
		40	38 \|\|
		41	39 \|\| SELEZIONE ATA 0 -> FE20 - FE27, FE2C, FE2E - FE2F
		42	40 \| ATA0 = (ATA0A # ATA0B # ATA0C)
		43	41 \|\| SELEZIONE ATA 1 -> FE30 - FE37, FE3C, FE3E - FE3F
		44	42 \| ATA1 = (ATA1A # ATA1B # ATA1C)
		45	43 \|\| ENABLE WAIT ATA 0
		46	44 \| WATA0 = ((ATA0A # ATA0B) & WA0')
		47	45 \|\| ENABLE WAIT ATA 1
		48	46 \| WATA1 = ((ATA1A # ATA1B) & WA1')
		49	47 \|\|
		50	48 \|\| --------------------------------------------------------
		51	49 \|\| DMA & FDC
		52	50 \|\| DMA -> FE60 - FE6F
		53	51 \| DMAS = (IO1' & A7' & A6 & A5 & A4')
		54	52 \|\| FDC -> FE58 - FE5F
		55	53 \| FDCS = (IO1' & A7' & A6 & A5' & A4 & A3)
		56	54 \| DMA = DMAS
		57	55 \| FDC = FDCS
		58
		59
		60	58 \|\| IOY -> FE40 - FE4F
		61	59 \| IOY = (IO1' & A7' & A6 & A5' & A4')
		62	60 \|\| RTC -> FE4C - FE4D
		63	61 \| RTCA = (IOY & A3 & A2 & A1')
		64	62 \|\| VDC -> FE4E - FE4F
		65	63 \| VDCA = (IOY & A3 & A2 & A1)
		66	64 \|\| CTC -> FE48 - FE4B
		67	65 \| CTCA = (IOY & A3 & A2')
		68	66 \|\| SELEZIONE RTC, CTC
		69	67 \| IOX = (RTCA # CTCA)
		70	68 \| VDC = VDCA
		71	69 \|\| WAIT CTC
		72	70 \| WCTC = (CTCA & WT')
		73	71 \|\| WAIT VDC
		74	72 \| WVDC = (VDCA & WV')
		75	73 \|\|
		76	74 \|\| --------------------------------------------------------
		77	75 \|\| PIA -> FE28 - FE2B
		78	76 \| PIA = (IO1' & A7' & A6' & A5 & A4' & A3 & A2')
		79	77 \|\|
		80	78 \|\| --------------------------------------------------------
		81	79 \|\| SEGNALE WAIT
		82	80 \| WAIT = (WATA0 # WATA1 # WCTC # WVDC)
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		89	I202 7/24/12 11:17 am (Tuesday)
		90
		91
		92	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0151.PLA)
		93
		94	I289 Simple GAL architecture selected.
		95
		96
		97
		98
		99
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		102	57 A1 A2 A3 A4' A5 A6' A7' IO1'
		103
		104
		105
		106	49 A1 A2 A3 A4 A5 A6' A7' IO1'
		107	50 A3' A4 A5 A6' A7' IO1'
		108
		109
		110
		111	FDC 32 A3 A4 A5' A6 A7' IO1'
		112
		113
		114	17 A2' A3 A4' A5' A6 A7' IO1'
		115
		116	VDC 24 A1 A2 A3 A4' A5' A6 A7' IO1'
		117
		118	PIA 8 A2' A3 A4' A5 A6' A7' IO1'
		119
		120
		121	1 A1 A2 A3 A4' A5 A6' A7' IO1' WA0'
		122
		123	3 A2' A3 A4' A5' A6 A7' IO1' WT'
		124
		125	5 A3' A4 A5 A6' A7' IO1' WA1'
		126
		127
		128
		129	SIGNAL ASSIGNMENT
		130	Rows
		131
		132
		133
		134
		135	2. A1 0 - - - High
		136	3. A2 4 - - - High
		137	4. A3 8 - - - High
		138	5. A4 12 - - - High
		139
		140	7. A6 20 - - - High
		141	8. A7 24 - - - High
		142	9. IO1 28 - - - High
		143	10. - 32 - - -
		144	11. WA0 36 - - - High
		145	13. WA1 38 - - - High (Enable)
		146	14. WV 34 - - - High
		147	15. ATA0 31 56 8 3 Low
		148	16. ATA1 27 48 8 3 Low
		149	17. DMA 23 40 8 1 Low
		150	18. FDC - 32 8 1 Low
		151	19. VDC - 24 8 1 Low
		152	20. IOX 19 16 8 2 Low
		153	21. PIA 15 8 8 1 Low
		154	22. WAIT 11 0 8 6 Low
		155	23. WT 6 - - - High
		156	---- ----
		157	64 18 (28%)
		158
		159
		160	I200 No fatal errors found in source code (device phase).
		161	I201 No warnings.
		162
		163
		164
		165
		166	*
		167	QP24* QF2706* QV1024*
		168
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		170
		171	L0080 01 11 01 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 10 *
		172	L0120 11 11 10 10 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		173	L0160 11 11 11 11 10 11 10 11 01 11 10 11 10 11 10 11 11 11 10 11 *
		174	L0200 11 11 11 11 10 11 01 11 01 11 10 11 10 11 10 11 11 11 11 10 *
		175	L0320 11 11 10 11 01 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		176	L0640 10 11 01 11 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		177	L0680 11 11 10 11 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		178	L0960 01 11 01 11 01 11 10 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		179	L1280 11 11 11 11 01 11 01 11 10 11 01 11 10 11 10 11 11 11 11 11 *
		180	L1600 11 11 11 11 11 11 10 11 01 11 01 11 10 11 10 11 11 11 11 11 *
		181	L1920 10 10 01 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		182	L1960 01 11 01 11 01 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		183	L2000 11 11 11 11 10 11 01 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		184	L2240 10 10 01 11 01 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		185	L2280 01 11 01 11 01 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		186	L2320 11 11 11 11 10 11 10 11 01 11 10 11 10 11 10 11 11 11 11 11 *
		187	L2560 00 00 00 00 00 11 00 00 00 11 00 01 00 11 01 01 00 11 00 01 *
		188	L2600 00 10 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 00 00 00 *
		189	L2640 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 *
		190	L2680 11 11 11 11 11 11 11 11 11 11 11 11 10 *
		191	C5A6A*
		192
		193	I202 7/24/12 11:17 am (Tuesday)
		194	I203 Memory usage 8K
		195	I204 Elapsed time 1 second
		196

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