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  Tue Jul 17 11:00:15 2018                                                                                               Page    1
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          2500 A.D. 65816 Macro Assembler #26960 - Version 5.02g
10
          -----------------------------------------------------
11
 
12
                       Input  Filename : src\F8\reset.asm
13
                       Output Filename : obj\F8\reset.obj
14
                       Listing Has Been Relocated
15
 
16
 
17
 2597                        	.LIST		on
18
 2598
19
 2599  F8FFB1                		.INCLUDE inc\dirp00.inc
20
 2600                        	;----------------------------------------------------------
21
 2601                        	; DIRP00.ASM
22
 2602                        	; PROGETTO: B1601
23
 2603                        	;
24
 2604                        	; Variabili in Direct Page $00
25
 2605                        	;----------------------------------------------------------
26
 2606
27
 2607                        	; sezione COMMON -- questo permette di includere il file in piu' file
28
 2608
29
 2609                        	.LIST on
30
 2610
31
 2611                        	DIRP00:	.SECTION page0, ref_only, common	;Direct-Page 00
32
 2612
33
 2613  000000                		.ABSOLUTE		;; inizia sempre da $00
34
 2614  000000                		.ORG		0x00
35
 2615  000000
36
 2616  000000  0000          	JiffyClk	.DW			; contatore 10ms 32 bit
37
 2617  000002  0000          			.DW
38
 2618  000004                	SysTmr		.DS	SYSTMRCNT	; system timer 0 (10ms)
39
 2619  000008                	SysTMF		.DS	SYSTMRCNT	; flag timer (80 -> start)
40
 2620  00000C  00            	Bnk0Flag	.DB			; <7>: flag test RAM banco 0 ok
41
 2621                        						; <6>: flag warm reset
42
 2622  00000D  00            	RTCFlag		.DB
43
 2623
44
 2624  00000E                	diskstat	.DS	2	; flag device on ata bus #0 & #1
45
 2625                        					; <7>: device ready
46
 2626                        					; <6>: compact flash device (C.F.)
47
 2627                        					; <5>: device identification ok
48
 2628                        					; <4>: MBR loaded
49
 2629                        					; <3>: valid signature in MBR
50
 2630                        					; <2>: first partition found&active
51
 2631                        					; <1>:
52
 2632                        					; <0>: valid partition flag
53
 2633
54
 2634                        					; <7>: device ready
55
 2635                        					; <6>: USB device
56
 2636                        					; <5>: compact flash device (C.F.)
57
 2637                        					; <4>: device identification ok
58
 2638                        					; <3>: MBR loaded
59
 2639                        					; <2>: first partition found&active
60
 2640                        					; <1>: always 1
61
 2641                        					; <0>: valid partition flag
62
 2642  000010
63
  Tue Jul 17 11:00:15 2018                                                                                               Page    2
64
 
65
 
66
 
67
 
68
 2643
69
 2644          00000E        	atadev		.EQU	diskstat
70
 2645
71
 2646  000010                	usbdev		.DS	2	; flag flash disk on usb bus #0
72
 2647                        					; <7>: device plugged and ready
73
 2648                        					; <6>: always 1
74
 2649                        					; <5>: device identification ok
75
 2650                        					; <4>: MBR loaded
76
 2651                        					; <3>: valid signature in MBR
77
 2652                        					; <2>: first partition found&active
78
 2653                        					; <1>:
79
 2654                        					; <0>: valid partition flag
80
 2655
81
 2656  000012                	diskmax		.DS	16	; disk max. sector's
82
 2657          000012        	atasec		.EQU	diskmax
83
 2658          00001A        	usbsec		.EQU	diskmax+8
84
 2659
85
 2660
86
 2661  000022                	atambr		.DS	8	; data for first partition found in mbr
87
 2662                        					; first 3 bytes for start sector of partition
88
 2663                        					; last byte for partition type
89
 2664  00002A                	usbmbr		.DS	8
90
 2665
91
 2666  000032                	ataprt		.DS	8	; total sec's of first partition
92
 2667  00003A                	usbprt		.DS	8	; total sec's of first partition
93
 2668
94
 2669
95
 2670  000042  00            	usb0ch		.DB	; usb0 (ch375/ch376) flag
96
 2671                        				; <7>: module on
97
 2672                        				; <6>: ch376 flag
98
 2673                        				; <5:0>: chip version
99
 2674
100
 2675  000043  00            	usb0st		.DB	; usb0 status
101
 2676                        				; <7>: usb0 host mode ok
102
 2677                        				; <6>: flash disk attached flag
103
 2678                        				; <5>: usb device attached
104
 2679
105
 2680  000044  00            	fdcdrv		.DB		; phisycal drive status (drive #0)
106
 2681                        					; <7>: disk format established in bit 0&1
107
 2682                        					; <6>: double step seek done
108
 2683                        					; <5>: trust format bit's (set after ok r/w)
109
 2684                        					; <4>: write protect bit (if disk in drive)
110
 2685                        					; <3>: don't care
111
 2686                        					; <2>: don't care
112
 2687                        					; <1>: HD disk if set else DD disk
113
 2688                        					; <0>: CBM format if set else IBM format
114
 2689
115
 2690  000045  00            	vdrive		.DB		; virtual drive status (ram disk, drive #1)
116
 2691                        					; <7>: disk format established in bit 0&1
117
 2692                        					; <6>: change disk simulation (after format)
118
 2693                        					; <5>: don't care
119
 2694                        					; <4>: write protect bit (under sw control)
120
 2695                        					; <3>: don't care
121
 2696                        					; <2>: don't care
122
 2697                        					; <1>: HD disk if set else DD disk
123
 2698                        					; <0>: CBM format if set else IBM format
124
 2699
125
  Tue Jul 17 11:00:15 2018                                                                                               Page    3
126
 
127
 
128
 
129
 
130
 2700  000046  00            	fdcctl		.DB		; fdc controller status
131
 2701                        					; <7>: drive is attached
132
 2702                        					; <6>: drive need recalibration (restore)
133
 2703                        					; <5>: FDC controller ok
134
 2704                        					; <4>: motor on
135
 2705                        					; <3>: dma is active
136
 2706                        					; <2>: dma chip ok (post routine)
137
 2707                        					; <1>: clock rate (1=HD,0=DD)
138
 2708                        					; <0>: disk ready
139
 2709
140
 2710  000047  00            	fdctrk		.DB		; fd: current seek track
141
 2711  000048  00            	fdcerr		.DB		; fd: last error code
142
 2712  000049  00            	ataerr		.DB		; ata: last error code
143
 2713  00004A  00            	ataxer		.DB		; ata: last extended error code
144
 2714
145
 2715  00004B  00            	CtrlBrk		.DB		; flag CTRL+BREAK (NMI)
146
 2716
147
 2717  00004C  0000          	MemTop		.DW		; top memoria RAM
148
 2718  00004E  00            			.DB		; banco top mem
149
 2719
150
 2720  00004F  00            	DflTxtIn	.DB		; device di default text input
151
 2721  000050  00            	DflTxtOut	.DB		; device di default text output
152
 2722
153
 2723  000051                	COPPtr		LP		; long pointer for COP decoding
154
 2724  000054  00            	COPIdx		.DB		; COP signature/index
155
 2725
156
 2726  000055  00            	BiosEnt		.DB		; flag accesso a bios setup
157
 2727
158
 2728                        	; variabili utilizzate da ACIA
159
 2729  000056                	spwrk		.DS	$30
160
 2730
161
 2731                        	; bios mem
162
 2732  000086  0000          	nsize		.DW	; dimensione blocco da allocare
163
 2733                        	;bsize		.DW	; dimensione vera blocco free
164
 2734  000088  0000          	splitsz		.DW	; dimensione blocco splittato
165
 2735  00008A  0000          	bfree		.DW	; puntatore blocco free
166
 2736  00008C  0000          	hdrptr		.DW	; puntatore header heap
167
 2737
168
 2738  00008E  0000          	pbrklv		.DW	; current break level of current process
169
 2739  000090  0000          	pbrkmin		.DW	; minimum breal level of current process
170
 2740  000092  0000          	pbrkmax		.DW	; maximum breal level of current process
171
 2741  000094
172
 2742                        	; bios temp. work area
173
 2743  000094                	bwrktmp		.DS	$28
174
 2744
175
 2745  0000BC  00            	coptmp		.DB	; temp. used while cop
176
 2746
177
 2747  0000BD  00            	tstser		.DB	; check ser/usb test board post
178
 2748                        				; <7>: VIA2 ok
179
 2749                        				; <6>: PICRAM ok
180
 2750                        				; <1>: UART 16C550 ok
181
 2751                        				; <0>: R65C51 ok
182
 2752
183
 2753
184
 2754                        	;crc16		.DW
185
 2755
186
 2756  0000BD                		.RELATIVE
187
  Tue Jul 17 11:00:15 2018                                                                                               Page    4
188
 
189
 
190
 
191
 
192
 2757
193
 2758                        		.ENDS
194
 2759
195
 2760          [01]          	.IFDEF		_ACIA_INC_
196
 2761  F8FFB1                		.INCLUDE INC\SP.INC
197
 2762                        	;;
198
 2763                        	;; Copyright (c) 2016 Marco Granati <mg@unet.bz>
199
 2764                        	;;
200
 2765                        	;; Permission to use, copy, modify, and distribute this software for any
201
 2766                        	;; purpose with or without fee is hereby granted, provided that the above
202
 2767                        	;; copyright notice and this permission notice appear in all copies.
203
 2768                        	;;
204
 2769                        	;; THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
205
 2770                        	;; WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
206
 2771                        	;; MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
207
 2772                        	;; ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
208
 2773                        	;; WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
209
 2774                        	;; ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
210
 2775                        	;; OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
211
 2776                        	;;
212
 2777
213
 2778                        	;; name: sp.inc
214
 2779                        	;; rev.: 2016/07/28
215
 2780                        	;; bios C816 version v1.0
216
 2781
217
 2782                        	.LIST on
218
 2783
219
 2784          000001        	SOH		.EQU	$01
220
 2785          000002        	STX		.EQU	$02
221
 2786          000003        	ETX		.EQU	$03
222
 2787          000004        	EOT		.EQU	$04
223
 2788          000005        	ENQ		.EQU	$05
224
 2789          000006        	ACK		.EQU	$06
225
 2790          000010        	DLE		.EQU	$10
226
 2791          000016        	SYN		.EQU	$16
227
 2792
228
 2793          002000        	SOBUFSIZ	.EQU	$2000	; dimensione coda TX1/TX2 ACIA (8K)
229
 2794                        	;SOBUFSIZ	.EQU	$0100	; dimensione coda TX1/TX2 ACIA (8K)
230
 2795          004000        	SIBUFSIZ	.EQU	$4000	; dimensione coda RX1/RX2 ACIA (16K)
231
 2796                        	;SIBUFSIZ	.EQU	$0100	; dimensione coda RX1/RX2 ACIA (16K)
232
 2797
233
 2798          000080        	NGUARD1		.EQU	$80	; numero bytes di guardia buffer RX XON/XOFF
234
 2799          000040        	NGUARD2		.EQU	$40	; numero bytes di guardia buffer RX handshake
235
 2800                        	;NGUARD1		.EQU	$40	; numero bytes di guardia buffer RX XON/XOFF
236
 2801                        	;NGUARD2		.EQU	$20	; numero bytes di guardia buffer RX handshake
237
 2802          001000        	NFREE1		.EQU	$1000	; minimo posto in coda RX per cancellare pausa remota
238
 2803          000800        	NFREE2		.EQU	$0800
239
 2804                        	;NGUARD3		.EQU	$F0
240
 2805                        	;NGUARD4		.EQU	$F8
241
 2806
242
 2807                        	;---------------------------------------------------------------------------
243
 2808                        	; direct page var's for serial ports handling
244
 2809                        	;---------------------------------------------------------------------------
245
 2810
246
 2811                        	DPSP:	.SECTION page0, common, ref_only, offset spwrk	;ACIA D.P.
247
 2812
248
 2813  000056                	_DPSP_START	.DS	0
249
  Tue Jul 17 11:00:15 2018                                                                                               Page    5
250
 
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252
 
253
 
254
 2814
255
 2815                        	; WARNING: not change order and type of the following variables
256
 2816
257
 2817                        	; acia 1 var's
258
 2818  000056  00            	splin		.DB		; interrupt status register
259
 2819  000057  00            	spcsr		.DB		; control status register
260
 2820  000058  00            	spfr		.DB		; format register
261
 2821  000059  00            	spout		.DB		; XON/XOFF send flag
262
 2822
263
 2823                        	; acia 2 var's
264
 2824  00005A  00            	splin2		.DB		; interrupt status register
265
 2825  00005B  00            	spcsr2		.DB		; control status register
266
 2826  00005C  00            	spfr2		.DB		; format register
267
 2827  00005D  00            	spout2		.DB		; XON/XOFF send flag
268
 2828
269
 2829                        	; serial port's mode & status
270
 2830  00005E  00            	spmode		.DB		; <7>: 0=no handshake, 1=handshake
271
 2831                        					; <6>: 0=software/1=hardware handshake
272
 2832                        					; <5>: not used
273
 2833                        					; <4>: baud rate: 0=19200, 1=38400
274
 2834                        					; <3>: 0=odd parity, 1=even parity
275
 2835                        					; <2>: 0=no parity, 1=parity as specified
276
 2836                        					;      by bit <3>
277
 2837                        					; <1>: interface type: 0=RS232, 1=RS485
278
 2838                        					; <0>: RS232: uplink flow control (RTS/DCD)
279
 2839                        					;      RS485: 120 ohm termination on
280
 2840                        					; if bit 7=1 and bit 1=1, bit 6 is forced to 0
281
 2841  00005F
282
 2842  00005F  00            	spstat		.DB		; serial port status
283
 2843                        					; <7>: rx error (data discarded)
284
 2844                        					; <6>: rx buffer overflow
285
 2845                        					; <5>: remote disconnession (DSR line = 1)
286
 2846                        					; <4>: output buffer overflow
287
 2847                        					; <3>: not used
288
 2848                        					; <2>: framing error
289
 2849                        					; <1>: parity error
290
 2850                        					; <0>: overrun error
291
 2851
292
 2852  000060  00            	sppause		.DB		; local/remote pause flag's
293
 2853                        					; <7>: remote pause (sent an XON or set RTS=1)
294
 2854                        					; <6>: local pause (received an XON or CTS=1)
295
 2855
296
 2856  000061  00            	sptmp		.DB		; temp. byte used while get data
297
 2857
298
 2858                        	; serial port's mode & status
299
 2859  000062  00            	spmode2		.DB		; <7>: 0=no handshake, 1=handshake
300
 2860                        					; <6>: 0=software/1=hardware handshake
301
 2861                        					; <5>: not used
302
 2862                        					; <4>: baud rate: 0=19200, 1=38400
303
 2863                        					; <3>: 0=odd parity, 1=even parity
304
 2864                        					; <2>: 0=no parity, 1=parity as specified
305
 2865                        					;      by bit <3>
306
 2866                        					; <1>: interface type: 0=RS232, 1=RS485
307
 2867                        					; <0>: RS232: uplink flow control (RTS/DCD)
308
 2868                        					;      RS485: 120 ohm termination on
309
 2869                        					; if bit 7=1 and bit 1=1, bit 6 is forced to 0
310
 2870  000063
311
  Tue Jul 17 11:00:15 2018                                                                                               Page    6
312
 
313
 
314
 
315
 
316
 2871  000063  00            	spstat2		.DB		; serial port status
317
 2872                        					; <7>: rx error (data discarded)
318
 2873                        					; <6>: rx buffer overflow
319
 2874                        					; <5>: remote disconnession (DSR line = 1)
320
 2875                        					; <4>: output buffer overflow
321
 2876                        					; <3>: not used
322
 2877                        					; <2>: framing error
323
 2878                        					; <1>: parity error
324
 2879                        					; <0>: overrun error
325
 2880
326
 2881  000064  00            	sppause2	.DB		; local/remote pause flag's
327
 2882                        					; <7>: remote pause (sent XOFF/XON or RTS=1/0)
328
 2883                        					; <6>: local pause (rx XOFF/XON or CTS=0/1)
329
 2884
330
 2885  000065  00            	sppost		.DB		; after POST must hold $C0
331
 2886
332
 2887  000066  0000          	ibuftail	.DW		; pointer to tail of input buffer
333
 2888  000068  0000          	ibufhead	.DW		; pointer to head of input buffer
334
 2889  00006A  0000          	ibuftail2	.DW
335
 2890  00006C  0000          	ibufhead2	.DW
336
 2891
337
 2892  00006E  0000          	obuftail	.DW		; pointer to tail of output buffer
338
 2893  000070  0000          	obufhead	.DW		; pointer to head of output buffer
339
 2894  000072  0000          	obuftail2	.DW
340
 2895  000074  0000          	obufhead2	.DW
341
 2896
342
 2897  000076  0000          	ibufcnt		.DW		; count of bytes in input buffer
343
 2898  000078  0000          	obufcnt		.DW		; count of bytes in output buffer
344
 2899  00007A  0000          	ibufcnt2	.DW
345
 2900  00007C  0000          	obufcnt2	.DW
346
 2901
347
 2902  00007E  0000          	icntmin		.DW		; min. count for clear remote pause
348
 2903  000080  0000          	icntmax		.DW		; max. count for set remote pause
349
 2904  000082  0000          	icntmin2	.DW
350
 2905  000084  0000          	icntmax2	.DW
351
 2906
352
 2907  000086                	_DPSP_END	.DS	0
353
 2908          000030        	DPSPSIZ		.EQU	(_DPSP_END - _DPSP_START)
354
 2909
355
 2910
356
 2911                        		.ENDS
357
 2912
358
 2913          00005F        	ACIArxe_1	.EQU	spstat
359
 2914          000063        	ACIArxe_2	.EQU	spstat2
360
 2915          00005E        	ACIAhsk_1	.EQU	spmode
361
 2916          000062        	ACIAhsk_2	.EQU	spmode2
362
 2917          000060        	ACIAPause_1	.EQU	sppause
363
 2918          000064        	ACIAPause_2	.EQU	sppause2
364
 2919          000057        	ACIAcsr_1	.EQU	spcsr
365
 2920          00005B        	ACIAcsr_2	.EQU	spcsr2
366
 2921          000058        	ACIAfr_1	.EQU	spfr
367
 2922          00005C        	ACIAfr_2	.EQU	spfr2
368
 2923          000060        	ACIAOut_1	.EQU	sppause
369
 2924          000064        	ACIAOut_2	.EQU	sppause2
370
 2925          000076        	ACIAICnt_1	.EQU	ibufcnt
371
 2926          00007A        	ACIAICnt_2	.EQU	ibufcnt2
372
 2927          000068        	ACIAIHead_1	.EQU	ibufhead
373
  Tue Jul 17 11:00:15 2018                                                                                               Page    7
374
 
375
 
376
 
377
 
378
 2928          00006C        	ACIAIHead_2	.EQU	ibufhead2
379
 2929          000066        	ACIAITail_1	.EQU	ibuftail
380
 2930          00006A        	ACIAITail_2	.EQU	ibuftail2
381
 2931          000078        	ACIAOCnt_1	.EQU	obufcnt
382
 2932          00007C        	ACIAOCnt_2	.EQU	obufcnt2
383
 2933          000070        	ACIAOHead_1	.EQU	obufhead
384
 2934          000074        	ACIAOHead_2	.EQU	obufhead2
385
 2935          00006E        	ACIAOTail_1	.EQU	obuftail
386
 2936          000072        	ACIAOTail_2	.EQU	obuftail2
387
 2937
388
 2938          002000        	ACIAOBUFLEN	.EQU	SOBUFSIZ
389
 2939          004000        	ACIAIBUFLEN	.EQU	SIBUFSIZ
390
 2940          050000        	ACIAOUTBUF1	.EQU	SPOUTBUFF
391
 2941          052000        	ACIAOUTBUF2	.EQU	SPOUTBUFF2
392
 2942          054000        	ACIAINBUF1	.EQU	SPINBUFF
393
 2943          058000        	ACIAINBUF2	.EQU	SPINBUFF2
394
 2944
395
 2945          000061        	ACIATmp		.EQU	sptmp
396
 2946
397
 2964                        	.LIST on
398
 2965
399
 2966          000060        	KBDBUFLEN	.EQU	96		; dimensione buffer di tastiera
400
 2967
401
 2968                        	DIRP01:	.SECTION page0, ref_only, common	;Direct-Page 01
402
 2969
403
 2970  000000                		.ABSOLUTE		;; inizia sempre da $00
404
 2971  000000                		.ORG		0x00
405
 2972
406
 2973  000000
407
 2974  000000                	KbdBuf		.DS	KBDBUFLEN	; buffer della tastiera
408
 2975  000060  00            	KbdITail	.DB			; coda buffer tastiera
409
 2976  000061  00            	KbdIHead	.DB			; testa buffer tastiera
410
 2977  000062  00            	KbdCnt		.DB			; numero bytes nel buffer
411
 2978  000063  00            	KbdShift	.DB
412
 2979  000064  00            	KbdFlag		.DB
413
 2980  000065  00            	KbdToggle	.DB
414
 2981  000066  00            	KbdSt		.DB			; status tastiera dopo reset
415
 2982  000067  00            	PS2Ctl		.DB			; flag controller PS2 keyboard
416
 2983
417
 2984  000068  00            	LCDFlag		.DB
418
 2985  000069  00            	LCDTmp		.DB
419
 2986  00006A  0000          	LCDVal		.DW
420
 2987
421
 2988  00006C  00            	VBBFlag		.DB		; flag video board
422
 2989  00006D  00            	VBBRam		.DB		; flag video RAM
423
 2990
424
 2991  00006E  00            	ScnLinTmp	.DB
425
 2992  00006F  00            	ScnChBase	.DB		; base video ram VDC
426
 2993  000070  00            	ScnAttBase	.DB		; base ram attributi VDC
427
 2994  000071  00            	ScnCursMode	.DB		; VDC cursore default
428
 2995  000072  00            	ScnSaveAttr	.DB
429
 2996  000073  00            	ScnInsert	.DB
430
 2997  000074  00            	ScnAutoIns	.DB		; bit 7 -> autoins - bit 6 -> modo input
431
 2998  000075  00            	ScnScroll	.DB
432
 2999  000076  00            	ScnMaxRow	.DB		; max. righe finestra (-1)
433
 3000  000077  00            	ScnMaxCols	.DB		; max. colonne finestra (-1)
434
 3001
435
  Tue Jul 17 11:00:15 2018                                                                                               Page    8
436
 
437
 
438
 
439
 
440
 3002  000078                	ScnMapTabs1	.DS	10
441
 3003  000082                	ScnMapTabs2	.DS	4
442
 3004  000086
443
 3005  000086  0000          	ScnPtr		.DW		; puntatore video ram linea corrente
444
 3006  000088  00            			.DB
445
 3007
446
 3008  000089  00            	ScnFiltLen	.DB		; lunghezza set caratteri filtro
447
 3009
448
 3010  00008A  0000          	ScnAtPtr	.DW		; puntatore attributi ram linea corrente
449
 3011  00008C  00            			.DB
450
 3012
451
 3013  00008D  00            	ScnTmpx		.DB		; temporaneo: durante put char
452
 3014  00008E
453
 3015  00008E  00            	ScnTop		.DB		; riga superiore finestra
454
 3016  00008F  00            	ScnLeft		.DB		; colonna sinistra finestra
455
 3017  000090  00            	ScnBottom	.DB		; riga inferiore finestra
456
 3018  000091  00            	ScnRight	.DB		; colonna destra finestra
457
 3019  000092  00            	ScnAttr		.DB		; attributo default
458
 3020  000093  00            	ScnAttr2	.DB		; attributo alternativo
459
 3021  000094  00            	ScnRow		.DB		; riga cursore
460
 3022  000095  00            	ScnCol		.DB		; colonna cursore
461
 3023  000096  00            	ScnRowStart	.DB		; riga di start input
462
 3024  000097  00            	ScnInput	.DB		; riga di fine input
463
 3025  000098  00            	ScnColStart	.DB		; colonna di start input
464
 3026  000099  00            	ScnSaveX	.DB
465
 3027  00009A  00            	ScnSaveY	.DB
466
 3028  00009B  00            	ScnTmpL		.DB
467
 3029  00009C  00            	ScnTmpH		.DB
468
 3030  00009D  00            	ScnSaveRow	.DB
469
 3031  00009E  00            	ScnSaveCol	.DB
470
 3032  00009F  00            	ScnCurChr	.DB
471
 3033  0000A0  00            	ScnLstChr	.DB
472
 3034  0000A1  00            	ScnCR		.DB
473
 3035  0000A2  0000          	ScnPrm		.DW		; puntatore long utilizzato da print imm
474
 3036  0000A4  00            			.DB		; banco puntatore ScnPrm
475
 3037  0000A5  00            	ScnMode		.DB		; flag modo schermo
476
 3038
477
 3039  0000A6                	ScnPtr1		LP
478
 3040
479
 3041  0000A9  00            	ScnDefCol	.DB		; default foreground color
480
 3042
481
 3043  0000AA                	ScnPtr2		LP
482
 3044
483
 3045  0000AD  00            	ScnDefBkgCol	.DB		; default background color
484
 3046  0000AE  00            	ScnInpRow	.DB		; modo input line: riga start input
485
 3047  0000AF  00            	ScnInpCol	.DB		; modo input line: colonna start input
486
 3048  0000B0  00            	ScnLstRow	.DB		; modo input line: riga stop input
487
 3049  0000B1  00            	ScnLstCol	.DB		; modo input line: colonna stop input
488
 3050  0000B2  00            	ScnFlag		.DB		; Bit 7: input line - Bit 6: input riga unica
489
 3051  0000B3  00            	ScnMask		.DB		; flag tasti funzione editor di linea
490
 3052  0000B4  00            	ScnFilt		.DB		; filtro tasti editor di linea
491
 3053  0000B5  00            	ScnCntrl	.DB		; flag ASCII/CONTROL
492
 3054                        	;DflTxtIn	.DB		; device di default text input
493
 3055                        	;DflTxtOut	.DB		; device di default text output
494
 3056  0000B6
495
 3057          000047        	SCNCLRLEN	.EQU	($ - ScnLinTmp - 1)
496
 3058
497
  Tue Jul 17 11:00:15 2018                                                                                               Page    9
498
 
499
 
500
 
501
 
502
 3059                        	;SCNCLRLEN	.EQU	(DflTxtOut - ScnLinTmp)
503
 3060
504
 3061                        	; variabili monitor
505
 3062  0000B6  00            	SMAddrL		.DB	; address low/high
506
 3063  0000B7  00            	SMAddrH		.DB
507
 3064  0000B8  00            	SMAddrK		.DB	; address bank
508
 3065  0000B9  00            	SMFlag32	.DB	; flag parametro 32 bit
509
 3066  0000BA  00            	SMTmpL		.DB	; temp. low/high
510
 3067  0000BB  00            	SMTmpH		.DB
511
 3068  0000BC  00            	SMTmpK		.DB	; temp. bank
512
 3069  0000BD  00            	SMTmpKK		.DB	; high byte param. 32 bit
513
 3070  0000BE  00            	SMSizeL		.DB	; size low/high
514
 3071  0000BF  00            	SMSizeH		.DB
515
 3072  0000C0  00            	SMSizeK		.DB	; size bank
516
 3073  0000C1  00            	SMXAddrL	.DB	; address low/high XM
517
 3074  0000C2  00            	SMXAddrH	.DB
518
 3075  0000C3  00            	SMXAddrK	.DB	; address bank XM
519
 3076  0000C4  00            	SMbndx		.DB	; indice input buffer
520
 3077  0000C5  00            	SMnprm		.DB	; numero parametri riga di comando
521
 3078  0000C6  00            	SMdumb		.DB
522
 3079  0000C7  00            	SMkr		.DB
523
 3080  0000C8  0000          	SMpc		.DW
524
 3081  0000CA  00            	SMsr		.DB
525
 3082  0000CB  00            	SMbr		.DB
526
 3083  0000CC  0000          	SMdp		.DW
527
 3084  0000CE  0000          	SMac		.DW
528
 3085  0000D0  0000          	SMxr		.DW
529
 3086  0000D2  0000          	SMyr		.DW
530
 3087  0000D4  0000          	SMsp		.DW
531
 3088
532
 3089  0000D6  00            	SMAuxL		.DB
533
 3090  0000D7  00            	SMAuxH		.DB
534
 3091
535
 3092  0000D8  00            	asmlong		.DB	; flag for CPU in 16 mode
536
 3093                        				; <7> -> A/M in 16 bit mode
537
 3094                        				; <6> -> X/Y in 16 bit mode
538
 3095  0000D9  00            	asmcpu		.DB	; <7> -> 8 bit family
539
 3096                        				; <6> -> 65C02 cmos version
540
 3097
541
 3098  0000DA  00            	SMctx		.DB	; context (if = $00 no quit command)
542
 3099  0000DB                	SMrsm		LP	; long pointer to resume caller context
543
 3100
544
 3101  0000DE  00            	rtcadr		.DB	; rtc internal ram address
545
 3102  0000DF  00            	rtcbnk		.DB	; RTC internal bank ram
546
 3103  0000E0  00            	cmdlin		.DB	;
547
 3104  0000E1  00            	SMesc		.DB
548
 3105
549
 3106  0000E2                	SMXTmp:		.DS	26	; 26 bytes tmp
550
 3107
551
 3108          0000E2        	SMTmp2		.EQU	SMXTmp
552
 3109          0000E4        	SMTmp3		.EQU	SMXTmp+2
553
 3110          0000E6        	SMdwTmp1	.EQU	SMXTmp+4
554
 3111          0000EA        	SMdwTmp2	.EQU	SMXTmp+8
555
 3112          0000EE        	SMFsrc		.EQU	SMXTmp+12	; source bank for flash update
556
 3113          0000EF        	SMFflag		.EQU	SMXTmp+13	; flag file for flash update
557
 3114          0000F0        	SMXPos2		.EQU	SMXTmp+14
558
 3115          0000F1        	SMYPos2		.EQU	SMXTmp+15
559
  Tue Jul 17 11:00:15 2018                                                                                               Page   10
560
 
561
 
562
 
563
 
564
 3116          0000F2        	SMXPos3		.EQU	SMXTmp+16
565
 3117          0000F3        	SMYPos3		.EQU	SMXTmp+17
566
 3118                        	;SMAuxL		.EQU	SMXTmp+18
567
 3119                        	;SMAuxH		.EQU	SMXTmp+19
568
 3120          0000F6        	SMXPos		.EQU	SMXTmp+20
569
 3121          0000F7        	SMYPos		.EQU	SMXTmp+21
570
 3122          0000F8        	SMdwTmp3	.EQU	SMXTmp+22
571
 3123
572
 3124          0000E2        	atcmd		.EQU	SMXTmp		; save @ command
573
 3125          0000E3        	atnum		.EQU	SMXTmp+1	; @ command index
574
 3126          0000E4        	atflag		.EQU	SMXTmp+2	; @ L,S,V,R,W start address flag
575
 3127          0000E5        	atbnk		.EQU	SMXTmp+3	; @ L,S,V,R,W bank
576
 3128          0000E6        	atstr		.EQU	SMXTmp+4	; @ command string start (word)
577
 3129          0000E8        	atstart		.EQU	SMXTmp+6	; @ L,S,V,R,W start address (word)
578
 3130          0000EA        	atend		.EQU	SMXTmp+8	; @ S,W end address (word)
579
 3131          0000EC        	atbuf		.EQU	SMXTmp+10	; @ local buffer pointer (word)
580
 3132          0000EE        	atipb		.EQU	SMXTmp+12	; @ bank of input buffer
581
 3133          0000EF        	atdir		.EQU	SMXTmp+13	; @ load dir flag
582
 3134          0000F0        	atptr		.EQU	SMXTmp+14	; @ load dir pointer (word)
583
 3135          0000F2        	atsiz		.EQU	SMXTmp+16	; @ buffer size (word)
584
 3136          0000F5        	atlp		.EQU	SMXTmp+19	; @ long pointer
585
 3137          0000F8        	atsa		.EQU	SMXTmp+22	; @ sa
586
 3138
587
 3139          0000E2        	btmpx		.EQU	SMXTmp		; asc2bin conversion
588
 3140          0000E3        	brtcsec		.EQU	SMXTmp+1
589
 3141          0000E4        	brtcmin		.EQU	SMXTmp+2
590
 3142          0000E5        	brtchour	.EQU	SMXTmp+3
591
 3143          0000E6        	brtcday		.EQU	SMXTmp+4
592
 3144          0000E7        	brtcmonth	.EQU	SMXTmp+5
593
 3145          0000E8        	brtcyear	.EQU	SMXTmp+6
594
 3146          0000E9        	brtcct		.EQU	SMXTmp+7
595
 3147
596
 3148
597
 3149  0000FC                		.RELATIVE
598
 3150
599
 3151                        		.ENDS
600
 3152
601
 3176                        	.LIST on
602
 3177
603
 3178          05C000        	SOBUFADDR3	.EQU	SPOUTBUFF3
604
 3179          05D000        	SIBUFADDR3	.EQU	SPINBUFF3
605
 3180          001000        	SOBUFSIZ3	.EQU	$1000
606
 3181          001000        	SIBUFSIZ3	.EQU	$1000
607
 3182
608
 3183          060000        	SOBUFADDR4	.EQU	SPOUTBUFF4
609
 3184          068000        	SIBUFADDR4	.EQU	SPINBUFF4
610
 3185                        	;SOBUFSIZ4	.EQU	$1000
611
 3186                        	;SIBUFSIZ4	.EQU	$1000
612
 3187          008000        	SOBUFSIZ4	.EQU	$8000
613
 3188          008000        	SIBUFSIZ4	.EQU	$8000
614
 3189
615
 3190          000200        	NGUARD31	.EQU	$0200	; numero bytes di guardia buffer RX XON/XOFF
616
 3191          000100        	NGUARD32	.EQU	$0100	; numero bytes di guardia buffer RX handshake
617
 3192          000800        	NFREE31		.EQU	$0800	; minimo posto in coda RX per cancellare pausa remota
618
 3193          000400        	NFREE32		.EQU	$0400
619
 3194
620
 3195                        	;---------------------------------------------------------------------------
621
  Tue Jul 17 11:00:15 2018                                                                                               Page   11
622
 
623
 
624
 
625
 
626
 3196                        	; direct page var's for test serial ports/usb handling
627
 3197                        	;---------------------------------------------------------------------------
628
 3198
629
 3199                        	DPSP2:	.SECTION page0, common, ref_only	;UART D.P.
630
 3200
631
 3201  000000  00            	usbslv		.DB	; <7>: plugged-in, <6>: plug-in pending
632
 3202  000001  00            	usbum		.DB	; <7>: pending message, <6>: connected
633
 3203  000002  00            	usbcnt1		.DB	; timeout UM245 plug-in detection
634
 3204  000003                	usbbuf		.DS	8
635
 3205  00000B  00            	usbtim		.DB
636
 3206  00000C  00            	usbcnt		.DB
637
 3207  00000D  00            	usbmst		.DB
638
 3208  00000E  0000          	usbsiz		.DW
639
 3209  000010                	usbptr		LP
640
 3210  000013  00            	usbtmp		.DB
641
 3211  000014  00            	usbcmp		.DB
642
 3212
643
 3213                        	; serial port 65C51
644
 3214  000015  00            	spmode3		.DB	; <7>: 0=no handshake, 1=handshake
645
 3215                        				; <6>: 0=software/1=hardware handshake
646
 3216                        				; <5>: not used
647
 3217                        				; <4>: not used
648
 3218                        				; <3>: 0=odd parity, 1=even parity
649
 3219                        				; <2>: 0=no parity, 1=parity as specified
650
 3220                        				;      by bit <3>
651
 3221                        				; <1:0> : baud rate
652
 3222                        				;	00 =  19200
653
 3223                        				;	01 =  38400
654
 3224                        				;	10 =  57600
655
 3225                        				;	11 = 115200
656
 3226  000016
657
 3227  000016  00            	splin3		.DB	; <7>: /CTS line level
658
 3228                        				; <6>: /DSR line status
659
 3229  000017
660
 3230  000017  00            	sppause3	.DB
661
 3231  000018  00            	spout3		.DB
662
 3232  000019  00            	spstat3		.DB	; staus
663
 3233                        				; <7>: rx error (data discarded)
664
 3234                        				; <6>: rx buffer overflow
665
 3235                        				; <5>: remote disconnession (/DSR line = 1)
666
 3236                        				; <4>: output buffer overflow
667
 3237                        				; <3>: not used
668
 3238                        				; <2>: framing error
669
 3239                        				; <1>: parity error
670
 3240                        				; <0>: overrun error
671
 3241
672
 3242  00001A  00            	sptmp3		.DB
673
 3243
674
 3244  00001B  0000          	ibuftail3	.DW
675
 3245  00001D  0000          	ibufhead3	.DW
676
 3246  00001F  0000          	obuftail3	.DW
677
 3247  000021  0000          	obufhead3	.DW
678
 3248  000023  0000          	ibufcnt3	.DW
679
 3249  000025  0000          	obufcnt3	.DW
680
 3250  000027  0000          	icntmin3	.DW
681
 3251  000029  0000          	icntmax3	.DW
682
 3252
683
  Tue Jul 17 11:00:15 2018                                                                                               Page   12
684
 
685
 
686
 
687
 
688
 3253                        	; serial port 16C550
689
 3254  00002B  00            	spmode4		.DB	; <7>: 0=no handshake, 1=handshake
690
 3255                        				; <6>: 0=software/1=hardware handshake
691
 3256                        				; <5>: not used
692
 3257                        				; <4>: not used
693
 3258                        				; <3>: 0=odd parity, 1=even parity
694
 3259                        				; <2>: 0=no parity, 1=parity as specified
695
 3260                        				;      by bit <3>
696
 3261                        				; <1:0> : baud rate
697
 3262                        				;	00 =  19200
698
 3263                        				;	01 =  38400
699
 3264                        				;	10 =  57600
700
 3265                        				;	11 = 115200
701
 3266  00002C
702
 3267  00002C  00            	splin4		.DB	; <7>: /DSR line level
703
 3268                        				; <6>: /CTS line status
704
 3269  00002D
705
 3270  00002D  00            	sppause4	.DB
706
 3271  00002E  00            	spout4		.DB
707
 3272  00002F  00            	spstat4		.DB	; staus
708
 3273                        				; <7>: rx error (data discarded)
709
 3274                        				; <6>: rx buffer overflow
710
 3275                        				; <5>: remote disconnession (/DSR line = 1)
711
 3276                        				; <4>: output buffer overflow
712
 3277                        				; <3>: break
713
 3278                        				; <2>: framing error
714
 3279                        				; <1>: parity error
715
 3280                        				; <0>: overrun error
716
 3281
717
 3282  000030  00            	sptmp4		.DB
718
 3283
719
 3284  000031  0000          	ibuftail4	.DW
720
 3285  000033  0000          	ibufhead4	.DW
721
 3286  000035  0000          	obuftail4	.DW
722
 3287  000037  0000          	obufhead4	.DW
723
 3288  000039  0000          	ibufcnt4	.DW
724
 3289  00003B  0000          	obufcnt4	.DW
725
 3290  00003D  0000          	icntmin4	.DW
726
 3291  00003F  0000          	icntmax4	.DW
727
 3292
728
 3293  000041  00            	spcnt4		.DB
729
 3294  000042  00            	uartlsr		.DB
730
 3295  000043  00            	uartiir		.DB
731
 3296
732
 3297  000044                	usb0name	.DS	36
733
 3298
734
 3299                        		.ENDS
735
 3300
736
 3306                        	.LIST on
737
 3307  F8FFB1
738
 3308                        		.CODEF8
739
 3309                        		.GLOBAL SysStart, LF8Tst
740
 3310                        		.EXTERN VDCSetup, VDCREG16, fdinit, vdinit
741
 3311                        		.EXTERN initata, showusb0, shusb0fat, _ScnInit
742
 3312
743
 3313                        		.EXTERN _KbdCnt, _KbdToggle, _KbdSt, _PS2Ctl, _KbdITail
744
 3314                        		.EXTERN _KbdIHead, _KbdShift, _KbdFlag, _LCDFlag
745
  Tue Jul 17 11:00:15 2018                                                                                               Page   13
746
 
747
 
748
 
749
 
750
 3315
751
 3316                        		.EXTERN LCDSetup, GetBufKey
752
 3317                        		.EXTERN TORAM, intsr
753
 3318
754
 3319                        	; valore contatore T1 VIA 0 per IRQ con periodo di TJIFFY ms
755
 3320          009C3E        	VIA0T1CNT	.SET	((TJIFFY * 1000 * PHI2) - 2)
756
 3321
757
 3322          00EA5E        	VIA2T1CNT	.SET	((15000 * PHI2) - 2)	; 15ms timeout
758
 3323
759
 3324                        	; valore contatore T1 VIA 1 per PBt -> 1KHZ
760
 3325          0007CE        	VIA1T1CNT	.SET	((500 * PHI2) - 2)
761
 3326
762
 3327                        	;VIA0INT		.EQU	($80.OR.CA2IFRB.OR.CB2IFRB.OR.T1IFRB)
763
 3328          0000C1        	VIA0INT		.EQU	($80.OR.CA2IFRB.OR.T1IFRB)
764
 3329
765
 3330          000089        	VIA1INT		.EQU	($80.OR.CA2IFRB.OR.CB2IFRB)
766
 3331
767
 3332          00FC04        	BITCR2		.EQU	$FC04
768
 3333          00FC05        	BITCR2ON	.EQU	$FC05
769
 3334
770
 3335          0007D0        	KBDTMO		.EQU	2000	; timeout tastiera in ms
771
 3336  F81286
772
 3337          0001F4        	F8TMO		.EQU	500	; timeout <F8> = 500ms
773
 3338
774
 3339                        	;--------------------------------------------------------------------
775
 3340                        	; SYSTEM BOOTSTRAP
776
 3341                        	;--------------------------------------------------------------------
777
 3342  F81286                	SysStart:
778
 3343                        		; setup iniziale chips I/O
779
 3344  F81286                		CPU08
780
 3345  F81286  E2 30         		sep	#(PMFLAG.OR.PXFLAG)
781
 3346                        		.LONGA	off
782
 3347                        		.LONGI	off
783
 3348                        		.MNLIST
784
 3349                        		;ldx	#RTCCTRLA	;RTC OFF -- reset RTC
785
 3350                        		;stx	RTCALE
786
 3351                        		;stz	RTCDATA
787
 3352
788
 3353  F81288  EA            		nop
789
 3354  F81289  EA            		nop
790
 3355  F8128A  EA            		nop
791
 3356  F8128B  90 01         		bcc	$+3
792
 3357  F8128D  E8            		inx
793
 3358  F8128E  E8            		inx
794
 3359  F8128F
795
 3360          004D43        	MSGN	.EQU	'MC'
796
 3361  F8128F                		ACC16
797
 3362  F8128F  C2 20         		rep	#PMFLAG
798
 3363                        		.LONGA	on
799
 3364                        		.MNLIST
800
 3365  F81291  A9 43 4D      		lda	#MSGN
801
 3366  F81294                		ACC08
802
 3367  F81294  E2 20         		sep	#PMFLAG
803
 3368                        		.LONGA	off
804
 3369                        		.MNLIST
805
 3370  F81296
806
 3371                        		; setup iniziale CTC
807
  Tue Jul 17 11:00:15 2018                                                                                               Page   14
808
 
809
 
810
 
811
 
812
 3372  F81296  A9 30         		lda	#00110000B		; CTC counter 0 in modo 0 - 2 bytes
813
 3373  F81298  8D 4B FD      		sta	CTC0+CTCCTRL
814
 3374  F8129B  A9 70         		lda	#01110000B		; CTC counter 1 in modo 0 - 2 bytes
815
 3375  F8129D  8D 4B FD      		sta	CTC0+CTCCTRL
816
 3376  F812A0  A9 B0         		lda	#10110000B		; CTC counter 2 in modo 0 - 2 bytes
817
 3377  F812A2  8D 4B FD      		sta	CTC0+CTCCTRL
818
 3378  F812A5
819
 3379                        		; setup VIA 0 & 1
820
 3380  F812A5  A2 7F         		ldx	#$7F
821
 3381  F812A7  8E 0E FD      		stx	VIA0+VIAIER		; disabilita interrupt VIA 0
822
 3382  F812AA  8E 0D FD      		stx	VIA0+VIAIFR		; ed azzera tutti i flag
823
 3383  F812AD  8E 1E FD      		stx	VIA1+VIAIER		; disabilita interrupt VIA 1
824
 3384  F812B0  8E 1D FD      		stx	VIA1+VIAIFR		; ed azzera tutti i flag
825
 3385  F812B3  A9 FE         		lda	#$FE			; VIA 0 PA0 -> XM16 -> LOW
826
 3386  F812B5  8D 01 FD      		sta	VIA0+VIAPRA
827
 3387  F812B8  A9 FF         		lda	#$FF			; VIA 0 -> wait disabilitati
828
 3388  F812BA  8D 00 FD      		sta	VIA0+VIAPRB
829
 3389  F812BD  8D 11 FD      		sta	VIA1+VIAPRA		; VIA 1 PORT A uscite alte
830
 3390  F812C0  8D 10 FD      		sta	VIA1+VIAPRB		; VIA 1 PORT B uscite alte
831
 3391  F812C3  8D 03 FD      		sta	VIA0+VIADDRA		; VIA 0 PORT A in output
832
 3392  F812C6  8D 13 FD      		sta	VIA1+VIADDRA		; VIA 1 PORT A in output
833
 3393  F812C9  A9 BF         		lda	#10111111B		; VIA 0 PB6 in input (1KHZ)
834
 3394  F812CB  8D 02 FD      		sta	VIA0+VIADDRB
835
 3395  F812CE  A9 AF         		lda	#10101111B		; VIA 0 PB6, PB4 in input
836
 3396  F812D0  8D 12 FD      		sta	VIA1+VIADDRB
837
 3397                        		; S.R. disabilitato, latch disabilitato, T1 free-run
838
 3398                        		; T2 one shot - PB7 disabilitato - T1 & T2 count PHI2
839
 3399  F812D3  A9 40         		lda	#$40
840
 3400  F812D5  8D 0B FD      		sta	VIA0+VIAACR
841
 3401                        		; S.R. disabilitato, latch disabilitato, T1 free-run
842
 3402                        		; T2 one shot - PB7 abilitato - T1 count PHI2
843
 3403                        		; T2 count PB6 (1KHz) - counter risoluzione  1 ms
844
 3404  F812D8  A9 E0         		lda	#$E0
845
 3405  F812DA  8D 1B FD      		sta	VIA1+VIAACR
846
 3406                        		; CA2, CA1, CB2 fronte negativo, CB1 fronte positivo
847
 3407  F812DD  A9 32         		lda	#00110010B
848
 3408  F812DF  8D 0C FD      		sta	VIA0+VIAPCR
849
 3409                        		; CA2, CB2 fronte negativo, CA1 e CB1 fronte positivo
850
 3410  F812E2  A9 33         		lda	#00110011B
851
 3411  F812E4  8D 1C FD      		sta	VIA1+VIAPCR
852
 3412  F812E7  A9 CE         		lda	#.LOW.VIA1T1CNT		; imposta VIA 1 T1
853
 3413  F812E9  8D 14 FD      		sta	VIA1+VIAT1CL		; PB7 -> 1KHz
854
 3414  F812EC  A9 07         		lda	#.HIGH.VIA1T1CNT
855
 3415  F812EE  8D 15 FD      		sta	VIA1+VIAT1CH
856
 3416  F812F1  A9 FF         		lda	#$FF			; VIA 1 T2 init a $FFFF
857
 3417  F812F3  8D 18 FD      		sta	VIA1+VIAT2CL		; per conteggio iniziale in ms
858
 3418  F812F6  8D 19 FD      		sta	VIA1+VIAT2CH
859
 3419
860
 3420          [01]          	.IF	PHI2 = 4
861
 3421  F812F9  A9 04         		lda	#$04			; abilita WAIT ACIA se PHI2 = 4MHz
862
 3422  F812FB  1C 00 FD      		trb	VIA0+VIAPRB
863
 3423          [00]          	.ENDIF
864
 3424
865
 3425                        		; inizializzazione registri MOS8563 - VDC
866
 3426                        		;lda	#$08
867
 3427                        		;trb	VIA1+VIAPRB		; /VDCS0 - write VDC con PHI0
868
 3428                        		;tsb	VIA1+VIAPRB		; /VDCS0 - write VDC con PHI0
869
  Tue Jul 17 11:00:15 2018                                                                                               Page   15
870
 
871
 
872
 
873
 
874
 3429  F812FE  A9 08         		lda	#$08			; VSYNC negativi su porta VGA
875
 3430  F81300  1C 11 FD      		trb	VIA1+VIAPRA
876
 3431                        		;lda	#$20			; abilita WAIT VDC
877
 3432                        		;trb	VIA0+VIAPRB
878
 3433                        		;tsb	VIA0+VIAPRB
879
 3434
880
 3435                        		;lda	#$20			; /MW0 low
881
 3436                        		;trb	VIA1+VIAPRB
882
 3437  F81303
883
 3438  F81303  A9 18         		lda	#$18			; enable new FDC/DMA/ATA board
884
 3439  F81305  1C 00 FD      		trb	VIA0+VIAPRB		; disable onboard ATA
885
 3440  F81308
886
 3441                        		; setup VIA 3
887
 3442  F81308  A9 7F         		lda	#$7F
888
 3443  F8130A  8D CE FD      		sta	!VIA3+VIAIER		; disabilita interrupt
889
 3444  F8130D  8D CD FD      		sta	!VIA3+VIAIFR		; ed azzera tutti i flag
890
 3445  F81310  A9 07         		lda	#00000111B		; PA<2:0> out, PA<7:3> input
891
 3446  F81312  8D C3 FD      		sta	!VIA3+VIADDRA
892
 3447  F81315  A9 7F         		lda	#$7F
893
 3448  F81317  8D C2 FD      		sta	!VIA3+VIADDRB		; PB<0:6> out, PB7 in
894
 3449  F8131A  9C C1 FD      		stz	!VIA3+VIAPRA		; clear PA in out
895
 3450  F8131D  A9 58         		lda	#11111000
896
 3451  F8131F  8D C0 FD      		sta	!VIA3+VIAPRB
897
 3452  F81322
898
 3453                        		; S.R. disabilitato, latch disabilitato, T1 free-run
899
 3454                        		; T2 one shot - PB7 disabilitato - T1 & T2 count PHI2
900
 3455  F81322  A9 40         		lda	#$40
901
 3456  F81324  8D CB FD      		sta	!VIA3+VIAACR
902
 3457  F81327
903
 3458                        		; CB2, CA2, CB1, CA1, CB1 fronte negative edge
904
 3459  F81327  A9 22         		lda	#00100010B
905
 3460  F81329  8D CC FD      		sta	!VIA3+VIAPCR
906
 3461  F8132C
907
 3462  F8132C  A9 02         		lda	#$02			; imposta dot clock
908
 3463  F8132E  1C 11 FD      		trb	VIA1+VIAPRA		; DOTCLOCK 16MHZ - PAL RGB
909
 3464  F81331  A2 00         		ldx	#0			; indice per setup 16MHZ
910
 3465
911
 3466  F81333  BF 48 AF F8   	?00a:	LDA	VDCREG16,X
912
 3467  F81337  30 0F         		BMI	?00b
913
 3468  F81339  A8            		tay
914
 3469  F8133A  E8            		INX
915
 3470  F8133B  BF 48 AF F8   		LDA	VDCREG16,X
916
 3471  F8133F  E8            		INX
917
 3472  F81340  8C 4E FD      		STY	VDCAddr
918
 3473  F81343  8D 4F FD      		STA	VDCData
919
 3474  F81346  10 EB         		BPL	?00a
920
 3475  F81348                	?00b:
921
 3476
922
 3477                        		; setup PIA 0
923
 3478  F81348  9C 29 FD      		stz	PIA0+PIACRA		; IRQ disabilitati
924
 3479  F8134B  9C 2B FD      		stz	PIA0+PIACRB		; accesso DDRA,DDRB
925
 3480  F8134E  A9 FF         		lda	#$FF			; porta A output
926
 3481  F81350  8D 28 FD      		sta	PIA0+PIADDRA
927
 3482  F81353  A9 0F         		lda	#00001111B
928
 3483  F81355  8D 2A FD      		sta	PIA0+PIADDRB		; porta B<7:4> input
929
 3484  F81358  A9 3C         		lda	#00111100B		; accesso a PRA e PRB
930
 3485  F8135A  8D 29 FD      		sta	PIA0+PIACRA		; CA2/CB2 in modo output H
931
  Tue Jul 17 11:00:15 2018                                                                                               Page   16
932
 
933
 
934
 
935
 
936
 3486  F8135D  8D 2B FD      		sta	PIA0+PIACRB
937
 3487  F81360  9C 28 FD      		stz	PIA0+PIAPRA
938
 3488  F81363  9C 2A FD      		stz	PIA0+PIAPRB
939
 3489
940
 3490                        		; clear cmos user ram banco 0
941
 3491  F81366  A2 0A         		ldx	#RTCCTRLA		; accesso CMOS RAM banco 0
942
 3492  F81368  8E 4C FD      		stx	RTCALE
943
 3493  F8136B  A9 10         		lda	#00010000B
944
 3494  F8136D  1C 4D FD      		trb	RTCDATA			; banco 0
945
 3495  F81370  A2 40         		ldx	#RTCURAM0		; accesso  user ram banco 0
946
 3496  F81372  A0 3F         		ldy	#(RTCURAM0LAST - RTCURAM0)
947
 3497  F81374  8E 4C FD      	?01:	stx	RTCALE			; azzera cmos user ram 0
948
 3498  F81377  9C 4D FD      		stz	RTCDATA
949
 3499  F8137A  E8            		inx
950
 3500  F8137B  88            		dey
951
 3501  F8137C  10 F6         		bpl	?01
952
 3502  F8137E  A2 40         		ldx	#RTCURAM0
953
 3503  F81380  8E 4C FD      		stx	RTCALE			; $40
954
 3504
955
 3505                        		; setup PIA 1 - LCD
956
 3506  F81383  9C 39 FD      		stz	PIA1+PIACRA		; IRQ disabilitati
957
 3507  F81386  9C 3B FD      		stz	PIA1+PIACRB		; accesso DDRA,DDRB
958
 3508  F81389  A0 FF         		ldy	#$FF			; porta A output
959
 3509  F8138B  8C 38 FD      		sty	PIA1+PIADDRA
960
 3510  F8138E  9C 3A FD      		stz	PIA1+PIADDRB		; porta B input
961
 3511  F81391  A9 04         		lda	#0000100B		; accesso a PRA
962
 3512  F81393  8D 39 FD      		sta	PIA1+PIACRA
963
 3513  F81396  A0 02         		ldy	#0000010B		; linea RW high - E, RS low
964
 3514  F81398  8C 38 FD      		sty	PIA1+PIAPRA
965
 3515  F8139B  A0 00         		ldy	#0
966
 3516  F8139D  8C 3A FD      	?02:	sty	PIA1+PIADDRB		; test PIA LCD presente
967
 3517  F813A0  CC 3A FD      		cpy	PIA1+PIADDRB
968
 3518  F813A3  D0 03         		bne	?03
969
 3519  F813A5  C8            		iny
970
 3520  F813A6  D0 F5         		bne	?02
971
 3521  F813A8  9C 3A FD      	?03:	stz	PIA1+PIADDRB		; porta B input
972
 3522  F813AB  8D 3B FD      		sta	PIA1+PIACRB		; accesso a PRB
973
 3523  F813AE  D0 05         		bne	?04			; LCD non presente
974
 3524  F813B0  A9 80         		lda	#$80			; flag LCD presente -> $40
975
 3525  F813B2  8D 4D FD      		sta	RTCDATA
976
 3526  F813B5  E8            	?04:	inx				; $41
977
 3527  F813B6  8E 4C FD      		stx	RTCALE
978
 3528
979
 3529                        		; test & setup ACIA
980
 3530  F813B9  A9 7F         		lda	#$7F			; cancella IER1/IER2
981
 3531  F813BB  8D 50 FD      		sta	ACIA+ACIAIER1
982
 3532  F813BE  8D 54 FD      		sta	ACIA+ACIAIER2
983
 3533  F813C1  AD 50 FD      		lda	ACIA+ACIAISR1		; legge registri di stato
984
 3534  F813C4  AD 54 FD      		lda	ACIA+ACIAISR2		; per cancellare flag
985
 3535  F813C7  AD 51 FD      		lda	ACIA+ACIACSR1		; legge registri control status
986
 3536  F813CA  AD 55 FD      		lda	ACIA+ACIACSR2
987
 3537  F813CD  AD 53 FD      		lda	ACIA+ACIARDR1		; legge registri RX data
988
 3538  F813D0  AD 57 FD      		lda	ACIA+ACIARDR2		; per cancellare flag
989
 3539  F813D3  A9 4E         		lda	#01001110B		; 38400 - 1 stop bit - no echo - ACR
990
 3540  F813D5  8D 51 FD      		sta	ACIA+ACIACR1		; imposta reg. controllo CR
991
 3541  F813D8  8D 55 FD      		sta	ACIA+ACIACR2
992
 3542  F813DB  A9 E7         		lda	#11100111B		; odd parity - 8 bit - RTS/DTR -> H
993
  Tue Jul 17 11:00:15 2018                                                                                               Page   17
994
 
995
 
996
 
997
 
998
 3543  F813DD  8D 51 FD      		sta	ACIA+ACIAFR1		; imposta registro di formato FR
999
 3544  F813E0  8D 55 FD      		sta	ACIA+ACIAFR2
1000
 3545  F813E3  9C 52 FD      		stz	ACIA+ACIAACR1		; parity in status - normal TX
1001
 3546  F813E6  9C 56 FD      		stz	ACIA+ACIAACR2		; imposta registri aux. controllo
1002
 3547  F813E9  A0 80         		ldy	#$80			; flag ACIA canale 1
1003
 3548  F813EB  AD 51 FD      		lda	ACIA+ACIACSR1
1004
 3549  F813EE  29 20         		and	#00100000B		; maschera bit CTS1 LVL
1005
 3550  F813F0  8D 4D FD      		sta	RTCDATA			; salva
1006
 3551  F813F3  A9 20         		lda	#00100000B		; inverte CTS1
1007
 3552  F813F5  1C 11 FD      		trb	VIA1+VIAPRA
1008
 3553  F813F8  AD 51 FD      		lda	ACIA+ACIACSR1		; legge livello CTS1
1009
 3554  F813FB  29 20         		and	#00100000B		; maschera bit CTS1 LVL
1010
 3555  F813FD  4D 4D FD      		eor	RTCDATA			; confronta con lettura precedente
1011
 3556  F81400  D0 02         		bne	?06			; OK - CTS1 invertito
1012
 3557  F81402  A0 00         		ldy	#0			; ACIA canale 1 BAD
1013
 3558  F81404  8C 4D FD      	?06:	sty	RTCDATA
1014
 3559  F81407  E8            		inx				; $42
1015
 3560  F81408  8E 4C FD      		stx	RTCALE
1016
 3561  F8140B  A0 40         		ldy	#$40			; flag ACIA canale 2
1017
 3562  F8140D  AD 55 FD      		lda	ACIA+ACIACSR2
1018
 3563  F81410  29 20         		and	#00100000B		; maschera bit CTS2 LVL
1019
 3564  F81412  8D 4D FD      		sta	RTCDATA			; salva
1020
 3565  F81415  A9 40         		lda	#01000000B		; inverte CTS2
1021
 3566  F81417  1C 11 FD      		trb	VIA1+VIAPRA
1022
 3567  F8141A  AD 55 FD      		lda	ACIA+ACIACSR2		; legge livello CTS2
1023
 3568  F8141D  29 20         		and	#00100000B		; maschera bit CTS2 LVL
1024
 3569  F8141F  4D 4D FD      		eor	RTCDATA			; confronta con lettura precedente
1025
 3570  F81422  D0 02         		bne	?08			; OK - CTS2 invertito
1026
 3571  F81424  A0 00         		ldy	#0			; ACIA canale 2 BAD
1027
 3572  F81426  9C 4D FD      	?08:	stz	RTCDATA
1028
 3573  F81429  CA            		dex				; $41
1029
 3574  F8142A  8E 4C FD      		stx	RTCALE
1030
 3575  F8142D  98            		tya
1031
 3576  F8142E  0C 4D FD      		tsb	RTCDATA			; set flag ACIA canale 2
1032
 3577  F81431  E8            		inx				; $42
1033
 3578  F81432  8E 4C FD      		stx	RTCALE
1034
 3579  F81435  AD 50 FD      		lda	ACIA+ACIAISR1		; legge registri di stato
1035
 3580  F81438  AD 54 FD      		lda	ACIA+ACIAISR2		; per cancellare flag
1036
 3581  F8143B  AD 51 FD      		lda	ACIA+ACIACSR1		; legge registri control status
1037
 3582  F8143E  AD 55 FD      		lda	ACIA+ACIACSR2
1038
 3583  F81441  AD 53 FD      		lda	ACIA+ACIARDR1		; legge registri RX data
1039
 3584  F81444  AD 57 FD      		lda	ACIA+ACIARDR2		; per cancellare flag
1040
 3585  F81447
1041
 3586                        		; test & setup DMA - non necessario il wait a 4MHz
1042
 3587  F81447  A0 00         		ldy	#0			; flag DMA
1043
 3588  F81449  8D 9D FD      		sta	DMAWMCLR		; master clear
1044
 3589  F8144C  8D 8D FD      		sta	DMA0WMCLR		; master clear
1045
 3590  F8144F  EA            		nop
1046
 3591  F81450  8D 9C FD      		sta	DMAWCLRFF		; clear FF
1047
 3592  F81453  8D 8C FD      		sta	DMA0WCLRFF		; clear FF
1048
 3593  F81456  EA            		nop
1049
 3594  F81457  A9 01         		lda	#00000001B		; M-to-M chan.0&1 - contr. enabled
1050
 3595  F81459  8D 98 FD      		sta	DMAWCMD			; registro di comando
1051
 3596  F8145C  9C 88 FD      		stz	DMA0WCMD		; enabled
1052
 3597  F8145F  EA            		nop
1053
 3598  F81460  A9 FF         		lda	#$FF			; maschera tutti i bit
1054
 3599  F81462  8D 9F FD      		sta	DMAMASK
1055
  Tue Jul 17 11:00:15 2018                                                                                               Page   18
1056
 
1057
 
1058
 
1059
 
1060
 3600  F81465  8D 8F FD      		sta	DMA0MASK
1061
 3601  F81468  EA            		nop
1062
 3602                        		;lda	#10001000B		; modo read mem chan 0
1063
 3603  F81469  A9 44         		lda	#01000100B		; modo read mem chan 0
1064
 3604  F8146B  8D 9B FD      		sta	DMAMODE			; block mode
1065
 3605  F8146E  EA            		nop
1066
 3606                        		;lda	#10000101B		; modo write mem chan 1
1067
 3607  F8146F  A9 45         		lda	#01000101B
1068
 3608  F81471  8D 9B FD      		sta	DMAMODE			; block mode
1069
 3609  F81474  EA            		nop
1070
 3610                        		;lda	#01001010B		; modo read mem chan 2
1071
 3611  F81475  A9 46         		lda	#01000110B
1072
 3612  F81477  8D 9B FD      		sta	DMAMODE			; single transf.
1073
 3613  F8147A  EA            		nop
1074
 3614                        		;lda	#01001011B		; modo read mem chan 3
1075
 3615  F8147B  A9 47         		lda	#01000111B
1076
 3616  F8147D  8D 9B FD      		sta	DMAMODE			; single transf.
1077
 3617  F81480  EA            		nop
1078
 3618  F81481  A9 08         		lda	#00001000B		; demand mode chan 0
1079
 3619  F81483  8D 8B FD      		sta	DMA0MODE
1080
 3620  F81486  EA            		nop
1081
 3621  F81487  A9 09         		lda	#00001001B		; demand mode chan 1
1082
 3622  F81489  8D 8B FD      		sta	DMA0MODE
1083
 3623  F8148C  EA            		nop
1084
 3624  F8148D  A9 0A         		lda	#00001010B		; demand mode chan 2
1085
 3625  F8148F  8D 8B FD      		sta	DMA0MODE
1086
 3626  F81492  EA            		nop
1087
 3627  F81493  A9 0B         		lda	#00001011B		; demand mode chan 3
1088
 3628  F81495  8D 8B FD      		sta	DMA0MODE
1089
 3629  F81498  EA            		nop
1090
 3630  F81499  AD 98 FD      		lda	DMASR			; clr status reg.
1091
 3631  F8149C  EA            		nop
1092
 3632  F8149D  AD 88 FD      		lda	DMA0SR			; clr status reg.
1093
 3633  F814A0  EA            		nop
1094
 3634  F814A1  AD 9E FD      		lda	DMARCNT			; clear mode counter
1095
 3635  F814A4  EA            		nop
1096
 3636  F814A5  AD 8E FD      		lda	DMA0RCNT		; clear mode counter
1097
 3637  F814A8  EA            		nop
1098
 3638  F814A9
1099
 3639  F814A9  9C 90 FD      		stz	DMAC+DMAADDR0
1100
 3640  F814AC  9C 80 FD      		stz	DMAC0+DMAADDR0
1101
 3641  F814AF  9C 90 FD      		stz	DMAC+DMAADDR0
1102
 3642  F814B2  9C 80 FD      		stz	DMAC0+DMAADDR0
1103
 3643  F814B5  9C 91 FD      		stz	DMAC+DMACNT0
1104
 3644  F814B8  9C 81 FD      		stz	DMAC0+DMACNT0
1105
 3645  F814BB  9C 91 FD      		stz	DMAC+DMACNT0
1106
 3646  F814BE  9C 81 FD      		stz	DMAC0+DMACNT0
1107
 3647
1108
 3648  F814C1  9C 92 FD      		stz	DMAC+DMAADDR1
1109
 3649  F814C4  9C 82 FD      		stz	DMAC0+DMAADDR1
1110
 3650  F814C7  9C 92 FD      		stz	DMAC+DMAADDR1
1111
 3651  F814CA  9C 82 FD      		stz	DMAC0+DMAADDR1
1112
 3652  F814CD  9C 93 FD      		stz	DMAC+DMACNT1
1113
 3653  F814D0  9C 83 FD      		stz	DMAC0+DMACNT1
1114
 3654  F814D3  9C 93 FD      		stz	DMAC+DMACNT1
1115
 3655  F814D6  9C 83 FD      		stz	DMAC0+DMACNT1
1116
 3656  F814D9
1117
  Tue Jul 17 11:00:15 2018                                                                                               Page   19
1118
 
1119
 
1120
 
1121
 
1122
 3657  F814D9  9C 94 FD      		stz	DMAC+DMAADDR2
1123
 3658  F814DC  9C 84 FD      		stz	DMAC0+DMAADDR2
1124
 3659  F814DF  9C 94 FD      		stz	DMAC+DMAADDR2
1125
 3660  F814E2  9C 84 FD      		stz	DMAC0+DMAADDR2
1126
 3661  F814E5  9C 95 FD      		stz	DMAC+DMACNT2
1127
 3662  F814E8  9C 85 FD      		stz	DMAC0+DMACNT2
1128
 3663  F814EB  9C 95 FD      		stz	DMAC+DMACNT2
1129
 3664  F814EE  9C 85 FD      		stz	DMAC0+DMACNT2
1130
 3665
1131
 3666  F814F1  9C 96 FD      		stz	DMAC+DMAADDR3
1132
 3667  F814F4  9C 86 FD      		stz	DMAC0+DMAADDR3
1133
 3668  F814F7  9C 96 FD      		stz	DMAC+DMAADDR3
1134
 3669  F814FA  9C 86 FD      		stz	DMAC0+DMAADDR3
1135
 3670  F814FD  9C 97 FD      		stz	DMAC+DMACNT3
1136
 3671  F81500  9C 87 FD      		stz	DMAC0+DMACNT3
1137
 3672  F81503  9C 97 FD      		stz	DMAC+DMACNT3
1138
 3673  F81506  9C 87 FD      		stz	DMAC0+DMACNT3
1139
 3674
1140
 3675  F81509  AD 9B FD      		lda	DMAMODE			; verifica MODE REG.CH0
1141
 3676                        		;cmp	#10001011B
1142
 3677  F8150C  C9 47         		cmp	#$47
1143
 3678                        		;bne	?10			; errore
1144
 3679  F8150E  AD 9B FD      		lda	DMAMODE			; verifica MODE REG.CH1
1145
 3680  F81511  C9 47         		cmp	#$47
1146
 3681                        		;cmp	#10000111B
1147
 3682                        		;bne	?10			; errore
1148
 3683  F81513  AD 9B FD      		lda	DMAMODE			; verifica MODE REG.CH2
1149
 3684                        		;cmp	#01001011B
1150
 3685  F81516  C9 47         		cmp	#$47
1151
 3686                        		;bne	?10			; errore
1152
 3687  F81518  AD 9B FD      		lda	DMAMODE			; verifica MODE REG.CH3
1153
 3688                        		;cmp	#01001011B
1154
 3689  F8151B  C9 47         		cmp	#$47
1155
 3690                        		;bne	?10			; errore
1156
 3691  F8151D  AD 9A FD      		lda	DMARCMD			; verifica registro di comando
1157
 3692  F81520  C9 01         		cmp	#00000001B
1158
 3693                        		;bne	?10
1159
 3694  F81522  AD 98 FD      		lda	DMASR			; clr status reg.
1160
 3695  F81525  EA            		nop
1161
 3696  F81526  A9 FF         	?09:	lda	#$FF			; !!!! FAIL SOME TIMES
1162
 3697  F81528  8D 9F FD      		sta	DMAMASK
1163
 3698  F8152B  EA            		nop
1164
 3699  F8152C  8D 8F FD      		sta	DMA0MASK
1165
 3700  F8152F
1166
 3701  F8152F  AD 9F FD      		lda	DMAMASK			; verifica maschera
1167
 3702  F81532  C9 FF         		cmp	#$FF
1168
 3703                        		;bne	?09
1169
 3704                        		;bne	?10
1170
 3705  F81534  A0 04         		ldy	#$04			; flag DMA OK
1171
 3706  F81536  8C 4D FD      	?10:	sty	RTCDATA			; $42 -> flag DMA
1172
 3707
1173
 3708  F81539  A0 01         		ldy	#1
1174
 3709  F8153B  AD 8B FD      		lda	DMA0MODE
1175
 3710  F8153E  C9 0B         		cmp	#$0B
1176
 3711  F81540  D0 28         		bne	?10b
1177
 3712  F81542  C8            		iny
1178
 3713  F81543  AD 8B FD      		lda	DMA0MODE
1179
  Tue Jul 17 11:00:15 2018                                                                                               Page   20
1180
 
1181
 
1182
 
1183
 
1184
 3714  F81546  C9 0B         		cmp	#$0B
1185
 3715  F81548  D0 20         		bne	?10b
1186
 3716  F8154A  C8            		iny
1187
 3717  F8154B  AD 8B FD      		lda	DMA0MODE
1188
 3718  F8154E  C9 0B         		cmp	#$0B
1189
 3719  F81550  D0 18         		bne	?10b
1190
 3720  F81552  C8            		iny
1191
 3721  F81553  AD 8B FD      		lda	DMA0MODE
1192
 3722  F81556  C9 0B         		cmp	#$0B
1193
 3723  F81558  D0 10         		bne	?10b
1194
 3724  F8155A  C8            		iny
1195
 3725  F8155B  AD 8A FD      		lda	DMA0RCMD			; verifica registro di comando
1196
 3726  F8155E  D0 0A         		bne	?10b
1197
 3727  F81560  C8            		iny
1198
 3728  F81561  AD 8F FD      		lda	DMA0MASK			; verifica maschera
1199
 3729  F81564  C9 FF         		cmp	#$FF
1200
 3730                        		;bne	?09
1201
 3731  F81566  D0 02         		bne	?10b
1202
 3732  F81568  A0 00         		ldy	#0
1203
 3733  F8156A                	?10b:
1204
 3734  F8156A  A9 70         		lda	#$70
1205
 3735  F8156C  8D 4C FD      		sta	RTCALE			; $70
1206
 3736  F8156F  8C 4D FD      		sty	RTCDATA
1207
 3737  F81572
1208
 3738  F81572  A0 4E         		ldy	#$4E
1209
 3739  F81574  8C 4C FD      		sty	RTCALE			; $4E
1210
 3740
1211
 3741                        		; check video board
1212
 3742  F81577  A9 3C         		lda	#00111100B		; CA2,CB2 HIGH, PRA, PRB
1213
 3743  F81579  8D 75 FC      		sta	!PIAVBB+PIACRA
1214
 3744  F8157C  8D 77 FC      		sta	!PIAVBB+PIACRB
1215
 3745  F8157F  A2 FF         		ldx	#$FF
1216
 3746  F81581  8E 74 FC      		stx	PIAVBB+PIAPRA		; porta A tutte high
1217
 3747  F81584  8E 76 FC      		stx	PIAVBB+PIAPRB		; porta B tutte high
1218
 3748  F81587  A9 38         		lda	#00111000B		; CA2,CB2 HIGH, DDRA, DDRB
1219
 3749  F81589  8D 75 FC      		sta	!PIAVBB+PIACRA
1220
 3750  F8158C  8D 77 FC      		sta	!PIAVBB+PIACRB
1221
 3751  F8158F  8E 74 FC      		stx	PIAVBB+PIADDRA		; pota A tutte out
1222
 3752  F81592  8E 76 FC      		stx	PIAVBB+PIADDRB		; pota B tutte out
1223
 3753  F81595  A9 3E         		lda	#00111110B		; CA2 HIGH (FH -), PRA, CA1 fronte +
1224
 3754  F81597  8D 75 FC      		sta	!PIAVBB+PIACRA		; no IRQ
1225
 3755  F8159A  A9 38         		lda	#00111000B		; CB2 LOW (FV +), PRA, CA1 non usato
1226
 3756  F8159C  8D 77 FC      		sta	!PIAVBB+PIACRB		; no IRQ
1227
 3757  F8159F  A2 80         		ldx	#$80			; PB7 HIGH -> display off
1228
 3758  F815A1  8E 76 FC      	?12:	stx	PIAVBB+PIAPRB		; test porta B
1229
 3759  F815A4  EC 76 FC      		cpx	PIAVBB+PIAPRB
1230
 3760  F815A7  F0 01         		beq	?12a
1231
 3761                        		;jmp	?20a			; video board non presente
1232
 3762  F815A9  EA            		nop
1233
 3763  F815AA  E8            	?12a:	inx
1234
 3764  F815AB  D0 F4         		bne	?12
1235
 3765  F815AD  A9 80         		lda	#$80			; flag video board
1236
 3766  F815AF  8D 4D FD      		sta	!RTCDATA		; -> $4E
1237
 3767  F815B2
1238
 3768                        		; HD6445: registri R12 e R13 sono read/write
1239
 3769  F815B2  A9 0D         		lda	#$0D
1240
 3770  F815B4  8D 70 FC      		sta	!CRTAddr
1241
  Tue Jul 17 11:00:15 2018                                                                                               Page   21
1242
 
1243
 
1244
 
1245
 
1246
 3771  F815B7  A2 00         		ldx	#0
1247
 3772  F815B9  8E 71 FC      	?13:	stx	CRTData
1248
 3773  F815BC  EC 71 FC      		cpx	CRTData
1249
 3774  F815BF  D0 08         		bne	?13a			; R6545
1250
 3775  F815C1  E8            		inx
1251
 3776  F815C2  D0 F5         		bne	?13
1252
 3777  F815C4  A9 C0         		lda	#$C0			; flag video board + HD6445
1253
 3778  F815C6  8D 4D FD      		sta	!RTCDATA		; -> $4E
1254
 3779  F815C9
1255
 3780                        		; inizializza registri R6545/HD6445 (CRTC)
1256
 3781  F815C9  A2 00         	?13a:	ldx	#0
1257
 3782  F815CB  BF 08 1F F8   	?13b:	LDA	>CRTCREG,X
1258
 3783  F815CF  30 0F         		BMI	?13c
1259
 3784  F815D1  A8            		tay
1260
 3785  F815D2  E8            		INX
1261
 3786  F815D3  BF 08 1F F8   		LDA	>CRTCREG,X
1262
 3787  F815D7  E8            		INX
1263
 3788  F815D8  8C 70 FC      		STY	CRTAddr
1264
 3789  F815DB  8D 71 FC      		STA	!CRTData
1265
 3790  F815DE  10 EB         		BPL	?13b
1266
 3791  F815E0
1267
 3792  F815E0  A9 C0         	?13c:	lda	#$C0			; palette address = 0, SLW = 1, VGA
1268
 3793  F815E2  8D 74 FC      		sta	!PIAVBB+PIAPRA
1269
 3794  F815E5
1270
 3795                        		; test VIDEO RAM
1271
 3796  F815E5  A2 00         		ldx	#0
1272
 3797  F815E7  9B            		txy
1273
 3798  F815E8  8D 0D FC      		sta	!CREMEON		; abilita memoria video
1274
 3799  F815EB                		INDEX16
1275
 3800  F815EB  C2 10         		rep	#PXFLAG
1276
 3801                        		.LONGI	on
1277
 3802                        		.MNLIST
1278
 3803  F815ED  A9 55         	?14:	lda	#$55
1279
 3804  F815EF  9F 00 00 01   		sta	>VBBCHARRAM,x
1280
 3805  F815F3  DF 00 00 01   		cmp	>VBBCHARRAM,x
1281
 3806  F815F7  D0 6B         		bne	?16			; Y =  -> fail char. ram
1282
 3807  F815F9  A9 AA         		lda	#$AA
1283
 3808  F815FB  9F 00 00 01   		sta	>VBBCHARRAM,x
1284
 3809  F815FF  DF 00 00 01   		cmp	>VBBCHARRAM,x
1285
 3810  F81603  D0 5F         		bne	?16			; Y = 0 -> fail char. ram
1286
 3811  F81605  A9 20         		lda	#$20
1287
 3812  F81607  9F 00 00 01   		sta	>VBBCHARRAM,x
1288
 3813  F8160B  E8            		inx
1289
 3814  F8160C  E0 00 08      		cpx	#$0800
1290
 3815  F8160F  D0 DC         		bne	?14
1291
 3816  F81611  BB            		tyx
1292
 3817  F81612  A9 55         	?14a:	lda	#$55
1293
 3818  F81614  9F 00 08 01   		sta	>VBBATTRRAM,x
1294
 3819  F81618  DF 00 08 01   		cmp	>VBBATTRRAM,x
1295
 3820  F8161C  D0 1B         		bne	?14b
1296
 3821  F8161E  A9 AA         		lda	#$AA
1297
 3822  F81620  9F 00 08 01   		sta	>VBBATTRRAM,x
1298
 3823  F81624  DF 00 08 01   		cmp	>VBBATTRRAM,x
1299
 3824  F81628  D0 0F         		bne	?14b
1300
 3825  F8162A  A9 00         		lda	#$00
1301
 3826  F8162C  9F 00 08 01   		sta	>VBBATTRRAM,x
1302
 3827  F81630  E8            		inx
1303
  Tue Jul 17 11:00:15 2018                                                                                               Page   22
1304
 
1305
 
1306
 
1307
 
1308
 3828  F81631  E0 00 08      		cpx	#$0800
1309
 3829  F81634  D0 DC         		bne	?14a
1310
 3830  F81636  BB            		tyx
1311
 3831  F81637  F0 03         		beq	?14c
1312
 3832  F81639  C8            	?14b:	iny				; Y = 1 -> fail attr. ram
1313
 3833  F8163A  D0 28         		bne	?16
1314
 3834  F8163C  A9 55         	?14c:	lda	#$55
1315
 3835  F8163E  9F 00 10 01   		sta	>VBBPALRAM,x
1316
 3836  F81642  DF 00 10 01   		cmp	>VBBPALRAM,x
1317
 3837  F81646  D0 1B         		bne	?15
1318
 3838  F81648  A9 AA         		lda	#$AA
1319
 3839  F8164A  9F 00 10 01   		sta	>VBBPALRAM,x
1320
 3840  F8164E  DF 00 10 01   		cmp	>VBBPALRAM,x
1321
 3841  F81652  D0 0F         		bne	?15
1322
 3842  F81654  A9 F0         		lda	#$F0
1323
 3843  F81656  9F 00 10 01   		sta	>VBBPALRAM,x
1324
 3844  F8165A  E8            		inx
1325
 3845  F8165B  E0 00 04      		cpx	#$0400
1326
 3846  F8165E  D0 DC         		bne	?14c
1327
 3847  F81660  18            		clc				; RAM ok
1328
 3848  F81661  F0 02         		beq	?16a
1329
 3849  F81663  C8            	?15:	iny				; Y = 2 -> fail palette ram
1330
 3850  F81664  38            	?16:	sec				; CF = 1 -> ram fail
1331
 3851  F81665  8A            	?16a:	txa				; C -> fail address
1332
 3852  F81666                		INDEX08
1333
 3853  F81666  E2 10         		sep	#PXFLAG
1334
 3854                        		.LONGI	off
1335
 3855                        		.MNLIST
1336
 3856  F81668  90 29         		bcc	?16d
1337
 3857  F8166A  A2 50         		ldx	#$50
1338
 3858  F8166C  8E 4C FD      		stx	RTCALE
1339
 3859  F8166F  8D 4D FD      		sta	RTCDATA			; $50-$51-$52 -> fail address
1340
 3860  F81672  EB            		xba
1341
 3861  F81673  E8            		inx
1342
 3862  F81674  8E 4C FD      		stx	RTCALE
1343
 3863  F81677  C0 00         		cpy	#0
1344
 3864  F81679  F0 0A         		beq	?16c
1345
 3865  F8167B  18            		clc
1346
 3866  F8167C  88            		dey
1347
 3867  F8167D  D0 04         		bne	?16b
1348
 3868  F8167F  69 08         		adc	#$08
1349
 3869  F81681  80 02         		bra	?16c
1350
 3870  F81683  69 10         	?16b:	adc	#$10
1351
 3871  F81685  8D 4D FD      	?16c:	sta	RTCDATA
1352
 3872  F81688  E8            		inx
1353
 3873  F81689  8E 4C FD      		stx	RTCALE
1354
 3874  F8168C  A9 01         		lda	#$01
1355
 3875  F8168E  8D 4D FD      		sta	RTCDATA
1356
 3876  F81691  80 2C         		bra	?20b
1357
 3877  F81693  A2 4F         	?16d:	ldx	#$4F
1358
 3878  F81695  8E 4C FD      		stx	RTCALE
1359
 3879  F81698  A9 80         		lda	#$80			; $4F -> flag video ram OK
1360
 3880  F8169A  8D 4D FD      		sta	!RTCDATA
1361
 3881  F8169D  A9 80         		lda	#$80
1362
 3882  F8169F  1C 76 FC      		trb	!PIAVBB+PIAPRB
1363
 3883  F816A2
1364
 3884  F816A2  A9 08         		lda	#$08
1365
  Tue Jul 17 11:00:15 2018                                                                                               Page   23
1366
 
1367
 
1368
 
1369
 
1370
 3885  F816A4  8F 00 00 01   		sta	>$010000
1371
 3886  F816A8  8F 4F 00 01   		sta	>$01004f
1372
 3887  F816AC  8F 80 07 01   		sta	>$010780
1373
 3888  F816B0  8F CF 07 01   		sta	>$0107CF
1374
 3889  F816B4  A9 0F         		lda	#$0F
1375
 3890  F816B6  8D 72 FC      		sta	!URLVBB
1376
 3891  F816B9  A9 20         		lda	#$20
1377
 3892  F816BB  8F 81 0F 01   		sta	>$010F81
1378
 3893                        		;lda	#$04
1379
 3894                        		;trb	!PIAVBB+PIAPRB
1380
 3895  F816BF
1381
 3896  F816BF  8D 0C FC      	?20b:	sta	!CREMEOFF		; abilita memoria normale
1382
 3897
1383
 3898                        	?20a:	; check serial/usb test board
1384
 3899  F816C2  A2 53         		ldx	#$53
1385
 3900  F816C4  8E 4C FD      		stx	RTCALE			; $53 -> tstser flag
1386
 3901  F816C7  A9 00         		lda	#0			; clear flag
1387
 3902  F816C9  A0 55         		ldy	#$55			; check VIA2
1388
 3903  F816CB  8C 12 FC      		sty	.ABS.VIA2+VIADDRB
1389
 3904  F816CE  CC 12 FC      		cpy	.ABS.VIA2+VIADDRB
1390
 3905  F816D1  D0 20         		bne	?z21			; fail
1391
 3906  F816D3  A0 AA         		ldy	#$AA
1392
 3907  F816D5  8C 12 FC      		sty	.ABS.VIA2+VIADDRB
1393
 3908  F816D8  CC 12 FC      		cpy	.ABS.VIA2+VIADDRB
1394
 3909  F816DB  D0 16         		bne	?z21			; fail
1395
 3910  F816DD  A0 C3         		ldy	#$C3
1396
 3911  F816DF  8C 12 FC      		sty	.ABS.VIA2+VIADDRB
1397
 3912  F816E2  CC 12 FC      		cpy	.ABS.VIA2+VIADDRB
1398
 3913  F816E5  D0 0C         		bne	?z21			; fail
1399
 3914  F816E7  A0 3C         		ldy	#$3C
1400
 3915  F816E9  8C 12 FC      		sty	.ABS.VIA2+VIADDRB
1401
 3916  F816EC  CC 12 FC      		cpy	.ABS.VIA2+VIADDRB
1402
 3917  F816EF  D0 02         		bne	?z21			; fail
1403
 3918  F816F1  A9 80         		lda	#$80			; set bit <7>: VIA2 ok
1404
 3919  F816F3  A0 55         	?z21:	ldy	#$55			; check UART 16C550 (scratchpad reg.)
1405
 3920  F816F5  8C 27 FC      		sty	.ABS.UART_SCP
1406
 3921  F816F8  CC 27 FC      		cpy	.ABS.UART_SCP
1407
 3922  F816FB  D0 20         		bne	?z22			; fail
1408
 3923  F816FD  A0 AA         		ldy	#$AA
1409
 3924  F816FF  8C 27 FC      		sty	.ABS.UART_SCP
1410
 3925  F81702  CC 27 FC      		cpy	.ABS.UART_SCP
1411
 3926  F81705  D0 16         		bne	?z22			; fail
1412
 3927  F81707  A0 C3         		ldy	#$C3
1413
 3928  F81709  8C 27 FC      		sty	.ABS.UART_SCP
1414
 3929  F8170C  CC 27 FC      		cpy	.ABS.UART_SCP
1415
 3930  F8170F  D0 0C         		bne	?z22			; fail
1416
 3931  F81711  A0 3C         		ldy	#$3C
1417
 3932  F81713  8C 27 FC      		sty	.ABS.UART_SCP
1418
 3933  F81716  CC 27 FC      		cpy	.ABS.UART_SCP
1419
 3934  F81719  D0 02         		bne	?z22			; fail
1420
 3935  F8171B  09 02         		ora	#$02			; set bit <1>: uart 16C550 ok
1421
 3936  F8171D  A0 55         	?z22:	ldy	#$55			; check R65C51 (control reg.)
1422
 3937  F8171F  8C 2B FC      		sty	.ABS.ACIACTRL
1423
 3938  F81722  CC 2B FC      		cpy	.ABS.ACIACTRL
1424
 3939  F81725  D0 2E         		bne	?z23			; fail
1425
 3940  F81727  A0 AA         		ldy	#$AA
1426
 3941  F81729  8C 2B FC      		sty	.ABS.ACIACTRL
1427
  Tue Jul 17 11:00:15 2018                                                                                               Page   24
1428
 
1429
 
1430
 
1431
 
1432
 3942  F8172C  CC 2B FC      		cpy	.ABS.ACIACTRL
1433
 3943  F8172F  D0 24         		bne	?z23			; fail
1434
 3944  F81731  A0 C3         		ldy	#$C3
1435
 3945  F81733  8C 2B FC      		sty	.ABS.ACIACTRL
1436
 3946  F81736  CC 2B FC      		cpy	.ABS.ACIACTRL
1437
 3947  F81739  D0 1A         		bne	?z23			; fail
1438
 3948  F8173B  A0 3C         		ldy	#$3C
1439
 3949  F8173D  8C 2B FC      		sty	.ABS.ACIACTRL
1440
 3950  F81740  CC 2B FC      		cpy	.ABS.ACIACTRL
1441
 3951  F81743  D0 10         		bne	?z23			; fail
1442
 3952  F81745  09 01         		ora	#$01			; set bit <0>: acia R65C51 ok
1443
 3953  F81747
1444
 3954  F81747  8D 29 FC      		sta	ACIASR		; software reset
1445
 3955  F8174A  A0 02         		ldy	#ACIACMDOFF	; disabilita tutto
1446
 3956  F8174C  8C 2A FC      		sty	ACIACMD
1447
 3957  F8174F  AC 28 FC      		ldy	ACIADR		; clear flag
1448
 3958  F81752  AC 29 FC      		ldy	ACIASR
1449
 3959
1450
 3960  F81755  8D 0D FC      	?z23:	sta	!CREMEON		; enable extended memory
1451
 3961  F81758  A8            		tay				; save flag
1452
 3962  F81759  AF 00 15 01   		lda	>PICRAM+256		; test ram for pic usb-host
1453
 3963  F8175D  AA            		tax
1454
 3964  F8175E  A9 55         		lda	#$55
1455
 3965  F81760  8F 00 15 01   		sta	>PICRAM+256
1456
 3966  F81764  CF 00 15 01   		cmp	>PICRAM+256
1457
 3967  F81768  D0 2D         		bne	?z24
1458
 3968  F8176A  A9 AA         		lda	#$AA
1459
 3969  F8176C  8F 00 15 01   		sta	>PICRAM+256
1460
 3970  F81770  CF 00 15 01   		cmp	>PICRAM+256
1461
 3971  F81774  D0 21         		bne	?z24
1462
 3972  F81776  A9 C3         		lda	#$C3
1463
 3973  F81778  8F 00 15 01   		sta	>PICRAM+256
1464
 3974  F8177C  CF 00 15 01   		cmp	>PICRAM+256
1465
 3975  F81780  D0 15         		bne	?z24
1466
 3976  F81782  A9 3C         		lda	#$3C
1467
 3977  F81784  8F 00 15 01   		sta	>PICRAM+256
1468
 3978  F81788  CF 00 15 01   		cmp	>PICRAM+256
1469
 3979  F8178C  D0 09         		bne	?z24
1470
 3980  F8178E  8A            		txa
1471
 3981  F8178F  8F 00 15 01   		sta	>PICRAM+256
1472
 3982  F81793  98            		tya
1473
 3983  F81794  09 40         		ora	#$40			; set bit<6>: ram usb host ok
1474
 3984  F81796  A8            		tay
1475
 3985  F81797  8C 4D FD      	?z24:	sty	.ABS.RTCDATA		; save flag
1476
 3986  F8179A  8D 0D FC      		sta	!CREMEON
1477
 3987  F8179D  98            		tya
1478
 3988  F8179E  F0 24         		beq	?20aa			; board not present
1479
 3989
1480
 3990                        		; setup VIA 2
1481
 3991  F817A0  A9 7F         		lda	#$7F
1482
 3992  F817A2  8D 1E FC      		sta	!VIA2+VIAIER		; disabilita interrupt
1483
 3993  F817A5  8D 1D FC      		sta	!VIA2+VIAIFR		; ed azzera tutti i flag
1484
 3994  F817A8  A9 07         		lda	#00000111B		; PA<2:0> out, PA<7:3> input
1485
 3995  F817AA  8D 13 FC      		sta	!VIA2+VIADDRA
1486
 3996  F817AD  A9 FF         		lda	#$FF
1487
 3997  F817AF  8D 12 FC      		sta	!VIA2+VIADDRB		; port B all out
1488
 3998  F817B2  A9 04         		lda	#00000100B		; set RTS = high
1489
  Tue Jul 17 11:00:15 2018                                                                                               Page   25
1490
 
1491
 
1492
 
1493
 
1494
 3999  F817B4  8D 11 FC      		sta	!VIA2+VIAPRA
1495
 4000  F817B7  9C 10 FC      		stz	!VIA2+VIAPRB		; clear port B
1496
 4001  F817BA
1497
 4002                        		; S.R. disabilitato, latch disabilitato, T1 free-run
1498
 4003                        		; T2 one shot - PB7 disabilitato - T1 & T2 count PHI2
1499
 4004  F817BA  A9 40         		lda	#$40
1500
 4005  F817BC  8D 1B FC      		sta	!VIA2+VIAACR
1501
 4006  F817BF
1502
 4007                        		; CA2, CA1, CB1 fronte negativo - CB2 positive edge
1503
 4008  F817BF  A9 62         		lda	#01100010B
1504
 4009  F817C1  8D 1C FC      		sta	!VIA2+VIAPCR
1505
 4010  F817C4
1506
 4011  F817C4  A2 43         	?20aa:	ldx	#$43			; X -> $43
1507
 4012  F817C6  8E 4C FD      		stx	RTCALE
1508
 4013
1509
 4014                        		; full test ram banco 0
1510
 4015  F817C9  8D 0F FC      		sta	CRHIMON			; abilita ram in $FE00 - $FFFF
1511
 4016  F817CC                		INDEX16
1512
 4017  F817CC  C2 10         		rep	#PXFLAG
1513
 4018                        		.LONGI	on
1514
 4019                        		.MNLIST
1515
 4020  F817CE  A0 00 00      		ldy	#0			; start banco 0
1516
 4021  F817D1  B9 00 00      	?20:	lda	!$0000,y
1517
 4022  F817D4  EB            		xba				; salva MEM in B
1518
 4023  F817D5  A9 55         		lda	#$55			; pattern test
1519
 4024  F817D7  99 00 00      		sta	!$0000,y
1520
 4025  F817DA  D9 00 00      		cmp	!$0000,y
1521
 4026  F817DD  D0 3F         		bne	?28			; bad ram
1522
 4027  F817DF  A9 AA         		lda	#$AA
1523
 4028  F817E1  99 00 00      		sta	!$0000,y
1524
 4029  F817E4  D9 00 00      		cmp	!$0000,y
1525
 4030  F817E7  D0 35         		bne	?28			; bad ram
1526
 4031  F817E9  EB            		xba				; ripristina mem
1527
 4032  F817EA  99 00 00      		sta	!$0000,y
1528
 4033  F817ED  C8            		iny
1529
 4034  F817EE  C0 00 FC      		cpy	#RAM0TOP
1530
 4035  F817F1  90 DE         		bcc	?20			; loop
1531
 4036  F817F3  A0 00 FE      		ldy	#RAM0SYS		; seconda parte
1532
 4037  F817F6  B9 00 00      	?24:	lda	!$0000,y
1533
 4038  F817F9  EB            		xba				; salva MEM in B
1534
 4039  F817FA  A9 55         		lda	#$55			; pattern test
1535
 4040  F817FC  99 00 00      		sta	!$0000,y
1536
 4041  F817FF  D9 00 00      		cmp	!$0000,y
1537
 4042  F81802  D0 1A         		bne	?28			; bad ram
1538
 4043  F81804  A9 AA         		lda	#$AA
1539
 4044  F81806  99 00 00      		sta	!$0000,y
1540
 4045  F81809  D9 00 00      		cmp	!$0000,y
1541
 4046  F8180C  D0 10         		bne	?28			; bad ram
1542
 4047  F8180E  EB            		xba				; ripristina mem
1543
 4048  F8180F  99 00 00      		sta	!$0000,y
1544
 4049  F81812  C8            		iny
1545
 4050  F81813  D0 E1         		bne	?24			; loop fino a fine banco
1546
 4051  F81815                		ACC16
1547
 4052  F81815  C2 20         		rep	#PMFLAG
1548
 4053                        		.LONGA	on
1549
 4054                        		.MNLIST
1550
 4055  F81817  88            		dey
1551
  Tue Jul 17 11:00:15 2018                                                                                               Page   26
1552
 
1553
 
1554
 
1555
 
1556
 4056  F81818  98            		tya				; last addr -> A/B
1557
 4057  F81819  A0 80 00      		ldy	#$80
1558
 4058  F8181C  D0 06         		bne	?30			; OK
1559
 4059  F8181E                	?28:	ACC16
1560
 4060  F8181E  C2 20         		rep	#PMFLAG
1561
 4061                        		.LONGA	on
1562
 4062                        		.MNLIST
1563
 4063  F81820  98            		tya				; bad addr -> A/B
1564
 4064  F81821  A0 00 00      		ldy	#$00
1565
 4065  F81824                	?30:	CPU08
1566
 4066  F81824  E2 30         		sep	#(PMFLAG.OR.PXFLAG)
1567
 4067                        		.LONGA	off
1568
 4068                        		.LONGI	off
1569
 4069                        		.MNLIST
1570
 4070  F81826  8C 4D FD      		sty	RTCDATA			; $43 -> flag bad ram
1571
 4071  F81829  E8            		inx
1572
 4072  F8182A  8E 4C FD      		stx	RTCALE
1573
 4073  F8182D  8D 4D FD      		sta	RTCDATA			; $44 -> bad addr L
1574
 4074  F81830  E8            		inx
1575
 4075  F81831  8E 4C FD      		stx	RTCALE
1576
 4076  F81834  EB            		xba
1577
 4077  F81835  8D 4D FD      		sta	RTCDATA			; $45 -> bad addr H
1578
 4078  F81838  E8            		inx				; X -> $46
1579
 4079  F81839  9B            		txy				; salva X in Y
1580
 4080  F8183A
1581
 4081                        		; test cold/warm reset
1582
 4082  F8183A  A2 6F         		ldx	#$6F
1583
 4083  F8183C  BD 00 F0      	?31:	lda	!intsr,x
1584
 4084  F8183F  DF 00 F0 F8   		cmp	>intsr,x
1585
 4085  F81843  D0 0D         		bne	?31a
1586
 4086  F81845  CA            		dex
1587
 4087  F81846  10 F4         		bpl	?31
1588
 4088  F81848  A2 43         		ldx	#$43
1589
 4089  F8184A  8E 4C FD      		stx	RTCALE
1590
 4090  F8184D  A9 40         		lda	#$40
1591
 4091  F8184F  0C 4D FD      		tsb	RTCDATA
1592
 4092  F81852                	?31a:
1593
 4093                        		; azzeramento ram banco 0 - solo per COLD RESET
1594
 4094  F81852                		INDEX16
1595
 4095  F81852  C2 10         		rep	#PXFLAG
1596
 4096                        		.LONGI	on
1597
 4097                        		.MNLIST
1598
 4098  F81854  AD 2A FD      		lda	PIA0+PIAPRB		; test bit /FSR (PB4)
1599
 4099  F81857  89 10         		bit	#00010000B
1600
 4100  F81859  D0 15         		bne	?40			; /FSR = 1 -> WARM RESET
1601
 4101  F8185B  A2 00 00      		ldx	#0
1602
 4102  F8185E  9E 00 00      	?32:	stz	!0000,x
1603
 4103  F81861  E8            		inx
1604
 4104  F81862  E0 00 FC      		cpx	#RAM0TOP
1605
 4105  F81865  90 F7         		bcc	?32			; loop
1606
 4106  F81867  A2 00 FE      		ldx	#RAM0SYS		; seconda parte
1607
 4107  F8186A  9E 00 00      	?34:	stz	!0000,x
1608
 4108  F8186D  E8            		inx
1609
 4109  F8186E  D0 FA         		bne	?34
1610
 4110  F81870
1611
 4111                        		; copia segmento di sistema da flash a RAM
1612
 4112                        	?40:	;ldx	#$0BFF
1613
  Tue Jul 17 11:00:15 2018                                                                                               Page   27
1614
 
1615
 
1616
 
1617
 
1618
 4113                        	?42:	;lda	>TORAM,x
1619
 4114                        		;sta	!TORAM,x
1620
 4115                        		;dex
1621
 4116                        		;bpl	?42
1622
 4117                        		;ldx	#$01FF			; copia da F8FE00 a FE00 - FFFF
1623
 4118                        	?44:	;lda	>IntSr,x
1624
 4119                        		;sta	!IntSr,x
1625
 4120                        		;dex
1626
 4121                        		;bpl	?44
1627
 4122
1628
 4123                        		; copia con mvn
1629
 4124  F81870                		CPU16
1630
 4125  F81870  C2 30         		rep	#(PMFLAG.OR.PXFLAG)
1631
 4126                        		.LONGA	on
1632
 4127                        		.LONGI	on
1633
 4128                        		.MNLIST
1634
 4129  F81872  5A            		phy
1635
 4130  F81873  A9 FF 0B      		lda	#$0BFF
1636
 4131  F81876  A2 00 F0      		ldx	#!TORAM
1637
 4132  F81879  9B            		txy
1638
 4133  F8187A  54 00 F8      		mvn	#^TORAM, #0
1639
 4134  F8187D  A9 FF 01      		lda	#$01FF
1640
 4135  F81880
1641
 4136                        		;;;;;;ldx	#!intsr
1642
 4137  F81880  A2 00 FE      		ldx	#$FE00
1643
 4138
1644
 4139  F81883  9B            		txy
1645
 4140  F81884  54 00 F8      		mvn	#^intsr, #0
1646
 4141  F81887  7A            		ply
1647
 4142  F81888
1648
 4143                        		; setup RTC DS1687
1649
 4144  F81888                		CPU08
1650
 4145  F81888  E2 30         		sep	#(PMFLAG.OR.PXFLAG)
1651
 4146                        		.LONGA	off
1652
 4147                        		.LONGI	off
1653
 4148                        		.MNLIST
1654
 4149  F8188A  A2 0A         		ldx	#RTCCTRLA	; test primo setup RTC
1655
 4150  F8188C  8E 4C FD      		stx	RTCALE
1656
 4151  F8188F  AD 4D FD      		lda	RTCDATA
1657
 4152  F81892  89 20         		bit	#00100000B	; test DV1
1658
 4153  F81894  F0 03         		beq	?45		; DV1 = 0 -> oscillatore RTC off
1659
 4154  F81896  4C 3E 19      		jmp	?46
1660
 4155  F81899  A2 0B         	?45:	ldx	#RTCCTRLB	; primo setup RTC
1661
 4156  F8189B  8E 4C FD      		stx	RTCALE
1662
 4157  F8189E  A9 0E         		lda	#00001110B	; SET = 0, no IRQ, SQW OUT, binary, formato 24H
1663
 4158  F818A0  8D 4D FD      		sta	RTCDATA
1664
 4159  F818A3  CA            		dex			; CTRL REG. A
1665
 4160  F818A4  8E 4C FD      		stx	RTCALE
1666
 4161  F818A7  A9 35         		lda	#00110101B	; oscillatore on, banco 1, sqw = 2048HZ
1667
 4162  F818A9  8D 4D FD      		sta	RTCDATA
1668
 4163  F818AC  A2 4B         		ldx	#RTCEXTCTRLB
1669
 4164  F818AE  8E 4C FD      		stx	RTCALE
1670
 4165  F818B1  A9 80         		lda	#10000000B	; abilita VBAUX
1671
 4166  F818B3  8D 4D FD      		sta	RTCDATA
1672
 4167  F818B6  CA            		dex			; EXT. CTRL. REG. 4A
1673
 4168  F818B7  8E 4C FD      		stx	RTCALE
1674
 4169  F818BA  9C 4D FD      		stz	RTCDATA		; abilita /PWR - azzera flag
1675
  Tue Jul 17 11:00:15 2018                                                                                               Page   28
1676
 
1677
 
1678
 
1679
 
1680
 4170  F818BD  A2 0B         		ldx	#RTCCTRLB	; stop update
1681
 4171  F818BF  8E 4C FD      		stx	RTCALE
1682
 4172  F818C2  A9 80         		lda	#$80
1683
 4173  F818C4  0C 4D FD      		tsb	RTCDATA
1684
 4174  F818C7  9C 4C FD      		stz	RTCALE		; registro secondi
1685
 4175  F818CA  9C 4D FD      		stz	RTCDATA		; SECS = 0
1686
 4176  F818CD  A2 02         		ldx	#RTCMIN
1687
 4177  F818CF  8E 4C FD      		stx	RTCALE
1688
 4178  F818D2  9C 4D FD      		stz	RTCDATA		; MIN = 0
1689
 4179  F818D5  A2 04         		ldx	#RTCHOURS
1690
 4180  F818D7  8E 4C FD      		stx	RTCALE
1691
 4181  F818DA  9C 4D FD      		stz	RTCDATA		; HOURS = 0
1692
 4182  F818DD  A2 06         		ldx	#RTCDAY
1693
 4183  F818DF  8E 4C FD      		stx	RTCALE
1694
 4184  F818E2  A9 01         		lda	#1		; DOMENICA
1695
 4185  F818E4  8D 4D FD      		sta	RTCDATA		; DAY = domenica
1696
 4186  F818E7  E8            		inx			; registro data
1697
 4187  F818E8  8E 4C FD      		stx	RTCALE
1698
 4188  F818EB  8D 4D FD      		sta	RTCDATA		; DATA = 1
1699
 4189  F818EE  E8            		inx			; registro mese
1700
 4190  F818EF  8E 4C FD      		stx	RTCALE
1701
 4191  F818F2  8D 4D FD      		sta	RTCDATA		; mese = 1
1702
 4192  F818F5  E8            		inx			; registro anno
1703
 4193  F818F6  8E 4C FD      		stx	RTCALE
1704
 4194  F818F9  A9 0C         		lda	#12		; anno = 2012
1705
 4195  F818FB  8D 4D FD      		sta	RTCDATA
1706
 4196  F818FE  A2 48         		ldx	#RTCCENTURY
1707
 4197  F81900  8E 4C FD      		stx	RTCALE
1708
 4198  F81903  A9 14         		lda	#20		; anno 2012
1709
 4199  F81905  8D 4D FD      		sta	RTCDATA		; setup -> ore 00.00.00 del 01/01/2012 - domenica
1710
 4200  F81908  A2 01         		ldx	#RTCALMSECS
1711
 4201  F8190A  8E 4C FD      		stx	RTCALE
1712
 4202  F8190D  A9 C0         		lda	#$C0
1713
 4203  F8190F  8D 4D FD      		sta	RTCDATA
1714
 4204  F81912  A2 03         		ldx	#RTCALMMIN
1715
 4205  F81914  8E 4C FD      		stx	RTCALE
1716
 4206  F81917  8D 4D FD      		sta	RTCDATA
1717
 4207  F8191A  A2 05         		ldx	#RTCALMHOURS
1718
 4208  F8191C  8E 4C FD      		stx	RTCALE
1719
 4209  F8191F  8D 4D FD      		sta	RTCDATA
1720
 4210  F81922  A2 49         		ldx	#RTCALMDATE
1721
 4211  F81924  8E 4C FD      		stx	RTCALE
1722
 4212  F81927  8D 4D FD      		sta	RTCDATA
1723
 4213  F8192A  A2 0B         		ldx	#RTCCTRLB
1724
 4214  F8192C  8E 4C FD      		stx	RTCALE
1725
 4215  F8192F  A9 80         		lda	#$80		; start RTC
1726
 4216  F81931  1C 4D FD      		trb	RTCDATA
1727
 4217  F81934  A2 0E         		ldx	#RTCRAM0E
1728
 4218  F81936  8E 4C FD      		stx	RTCALE
1729
 4219  F81939  A9 FF         		lda	#$FF
1730
 4220  F8193B  8D 4D FD      		sta	RTCDATA		; flag time non valido
1731
 4221  F8193E  A2 01         	?46:	ldx	#RTCALMSECS
1732
 4222  F81940  8E 4C FD      		stx	RTCALE		; set alarm at 02:00:00
1733
 4223  F81943  9C 4D FD      		stz	RTCDATA
1734
 4224  F81946  A2 03         		ldx	#RTCALMMIN
1735
 4225  F81948  8E 4C FD      		stx	RTCALE
1736
 4226  F8194B  9C 4D FD      		stz	RTCDATA
1737
  Tue Jul 17 11:00:15 2018                                                                                               Page   29
1738
 
1739
 
1740
 
1741
 
1742
 4227  F8194E  A2 05         		ldx	#RTCALMHOURS
1743
 4228  F81950  8E 4C FD      		stx	RTCALE
1744
 4229  F81953  A9 02         		lda	#2
1745
 4230  F81955  8D 4D FD      		sta	RTCDATA
1746
 4231  F81958  A2 0B         		ldx	#RTCCTRLB	; set RTC alarm for DST
1747
 4232  F8195A  8E 4C FD      		stx	RTCALE
1748
 4233  F8195D  A9 20         		lda	#$20
1749
 4234  F8195F  0C 4D FD      		tsb	RTCDATA
1750
 4235  F81962  A2 0A         		ldx	#RTCCTRLA
1751
 4236  F81964  8E 4C FD      		stx	RTCALE
1752
 4237  F81967  A9 10         		lda	#00010000B
1753
 4238  F81969  0C 4D FD      		tsb	RTCDATA		; banco 1
1754
 4239  F8196C  A2 0E         		ldx	#RTCRAM0E	; test time valido
1755
 4240  F8196E  8E 4C FD      		stx	RTCALE
1756
 4241  F81971  AD 4D FD      		lda	RTCDATA		; bit 7 = 1 -> time valido
1757
 4242  F81974  29 80         		and	#$80
1758
 4243  F81976  49 80         		eor	#$80
1759
 4244  F81978  A2 0D         		ldx	#RTCSTATUS2	; test batteria
1760
 4245  F8197A  8E 4C FD      		stx	RTCALE
1761
 4246  F8197D  2C 4D FD      		bit	RTCDATA
1762
 4247  F81980  10 02         		bpl	?48		; batteria scarica
1763
 4248  F81982  09 40         		ora	#RTC_VBAT	; batteria OK
1764
 4249  F81984  A2 4A         	?48:	ldx	#RTCEXTCTRLA	; test VBAUX
1765
 4250  F81986  8E 4C FD      		stx	RTCALE
1766
 4251  F81989  2C 4D FD      		bit	RTCDATA
1767
 4252  F8198C  10 02         		bpl	?49		; batteria scarica
1768
 4253  F8198E  09 20         		ora	#RTC_VBAUX	; VBAUX OK
1769
 4254  F81990  EB            	?49:	xba
1770
 4255  F81991  A2 4B         		ldx	#RTCEXTCTRLB
1771
 4256  F81993  8E 4C FD      		stx	RTCALE
1772
 4257  F81996  A9 40         		lda	#$40		; E32K va azzerato dopo power-up
1773
 4258  F81998  1C 4D FD      		trb	RTCDATA
1774
 4259
1775
 4260  F8199B  A9 01         		lda	#$01		; abilita KSE
1776
 4261  F8199D  0C 4D FD      		tsb	RTCDATA
1777
 4262  F819A0  A2 4B         		ldx	#RTCEXTCTRLB
1778
 4263  F819A2  8E 4C FD      		stx	RTCALE
1779
 4264  F819A5  A9 08         		lda	#$08		; PSR = 0 -- POWERON -> HIGH
1780
 4265  F819A7  1C 4D FD      		trb	RTCDATA
1781
 4266  F819AA  A2 4A         		ldx	#RTCEXTCTRLA
1782
 4267  F819AC  8E 4C FD      		stx	RTCALE
1783
 4268  F819AF  A9 08         		lda	#$08		; PAB = 0 -- POWERON
1784
 4269  F819B1  1C 4D FD      		trb	RTCDATA
1785
 4270  F819B4
1786
 4271  F819B4  A2 0A         		ldx	#RTCCTRLA
1787
 4272  F819B6  8E 4C FD      		stx	RTCALE
1788
 4273  F819B9  A9 10         		lda	#00010000B
1789
 4274  F819BB  1C 4D FD      		trb	RTCDATA		; banco 0
1790
 4275  F819BE  8C 4C FD      		sty	RTCALE		; $46
1791
 4276  F819C1  EB            		xba
1792
 4277  F819C2  8D 4D FD      		sta	RTCDATA
1793
 4278  F819C5  BB            		tyx			; $46
1794
 4279  F819C6  88            		dey
1795
 4280  F819C7  88            		dey
1796
 4281  F819C8  88            		dey			; $43 -> flag RAM
1797
 4282  F819C9  8C 4C FD      		sty	RTCALE
1798
 4283
1799
  Tue Jul 17 11:00:15 2018                                                                                               Page   30
1800
 
1801
 
1802
 
1803
 
1804
 4284                        		; errore fatale se ram fail in banco 0
1805
 4285  F819CC  AD 4D FD      		lda	RTCDATA			; flag ram
1806
 4286  F819CF  D0 4F         		bne	?55			; OK
1807
 4287  F819D1  A9 B0         		lda	#10110000B		; CTC counter 2 in modo 0 - 2 bytes
1808
 4288  F819D3  8D 4B FD      		sta	CTC0+CTCCTRL
1809
 4289  F819D6  A9 76         		lda	#01110110B		; CTC counter 1 in modo 3 - 2 bytes
1810
 4290  F819D8  8D 4B FD      		sta	CTC0+CTCCTRL
1811
 4291  F819DB  A9 90         		lda	#<400			; beep 200ms - pausa 200ms
1812
 4292  F819DD  8D 49 FD      		sta	CTC0+CTCCNT1
1813
 4293  F819E0  A9 01         		lda	#>400
1814
 4294  F819E2  8D 49 FD      		sta	CTC0+CTCCNT1
1815
 4295  F819E5  A9 40         		lda	#<1600			; 4 beep
1816
 4296  F819E7  8D 4A FD      		sta	CTC0+CTCCNT2
1817
 4297  F819EA  A9 06         		lda	#>1600
1818
 4298  F819EC  8D 4A FD      		sta	CTC0+CTCCNT2
1819
 4299  F819EF  A9 08         		lda	#$08			; beep ... beep...
1820
 4300  F819F1  0C 2B FD      		tsb	PIA0+PIACRB
1821
 4301  F819F4  1C 29 FD      		trb	PIA0+PIACRA
1822
 4302  F819F7  A2 3D         		ldx	#$3D
1823
 4303  F819F9  8E 4C FD      		stx	RTCALE
1824
 4304  F819FC  9C 4D FD      		stz	RTCDATA			; $3D -> flag ram x log
1825
 4305  F819FF  C8            		iny
1826
 4306  F81A00  8C 4C FD      		sty	RTCALE			; $3E-$3F -> bad address
1827
 4307  F81A03  AD 4D FD      		lda	RTCDATA
1828
 4308  F81A06  E8            		inx
1829
 4309  F81A07  8E 4C FD      		stx	RTCALE
1830
 4310  F81A0A  8D 4D FD      		sta	RTCDATA
1831
 4311  F81A0D  C8            		iny
1832
 4312  F81A0E  8C 4C FD      		sty	RTCALE			; $3E-$3F -> bad address
1833
 4313  F81A11  AD 4D FD      		lda	RTCDATA
1834
 4314  F81A14  E8            		inx
1835
 4315  F81A15  8E 4C FD      		stx	RTCALE
1836
 4316  F81A18  8D 4D FD      		sta	RTCDATA
1837
 4317  F81A1B  EA            	?52:	nop				; loop infinito
1838
 4318  F81A1C  EA            		nop				; ERRORE FATALE - BAD RAM BANCO 0
1839
 4319  F81A1D  4C 1B 1A      		jmp	?52			; 4 beep da 200ms/200ms
1840
 4320
1841
 4321                        		; copia flag da ram cmos a ram banco 0
1842
 4322  F81A20  A2 40         	?55:	ldx	#RTCURAM0
1843
 4323  F81A22  8E 4C FD      		stx	RTCALE			; $40
1844
 4324  F81A25  AD 4D FD      		lda	RTCDATA			; flag LCD
1845
 4325  F81A28  20 98 10      		jsr	LCDSetup		; setup LCD
1846
 4326  F81A2B  A2 41         		ldx	#RTCURAM0+1
1847
 4327  F81A2D  8E 4C FD      		stx	RTCALE			; $41
1848
 4328  F81A30  AD 4D FD      		lda	RTCDATA
1849
 4329  F81A33  85 65         		sta	sppost
1850
 4330  F81A35  E8            		inx				; $42
1851
 4331  F81A36  8E 4C FD      		stx	RTCALE
1852
 4332  F81A39  AD 4D FD      		lda	RTCDATA
1853
 4333  F81A3C  85 46         		sta	fdcctl
1854
 4334  F81A3E  E8            		inx
1855
 4335  F81A3F  8E 4C FD      		stx	RTCALE			; $43
1856
 4336  F81A42  AD 4D FD      		lda	RTCDATA
1857
 4337  F81A45  85 0C         		sta	Bnk0Flag
1858
 4338  F81A47  E8            		inx
1859
 4339  F81A48  E8            		inx
1860
 4340  F81A49  E8            		inx
1861
  Tue Jul 17 11:00:15 2018                                                                                               Page   31
1862
 
1863
 
1864
 
1865
 
1866
 4341  F81A4A  8E 4C FD      		stx	RTCALE			; $46
1867
 4342  F81A4D  AD 4D FD      		lda	RTCDATA
1868
 4343  F81A50  85 0D         		sta	RTCFlag
1869
 4344  F81A52  A2 4E         		ldx	#$4E			; $4E -> flag video board
1870
 4345  F81A54  8E 4C FD      		stx	RTCALE
1871
 4346  F81A57  AD 4D FD      		lda	!RTCDATA
1872
 4347  F81A5A  8D 6C 01      		sta	!DP01ADDR+VBBFlag
1873
 4348  F81A5D  E8            		inx
1874
 4349  F81A5E  8E 4C FD      		stx	RTCALE			; $4F -> flag video RAM
1875
 4350  F81A61  AD 4D FD      		lda	!RTCDATA
1876
 4351  F81A64  8D 6D 01      		sta	!DP01ADDR+VBBRam
1877
 4352
1878
 4353                        		;stz	!DP01ADDR+VBBFlag
1879
 4354                        		;stz	!DP01ADDR+VBBRam
1880
 4355  F81A67  A9 04         		lda	#$04
1881
 4356  F81A69  1C 76 FC      		trb	!PIAVBB+PIAPRB
1882
 4357  F81A6C
1883
 4358  F81A6C  A2 53         		ldx	#$53			; serial/usb board
1884
 4359  F81A6E  8E 4C FD      		stx	.ABS.RTCALE
1885
 4360  F81A71  AD 4D FD      		lda	!RTCDATA
1886
 4361  F81A74  85 BD         		sta	tstser
1887
 4362
1888
 4363                        		; seguito startup
1889
 4364  F81A76  20 07 A2      		jsr	VDCSetup		; inizializza charset VDC
1890
 4365  F81A79  A9 03         		lda	#TXTD_SCN
1891
 4366  F81A7B  85 50         		sta	DflTxtOut
1892
 4367  F81A7D  64 4F         		stz	DflTxtIn
1893
 4368  F81A7F  20 1F A4      		jsr	_ScnInit		; cancella schermo
1894
 4369  F81A82
1895
 4370                        		; get line /TXE status from UM245
1896
 4371  F81A82  24 BD         		bit	tstser
1897
 4372  F81A84  10 2F         		bpl	?z30
1898
 4373  F81A86  A2 00         		ldx	#0
1899
 4374  F81A88  AD 1F FC      	?z25:	lda	!VIA2+VIAPRANH	; check /TXE line
1900
 4375  F81A8B  CD 1F FC      		cmp	!VIA2+VIAPRANH
1901
 4376  F81A8E  D0 F8         		bne	?z25
1902
 4377  F81A90  A8            		tay
1903
 4378  F81A91  0A            		asl	a		; /TXE-> bit<7>
1904
 4379  F81A92  30 02         		bmi	?z26
1905
 4380  F81A94  A2 80         		ldx	#$80		; /TXE low: assume UM245 connected to usb host
1906
 4381  F81A96  8E 00 05      	?z26:	stx	.ABS.DP05ADDR+usbslv
1907
 4382
1908
 4383                        		; get line /CTS & /DSR from R65C51
1909
 4384  F81A99  9C 16 05      		stz	.ABS.DP05ADDR+splin3
1910
 4385  F81A9C  98            		tya
1911
 4386  F81A9D  89 08         		bit	#00001000B
1912
 4387  F81A9F  F0 0A         		beq	?z27		; /CTS low
1913
 4388  F81AA1  A9 80         		lda	#$80
1914
 4389  F81AA3  0C 16 05      		tsb	.ABS.DP05ADDR+splin3	; /CTS high
1915
 4390  F81AA6  A9 40         		lda	#$40
1916
 4391  F81AA8  1C 1C FC      		trb	!VIA2+VIAPCR	; set CB2 negative edge
1917
 4392  F81AAB
1918
 4393  F81AAB  AD 29 FC      	?z27:	lda	!ACIASR		; check /DSR line
1919
 4394  F81AAE  29 40         		and	#01000000B
1920
 4395  F81AB0  F0 03         		beq	?z30
1921
 4396  F81AB2  0C 16 05      		tsb	.ABS.DP05ADDR+splin3
1922
 4397
1923
  Tue Jul 17 11:00:15 2018                                                                                               Page   32
1924
 
1925
 
1926
 
1927
 
1928
 4398                        	?z30:	; check ch375/376 module (host usb0)
1929
 4399  F81AB5  A9 06         		lda	#CMD_CHECK_EXIST
1930
 4400  F81AB7  8D D1 FD      		sta	usb0cmd
1931
 4401  F81ABA  EA            		nop			; 2uS
1932
 4402  F81ABB  EA            		nop
1933
 4403  F81ABC  EA            		nop
1934
 4404  F81ABD  EA            		nop
1935
 4405  F81ABE  A9 65         		lda	#$65
1936
 4406  F81AC0  8D D0 FD      		sta	usb0dat
1937
 4407  F81AC3  EA            		nop			; 1uS
1938
 4408  F81AC4  EA            		nop
1939
 4409  F81AC5  AD D0 FD      		lda	usb0dat
1940
 4410  F81AC8  C9 9A         		cmp	#$9A
1941
 4411  F81ACA  D0 23         		bne	?z100		; not installed
1942
 4412  F81ACC  A9 80         		lda	#$80
1943
 4413  F81ACE  85 42         		sta     usb0ch          ; <7>: module on
1944
 4414  F81AD0  A9 01         		lda	#CMD_GET_IC_VER
1945
 4415  F81AD2  8D D1 FD      		sta	usb0cmd		; get type
1946
 4416  F81AD5  EA            		nop			; 2uS
1947
 4417  F81AD6  EA            		nop
1948
 4418  F81AD7  EA            		nop
1949
 4419  F81AD8  EA            		nop
1950
 4420  F81AD9  AD D0 FD      		lda	usb0dat
1951
 4421
1952
 4422                        		; returned value:
1953
 4423                        		; 	bit<7> = 1 & bit<6> = 0 if ch375
1954
 4424                        		; 	bit<7> = 0 & bit<6> = 1 if ch376
1955
 4425                        		;	bit<0:5> = firmware version
1956
 4426  F81ADC  AA            		tax
1957
 4427  F81ADD  29 3F         		and	#00111111B	; mask version
1958
 4428  F81ADF  05 42         		ora	usb0ch
1959
 4429  F81AE1  85 42         		sta	usb0ch		; <0..5> hold version
1960
 4430  F81AE3  8A            		txa
1961
 4431  F81AE4  29 C0         		and	#11000000B	; mask type
1962
 4432  F81AE6  C9 80         		cmp	#10000000B	; ch375?
1963
 4433  F81AE8  F0 02         		beq	?z31		; yes
1964
 4434  F81AEA  04 42         		tsb	usb0ch		; <6>: ch376
1965
 4435  F81AEC  20 F4 1F      	?z31:	jsr	initusb0	; init usb0 bus
1966
 4436  F81AEF
1967
 4437  F81AEF  A9 01         	?z100:	lda	#$01
1968
 4438  F81AF1  04 55         		tsb	BiosEnt		; avoid usb msg
1969
 4439  F81AF3  20 61 1C      		jsr	EnableInt		; abilita IRQ e NMI
1970
 4440  F81AF6  A9 01         		lda	#$01			; video VDC ON
1971
 4441  F81AF8  1C 1F FD      		trb	VIA1+VIAPRANH
1972
 4442  F81AFB  20 49 1C      		jsr	BootBeep
1973
 4443  F81AFE  20 30 1F      		jsr	BootMsg
1974
 4444  F81B01  20 92 1C      		jsr	CheckKbd		; test keyboard
1975
 4445  F81B04  A5 0D         		lda	RTCFlag
1976
 4446  F81B06  30 23         		bmi	?60
1977
 4447  F81B08                		SCNPRINT
1978
 4448  F81B08  02 01         		cop	$01
1979
 4449                        		.MNLIST
1980
 4450  F81B0A  45 52 52 4F 52 		.DB	'ERROR: invalid CMOS time & date'
1981
               3A 20 69 6E 76
1982
               61 6C 69 64 20
1983
               43 4D 4F 53 20
1984
               74 69 6D 65 20
1985
  Tue Jul 17 11:00:15 2018                                                                                               Page   33
1986
 
1987
 
1988
 
1989
 
1990
               26 20 64 61 74
1991
               65
1992
 4451  F81B29  0D 00         		.DB	$0D, $00
1993
 4452  F81B2B  89 60         	?60:	bit	#$60			; test batteria
1994
 4453  F81B2D  D0 2E         		bne	?62
1995
 4454  F81B2F                		SCNPRINT
1996
 4455  F81B2F  02 01         		cop	$01
1997
 4456                        		.MNLIST
1998
 4457  F81B31  45 52 52 4F 52 		.DB	'ERROR: invalid CMOS data - replace battery'
1999
               3A 20 69 6E 76
2000
               61 6C 69 64 20
2001
               43 4D 4F 53 20
2002
               64 61 74 61 20
2003
               2D 20 72 65 70
2004
               6C 61 63 65 20
2005
               62 61 74 74 65
2006
               72 79
2007
 4458  F81B5B  0D 00         		.DB	$0D, $00
2008
 4459  F81B5D  A9 04         	?62:	lda	#$04
2009
 4460  F81B5F  24 46         		bit	fdcctl
2010
 4461  F81B61  D0 20         		bne	?64
2011
 4462  F81B63                		SCNPRINT
2012
 4463  F81B63  02 01         		cop	$01
2013
 4464                        		.MNLIST
2014
 4465  F81B65  45 52 52 4F 52 		.DB	'ERROR: DMA not found or fail'
2015
               3A 20 44 4D 41
2016
               20 6E 6F 74 20
2017
               66 6F 75 6E 64
2018
               20 6F 72 20 66
2019
               61 69 6C
2020
 4466  F81B81  0D 00         		.DB	$0D, $00
2021
 4467  F81B83  A5 65         	?64:	lda	sppost
2022
 4468  F81B85  29 C0         		and	#$C0
2023
 4469  F81B87  C9 C0         		cmp	#$C0
2024
 4470  F81B89  F0 34         		beq	?66
2025
 4471  F81B8B                		SCNPRINT
2026
 4472  F81B8B  02 01         		cop	$01
2027
 4473                        		.MNLIST
2028
 4474  F81B8D  45 52 52 4F 52 		.DB	'ERROR: Serial controller 65C52 not found or fail'
2029
               3A 20 53 65 72
2030
               69 61 6C 20 63
2031
               6F 6E 74 72 6F
2032
               6C 6C 65 72 20
2033
               36 35 43 35 32
2034
               20 6E 6F 74 20
2035
               66 6F 75 6E 64
2036
               20 6F 72 20 66
2037
               61 69 6C
2038
 4475  F81BBD  0D 00         		.DB	$0D, $00
2039
 4476
2040
 4477                        	?66:	;bit	_LCDFlag
2041
 4478                        		;bmi	?68
2042
 4479                        		;SCNPRINT
2043
 4480                        		;.DB	'ERROR: LCD controller not found'
2044
 4481                        		;.DB	$0D, $00
2045
 4482
2046
 4483  F81BBF                	?68:
2047
  Tue Jul 17 11:00:15 2018                                                                                               Page   34
2048
 
2049
 
2050
 
2051
 
2052
 4484  F81BBF  A9 4E         		lda	#01001110B		; 38400 - 1 stop bit - no echo - ACR
2053
 4485  F81BC1  8D 51 FD      		sta	ACIA+ACIACR1		; imposta reg. controllo CR
2054
 4486  F81BC4  8D 55 FD      		sta	ACIA+ACIACR2
2055
 4487  F81BC7  A9 E4         		lda	#11100100B		; odd parity - 8 bit - RTS/DTR -> L
2056
 4488  F81BC9  8D 51 FD      		sta	ACIA+ACIAFR1		; imposta registro di formato FR
2057
 4489  F81BCC  8D 55 FD      		sta	ACIA+ACIAFR2
2058
 4490  F81BCF  85 58         		sta	<ACIAfr_1
2059
 4491  F81BD1  85 5C         		sta	<ACIAfr_2
2060
 4492  F81BD3  A9 C0         		lda	#$C0
2061
 4493  F81BD5  85 5E         		sta	<ACIAhsk_1
2062
 4494  F81BD7  85 62         		sta	<ACIAhsk_2
2063
 4495  F81BD9  A9 F9         		lda	#$F9
2064
 4496  F81BDB  8D 50 FD      		sta	ACIA+ACIAIER1
2065
 4497  F81BDE  58            		cli			; abilita INT
2066
 4498  F81BDF  A9 40         		lda	#$40
2067
 4499  F81BE1  04 55         		tsb	BiosEnt		; abilita <F8> al boot
2068
 4500  F81BE3  20 3D 1D      		jsr	QuickMT		; test veloce memoria
2069
 4501  F81BE6  A9 04         		lda	#$04
2070
 4502  F81BE8  24 46         		bit	fdcctl
2071
 4503  F81BEA  F0 03         		beq	?80		; salta test FDC
2072
 4504  F81BEC  20 B6 9F      	?70:	jsr	fdinit
2073
 4505  F81BEF  20 40 A0      	?80:	jsr	vdinit		; init ram disk
2074
 4506  F81BF2  20 34 8F      		jsr	initata		; scanning bus ATA
2075
 4507  F81BF5  20 47 B6      		jsr	showusb0
2076
 4508  F81BF8  A9 41         	?80a:	lda	#$41		; disabilita <F8>
2077
 4509  F81BFA  14 55         		trb	BiosEnt
2078
 4510  F81BFC                		SCNGETPOS
2079
 4511  F81BFC  02 18         		cop	$18
2080
 4512  F81BFE  02            		.DB	$02
2081
 4513                        		.MNLIST
2082
 4514  F81BFF  DA            		phx			; salva posizione corrente cursore
2083
 4515  F81C00  5A            		phy
2084
 4516  F81C01  AE B6 01      		ldx	!(DP01ADDR + SMAddrL)	; set posizione <F8>
2085
 4517  F81C04  AC B7 01      		ldy	!(DP01ADDR + SMAddrL +1)
2086
 4518  F81C07                		SCNSETPOS
2087
 4519  F81C07  02 18         		cop	$18
2088
 4520  F81C09  03            		.DB	$03
2089
 4521                        		.MNLIST
2090
 4522  F81C0A                		SCNPRINT	; cancella linea <F8>
2091
 4523  F81C0A  02 01         		cop	$01
2092
 4524                        		.MNLIST
2093
 4525  F81C0C  1B 71 00      		.DB	KB_ESC, 'q', $00
2094
 4526  F81C0F  7A            		ply			; restore posizione cursore
2095
 4527  F81C10  FA            		plx
2096
 4528  F81C11                		SCNSETPOS
2097
 4529  F81C11  02 18         		cop	$18
2098
 4530  F81C13  03            		.DB	$03
2099
 4531                        		.MNLIST
2100
 4532  F81C14
2101
 4533  F81C14  22 00 00 F9   		jsl	OSINIT
2102
 4534  F81C18  20 D1 B6      		jsr	shusb0fat
2103
 4535
2104
 4536                        		;;; FOR NOW: simply launch system monitor after boot & test
2105
 4537                        		.EXTERN dummydir
2106
 4538  F81C1B  22 5D 64 F9   		jsl	dummydir
2107
 4539  F81C1F  20 49 1C      		jsr	BootBeep
2108
 4540  F81C22
2109
  Tue Jul 17 11:00:15 2018                                                                                               Page   35
2110
 
2111
 
2112
 
2113
 
2114
 4541  F81C22  AD 00 FC      		lda	!CRBIT0		; test boot
2115
 4542  F81C25  D0 1E         		bne	?1000		; firmware from EMU
2116
 4543
2117
 4544  F81C27                		SCNPRINT
2118
 4545  F81C27  02 01         		cop	$01
2119
 4546                        		.MNLIST
2120
 4547  F81C29  46 69 72 6D 77 		.DB	'Firmware loaded from FLASH'
2121
               61 72 65 20 6C
2122
               6F 61 64 65 64
2123
               20 66 72 6F 6D
2124
               20 46 4C 41 53
2125
               48
2126
 4548                        		;.DB	'Firmware loaded from EEROM8U'
2127
 4549  F81C43  0D 00         		.DB	$0d, $00
2128
 4550
2129
 4551  F81C45                	?1000:
2130
 4552  F81C45  5C 03 00 FF   		jml	SYSMON
2131
 4553  F81C49
2132
 4554  F81C49                	BootBeep:
2133
 4555  F81C49  A9 B0         		lda	#10110000B	; CTC 2 in modo 0 - 2 bytes
2134
 4556  F81C4B  8D 4B FD      		sta	CTC0+CTCCTRL
2135
 4557  F81C4E  A9 2C         		lda	#<300
2136
 4558  F81C50  8D 4A FD      		sta	CTC0+CTCCNT2
2137
 4559  F81C53  A9 01         		lda	#>300
2138
 4560  F81C55  8D 4A FD      		sta	CTC0+CTCCNT2
2139
 4561  F81C58  A9 08         		lda	#$08
2140
 4562  F81C5A  1C 2B FD      		trb	PIA0+PIACRB
2141
 4563  F81C5D  1C 29 FD      		trb	PIA0+PIACRA
2142
 4564  F81C60  60            		rts
2143
 4565  F81C61
2144
 4566                        	; abilita IRQ e NMI
2145
 4567  F81C61                	EnableInt:
2146
 4568                        		.LONGA	off
2147
 4569                        		.LONGI	off
2148
 4570
2149
 4571  F81C61  A9 89         		lda	#VIA1INT		; abilita NMI CA2, CB2
2150
 4572  F81C63  8D 1E FD      		sta	VIA1+VIAIER
2151
 4573  F81C66  A9 C1         		lda	#VIA0INT		; abilita INT 2 CA2, CA1
2152
 4574  F81C68  8D 0E FD      		sta	VIA0+VIAIER
2153
 4575  F81C6B  A9 3E         		lda	#.LOW.VIA0T1CNT		; imposta VIA 0 T1
2154
 4576  F81C6D  8D 04 FD      		sta	VIA0+VIAT1CL
2155
 4577  F81C70  A9 9C         		lda	#.HIGH.VIA0T1CNT
2156
 4578  F81C72  8D 05 FD      		sta	VIA0+VIAT1CH
2157
 4579  F81C75
2158
 4580  F81C75  24 43         		bit	usb0st		; check usb0 status
2159
 4581  F81C77  10 05         		bpl	?ser		; not ready
2160
 4582  F81C79
2161
 4583  F81C79  A9 88         		lda	#CB2IFRB+$80
2162
 4584  F81C7B  8D CE FD      		sta	!VIA3+VIAIER	; enable CB2 interrupt
2163
 4585  F81C7E
2164
 4586  F81C7E  24 BD         	?ser:	bit	tstser
2165
 4587  F81C80  10 0F         		bpl	?end
2166
 4588
2167
 4589  F81C82  A9 5E         		lda	#.LOW.VIA2T1CNT		; imposta VIA 2 T1
2168
 4590  F81C84  8D 14 FC      		sta	!VIA2+VIAT1CL
2169
 4591  F81C87  A9 EA         		lda	#.HIGH.VIA2T1CNT
2170
 4592  F81C89  8D 15 FC      		sta	!VIA2+VIAT1CH
2171
  Tue Jul 17 11:00:15 2018                                                                                               Page   36
2172
 
2173
 
2174
 
2175
 
2176
 4593
2177
 4594  F81C8C  A9 DB         		lda	#$DB
2178
 4595  F81C8E  8D 1E FC      		sta	!VIA2+VIAIER		; enable CA2 interrupt
2179
 4596
2180
 4597  F81C91  60            	?end:	rts
2181
 4598
2182
 4599  F81C92                	CheckKbd:
2183
 4600  F81C92  9C 62 01      		stz	_KbdCnt
2184
 4601  F81C95  9C 65 01      		stz	_KbdToggle
2185
 4602  F81C98  9C 66 01      		stz	_KbdSt
2186
 4603  F81C9B  9C 67 01      		stz	_PS2Ctl
2187
 4604  F81C9E  9C 60 01      		stz	_KbdITail
2188
 4605  F81CA1  9C 61 01      		stz	_KbdIHead
2189
 4606  F81CA4  9C 63 01      		stz	_KbdShift
2190
 4607  F81CA7  9C 64 01      		stz	_KbdFlag
2191
 4608  F81CAA  A9 20         		lda	#$20			; imposta T2 su PB6 - 1ms
2192
 4609  F81CAC  0C 0B FD      		tsb	VIA0+VIAACR
2193
 4610  F81CAF  A9 D0         		lda	#(.LOW.KBDTMO)		; imposta timeout T2
2194
 4611  F81CB1  A2 07         		ldx	#(.HIGH.KBDTMO)
2195
 4612  F81CB3  8D 08 FD      		sta	VIA0+VIAT2CL
2196
 4613  F81CB6  8E 09 FD      		stx	VIA0+VIAT2CH
2197
 4614  F81CB9  2C 44 FD      	?10:	bit	KBSTATUS		; test controller PS/2
2198
 4615  F81CBC  50 27         		bvc	?12			; controller ready
2199
 4616  F81CBE  A9 20         		lda	#T2IFRB
2200
 4617  F81CC0  2C 0D FD      	 	bit	VIA0+VIAIFR		; test T2 flag
2201
 4618  F81CC3  F0 F4         	 	beq	?10			; attende timeout o controller ready
2202
 4619  F81CC5                	 	SCNPRINT
2203
 4620  F81CC5  02 01         		cop	$01
2204
 4621                        		.MNLIST
2205
 4622  F81CC7  45 52 52 4F 52 	 	.DB	'ERROR: controller PS/2 fail', $0D, $00
2206
               3A 20 63 6F 6E
2207
               74 72 6F 6C 6C
2208
               65 72 20 50 53
2209
               2F 32 20 66 61
2210
               69 6C 0D 00
2211
 4623  F81CE4  60            	 	rts
2212
 4624  F81CE5  AE 43 FD      	?12:	ldx	KBFR+3			; status dopo reset
2213
 4625  F81CE8  8E 66 01      		stx	_KbdSt
2214
 4626  F81CEB  D0 26         		bne	?14			; status kbd ok
2215
 4627  F81CED                		SCNPRINT
2216
 4628  F81CED  02 01         		cop	$01
2217
 4629                        		.MNLIST
2218
 4630  F81CEF  45 52 52 4F 52 		.DB	'ERROR: keyboard not found or fail', $0D, $00
2219
               3A 20 6B 65 79
2220
               62 6F 61 72 64
2221
               20 6E 6F 74 20
2222
               66 6F 75 6E 64
2223
               20 6F 72 20 66
2224
               61 69 6C 0D 00
2225
 4631  F81D12  60            		rts
2226
 4632  F81D13  A9 E1         	?14:	lda	#$E1			; comando set LOCK
2227
 4633  F81D15  8D 40 FD      		sta	KBFR
2228
 4634  F81D18  A9 40         		lda	#NUMLOCKB		; imposta toggle NUM LOCK
2229
 4635  F81D1A  8D 41 FD      		sta	KBFR+1
2230
 4636  F81D1D  8D 44 FD      		sta	KBDRQ			; richiesta servizio al controller
2231
 4637  F81D20  2C 44 FD      	?16:	bit	KBSTATUS		; test controller PS/2
2232
 4638  F81D23  30 FB         		bmi	?16			; attende risposta
2233
  Tue Jul 17 11:00:15 2018                                                                                               Page   37
2234
 
2235
 
2236
 
2237
 
2238
 4639  F81D25  AD 43 FD      		lda	KBFR+3
2239
 4640  F81D28  F0 05         		beq	?20			; errore
2240
 4641  F81D2A  A9 40         		lda	#NUMLOCKB		; imposta toggle NUM LOCK
2241
 4642  F81D2C  8D 65 01      		sta	!_KbdToggle
2242
 4643  F81D2F  A9 C1         	?20:	lda	#$C1			; comando start scanning
2243
 4644  F81D31  8D 40 FD      		sta	KBFR
2244
 4645  F81D34  8D 44 FD      		sta	KBDRQ			; richiesta servizio al controller
2245
 4646  F81D37  2C 44 FD      	?22:	bit	KBSTATUS
2246
 4647  F81D3A  30 FB         		bmi	?22			; attende risposta
2247
 4648  F81D3C  60            		rts
2248
 4649
2249
 4650                        	;----------------------------------------------------------
2250
 4651                        	; funzioni test memoria utilizzate in fase di boot
2251
 4652
2252
 4653                        	; test RAM veloce (in fase di boot)
2253
 4654  F81D3D                	QuickMT:
2254
 4655  F81D3D  0B            		phd
2255
 4656  F81D3E  F4 00 01      		pea	#DP01ADDR
2256
 4657  F81D41  2B            		pld
2257
 4658  F81D42  A9 01         		lda	#$01
2258
 4659  F81D44  85 BC         		sta	SMTmpK		; banco start = $01
2259
 4660  F81D46  A9 FF         		lda	#$FF
2260
 4661  F81D48  8D 4C 00      		sta	!MemTop		; imposta MemTop = $FFFF
2261
 4662  F81D4B  8D 4D 00      		sta	!MemTop+1
2262
 4663  F81D4E  9C 4E 00      		stz	!MemTop+2
2263
 4664  F81D51  8D 0A FC      		sta	CRXMEOFF	; disabilita X mem
2264
 4665  F81D54  8D 0C FC      		sta	CREMEOFF	; disabilita E mem
2265
 4666  F81D57  8D 08 FC      		sta	CRXFEOFF	; disabilita F mem
2266
 4667  F81D5A  2C 55 00      		bit	!BiosEnt	; test <F8> solo nel caso che non sia stato
2267
 4668  F81D5D  30 43         		bmi	?01		; forzato accesso al bios setup
2268
 4669  F81D5F                		SCNGETPOS
2269
 4670  F81D5F  02 18         		cop	$18
2270
 4671  F81D61  02            		.DB	$02
2271
 4672                        		.MNLIST
2272
 4673  F81D62  86 B6         		stx	SMAddrL		; salva pos. corrente
2273
 4674  F81D64  84 B7         		sty	SMAddrH
2274
 4675  F81D66                		SCNPRINT
2275
 4676  F81D66  02 01         		cop	$01
2276
 4677                        		.MNLIST
2277
 4678  F81D68  50 72 65 73 73 		.DB	'Press <F8> for enter BIOS setup...', $0D, $00
2278
               20 3C 46 38 3E
2279
               20 66 6F 72 20
2280
               65 6E 74 65 72
2281
               20 42 49 4F 53
2282
               20 73 65 74 75
2283
               70 2E 2E 2E 0D
2284
               00
2285
 4679  F81D8C  A9 20         		lda	#$20			; imposta T2 su PB6 - 1ms
2286
 4680  F81D8E  0C 0B FD      		tsb	VIA0+VIAACR
2287
 4681  F81D91  A9 F4         		lda	#(.LOW.F8TMO)		; imposta timeout T2
2288
 4682  F81D93  A2 01         		ldx	#(.HIGH.F8TMO)
2289
 4683  F81D95  8D 08 FD      		sta	VIA0+VIAT2CL
2290
 4684  F81D98  8E 09 FD      		stx	VIA0+VIAT2CH
2291
 4685  F81D9B  A9 20         		lda	#T2IFRB
2292
 4686  F81D9D  2C 0D FD      	?00:	bit	VIA0+VIAIFR		; test T2 flag
2293
 4687  F81DA0  F0 FB         	 	beq	?00			; attende timeout
2294
 4688
2295
  Tue Jul 17 11:00:15 2018                                                                                               Page   38
2296
 
2297
 
2298
 
2299
 
2300
 4689  F81DA2                	?01:	SCN_CR
2301
 4690  F81DA2                		SCNPRCHAR
2302
 4691                        		.MLIST
2303
 4692  F81DA2  02 07         		cop	$07
2304
 4693                        		.MNLIST
2305
 4694  F81DA4  0D            		.DB	$0D
2306
 4695                        		.MNLIST
2307
 4696  F81DA5  64 62         		stz	KbdCnt		; svuota buffer tastiera
2308
 4697  F81DA7                		SCNPRINT
2309
 4698  F81DA7  02 01         		cop	$01
2310
 4699                        		.MNLIST
2311
 4700  F81DA9  51 75 69 63 6B 		.DB	'Quick memory test: $', $00
2312
               20 6D 65 6D 6F
2313
               72 79 20 74 65
2314
               73 74 3A 20 24
2315
               00
2316
 4701  F81DBE                		SCNGETPOS
2317
 4702  F81DBE  02 18         		cop	$18
2318
 4703  F81DC0  02            		.DB	$02
2319
 4704                        		.MNLIST
2320
 4705  F81DC1  86 D6         		stx	SMAuxL
2321
 4706  F81DC3  84 D7         		sty	SMAuxH
2322
 4707  F81DC5  A6 D6         	?02:	ldx	SMAuxL		; loop banco
2323
 4708  F81DC7  A4 D7         		ldy	SMAuxH
2324
 4709  F81DC9                		SCNSETPOS
2325
 4710  F81DC9  02 18         		cop	$18
2326
 4711  F81DCB  03            		.DB	$03
2327
 4712                        		.MNLIST
2328
 4713  F81DCC  A5 BC         		lda	SMTmpK		; print banco
2329
 4714  F81DCE  20 E8 1E      		jsr	_ScnHex
2330
 4715  F81DD1                		SCNGETPOS	; pos. address
2331
 4716  F81DD1  02 18         		cop	$18
2332
 4717  F81DD3  02            		.DB	$02
2333
 4718                        		.MNLIST
2334
 4719  F81DD4  86 F6         		stx	SMXPos
2335
 4720  F81DD6  84 F7         		sty	SMYPos
2336
 4721  F81DD8  64 BA         		stz	SMTmpL		; azzera ptr
2337
 4722  F81DDA  64 BB         		stz	SMTmpH
2338
 4723  F81DDC  20 34 1E      	?03:	jsr	F8Tst		; loop test
2339
 4724  F81DDF  20 A9 1E      		jsr	MEMTst		; test mem
2340
 4725  F81DE2  D0 4B         		bne	?10		; bad ram
2341
 4726  F81DE4  A9 80         		lda	#$80
2342
 4727  F81DE6  85 BB         		sta	SMTmpH
2343
 4728  F81DE8  20 34 1E      		jsr	F8Tst
2344
 4729  F81DEB  20 A9 1E      		jsr	MEMTst
2345
 4730  F81DEE  D0 3F         		bne	?10
2346
 4731  F81DF0  A9 40         		lda	#$40
2347
 4732  F81DF2  85 BB         		sta	SMTmpH
2348
 4733  F81DF4  20 34 1E      		jsr	F8Tst
2349
 4734  F81DF7  20 A9 1E      		jsr	MEMTst
2350
 4735  F81DFA  A9 80         		lda	#$80
2351
 4736  F81DFC  85 BB         		sta	SMTmpH
2352
 4737  F81DFE  20 34 1E      		jsr	F8Tst
2353
 4738  F81E01  20 A9 1E      		jsr	MEMTst
2354
 4739  F81E04  A9 C0         		lda	#$C0
2355
 4740  F81E06  85 BB         		sta	SMTmpH
2356
 4741  F81E08  20 34 1E      		jsr	F8Tst
2357
  Tue Jul 17 11:00:15 2018                                                                                               Page   39
2358
 
2359
 
2360
 
2361
 
2362
 4742  F81E0B  20 A9 1E      		jsr	MEMTst
2363
 4743  F81E0E  A9 FF         		lda	#$FF
2364
 4744  F81E10  85 BA         		sta	SMTmpL
2365
 4745  F81E12  85 BB         		sta	SMTmpH
2366
 4746  F81E14  8D 4C 00      		sta	!MemTop		; imposta MemTop = $FFFF
2367
 4747  F81E17  8D 4D 00      		sta	!MemTop+1
2368
 4748  F81E1A  A5 BC         		lda	SMTmpK
2369
 4749  F81E1C  8D 4E 00      		sta	!MemTop+2
2370
 4750  F81E1F  20 34 1E      		jsr	F8Tst
2371
 4751  F81E22  20 A9 1E      		jsr	MEMTst
2372
 4752  F81E25  D0 08         		bne	?10
2373
 4753  F81E27  E6 BC         		inc	SMTmpK
2374
 4754  F81E29  A5 BC         		lda	SMTmpK
2375
 4755  F81E2B  C9 F8         		cmp	#$F8
2376
 4756  F81E2D  90 96         		bcc	?02		; loop
2377
 4757  F81E2F                	?10:	SCN_CR
2378
 4758  F81E2F                		SCNPRCHAR
2379
 4759                        		.MLIST
2380
 4760  F81E2F  02 07         		cop	$07
2381
 4761                        		.MNLIST
2382
 4762  F81E31  0D            		.DB	$0D
2383
 4763                        		.MNLIST
2384
 4764  F81E32  2B            		pld
2385
 4765  F81E33  60            		rts
2386
 4766  F81E34
2387
 4767  F81E34                	F8Tst:
2388
 4768  F81E34  2C 55 00      		bit	!BiosEnt
2389
 4769  F81E37  30 51         		bmi	?01		; salta test <F8> se gia' premuto
2390
 4770  F81E39  50 4F         		bvc	?01		; bit 6 - abilita test F8 solo al boot
2391
 4771  F81E3B  A5 62         		lda	KbdCnt		; char disponibili nel buffer tastiera ?
2392
 4772  F81E3D  F0 4B         		beq	?01		; no
2393
 4773  F81E3F  20 1B A2      		jsr	GetBufKey	; Y -> flag - A -> codice
2394
 4774  F81E42  AA            		tax			; X = codice
2395
 4775  F81E43  98            		tya			; A = flag
2396
 4776  F81E44  0A            		asl	a		; C = bit 7, N = bit 6
2397
 4777  F81E45  30 43         		bmi	?01		; ignora rilascio tasti
2398
 4778  F81E47  90 41         		bcc	?01		; ignora tasti ASCII
2399
 4779  F81E49  E0 A7         		cpx	#KB_F8		; test F8
2400
 4780  F81E4B  D0 3D         		bne	?01		; scarta
2401
 4781  F81E4D  A9 80         		lda	#$80
2402
 4782  F81E4F  0C 55 00      		tsb	!BiosEnt	; flag ingresso al setup bios
2403
 4783  F81E52  A6 B6         		ldx	SMAddrL		; set posizione
2404
 4784  F81E54  A4 B7         		ldy	SMAddrH
2405
 4785  F81E56                		SCNSETPOS
2406
 4786  F81E56  02 18         		cop	$18
2407
 4787  F81E58  03            		.DB	$03
2408
 4788                        		.MNLIST
2409
 4789  F81E59                		SCNPRINT
2410
 4790  F81E59  02 01         		cop	$01
2411
 4791                        		.MNLIST
2412
 4792  F81E5B  3C 46 38 3E 20 		.DB	'<F8> detected - entering BIOS setup after boot', $00
2413
               64 65 74 65 63
2414
               74 65 64 20 2D
2415
               20 65 6E 74 65
2416
               72 69 6E 67 20
2417
               42 49 4F 53 20
2418
               73 65 74 75 70
2419
  Tue Jul 17 11:00:15 2018                                                                                               Page   40
2420
 
2421
 
2422
 
2423
 
2424
               20 61 66 74 65
2425
               72 20 62 6F 6F
2426
               74 00
2427
 4793  F81E8A  60            	?01:	rts
2428
 4794
2429
 4795                        	; versione long
2430
 4796  F81E8B                	LF8Tst:
2431
 4797  F81E8B  48            		pha
2432
 4798  F81E8C  DA            		phx
2433
 4799  F81E8D  5A            		phy
2434
 4800  F81E8E  08            		php
2435
 4801  F81E8F  0B            		phd
2436
 4802  F81E90  F4 00 01      		pea	#DP01ADDR
2437
 4803  F81E93  2B            		pld
2438
 4804  F81E94                		CPU08
2439
 4805  F81E94  E2 30         		sep	#(PMFLAG.OR.PXFLAG)
2440
 4806                        		.LONGA	off
2441
 4807                        		.LONGI	off
2442
 4808                        		.MNLIST
2443
 4809  F81E96                		SCNGETPOS
2444
 4810  F81E96  02 18         		cop	$18
2445
 4811  F81E98  02            		.DB	$02
2446
 4812                        		.MNLIST
2447
 4813  F81E99  DA            		phx
2448
 4814  F81E9A  5A            		phy
2449
 4815  F81E9B  20 34 1E      		jsr	F8Tst
2450
 4816  F81E9E  7A            		ply
2451
 4817  F81E9F  FA            		plx
2452
 4818  F81EA0                		SCNSETPOS
2453
 4819  F81EA0  02 18         		cop	$18
2454
 4820  F81EA2  03            		.DB	$03
2455
 4821                        		.MNLIST
2456
 4822  F81EA3  2B            		pld
2457
 4823  F81EA4  28            		plp
2458
 4824  F81EA5  7A            		ply
2459
 4825  F81EA6  FA            		plx
2460
 4826  F81EA7  68            		pla
2461
 4827  F81EA8  60            		rts
2462
 4828
2463
 4829  F81EA9                	MEMTst:
2464
 4830  F81EA9  A7 BA         		lda	[SMTmpL]
2465
 4831  F81EAB  EB            		xba			; salva dato in B
2466
 4832  F81EAC  A9 55         		lda	#$55
2467
 4833  F81EAE  87 BA         		sta	[SMTmpL]
2468
 4834  F81EB0  C7 BA         		cmp	[SMTmpL]
2469
 4835  F81EB2  D0 06         		bne	?02
2470
 4836  F81EB4  A9 AA         		lda	#$AA
2471
 4837  F81EB6  87 BA         		sta	[SMTmpL]
2472
 4838  F81EB8  C7 BA         		cmp	[SMTmpL]
2473
 4839  F81EBA  08            	?02:	php			; salva Z
2474
 4840  F81EBB  EB            		xba			; ripristina dato
2475
 4841  F81EBC  87 BA         		sta	[SMTmpL]
2476
 4842  F81EBE  28            		plp
2477
 4843  F81EBF  D0 11         		bne	?04
2478
 4844  F81EC1  A6 F6         		ldx	SMXPos
2479
 4845  F81EC3  A4 F7         		ldy	SMYPos
2480
 4846  F81EC5                		SCNSETPOS	; set pos address
2481
  Tue Jul 17 11:00:15 2018                                                                                               Page   41
2482
 
2483
 
2484
 
2485
 
2486
 4847  F81EC5  02 18         		cop	$18
2487
 4848  F81EC7  03            		.DB	$03
2488
 4849                        		.MNLIST
2489
 4850  F81EC8  A5 BA         		lda	SMTmpL
2490
 4851  F81ECA  A6 BB         		ldx	SMTmpH
2491
 4852  F81ECC  20 E2 1E      		jsr	_Scn2Hex
2492
 4853  F81ECF  A9 00         		lda	#$00		; Z = 1
2493
 4854  F81ED1  60            		rts
2494
 4855  F81ED2  A6 D6         	?04:	ldx	SMAuxL		; set pos banco
2495
 4856  F81ED4  A4 D7         		ldy	SMAuxH
2496
 4857  F81ED6                		SCNSETPOS
2497
 4858  F81ED6  02 18         		cop	$18
2498
 4859  F81ED8  03            		.DB	$03
2499
 4860                        		.MNLIST
2500
 4861  F81ED9  AD 4E 00      		lda	!MemTop+2	; print banco
2501
 4862  F81EDC  20 E8 1E      		jsr	_ScnHex
2502
 4863  F81EDF  A9 01         		lda	#$01		; Z = 0
2503
 4864  F81EE1  60            		rts
2504
 4865
2505
 4866                        	; stampa a video word A(lo)-X(hi)
2506
 4867  F81EE2                	_Scn2Hex:
2507
 4868  F81EE2  48            		pha
2508
 4869  F81EE3  8A            		txa
2509
 4870  F81EE4  20 E8 1E      		jsr	_ScnHex
2510
 4871  F81EE7  68            		pla
2511
 4872
2512
 4873                        	; _ScnHex - stampa a video byte HEX
2513
 4874                        	; In	- A = byte
2514
 4875                        	; Out	- nessuno
2515
 4876  F81EE8                	_ScnHex:
2516
 4877  F81EE8  DA            		phx			; salva x
2517
 4878  F81EE9  20 F3 1E      		jsr	Byte2Hex	; X,A = HEX
2518
 4879  F81EEC                		TXTCHAROUT	; stampa hi digit
2519
 4880  F81EEC  02 06         		cop	$06
2520
 4881                        		.MNLIST
2521
 4882  F81EEE  8A            		txa
2522
 4883  F81EEF  FA            		plx			; ripristina x
2523
 4884  F81EF0                		TXTCHAROUT	; stampa low gigit
2524
 4885  F81EF0  02 06         		cop	$06
2525
 4886                        		.MNLIST
2526
 4887  F81EF2  60            		rts
2527
 4888
2528
 4889                        	; Byte2Hex - converte byte in HEX
2529
 4890                        	; In	- A = byte
2530
 4891                        	; Out:	- X = low digit
2531
 4892                        	;	  A = hi digit
2532
 4893  F81EF3                	Byte2Hex:
2533
 4894  F81EF3  48            		pha			; salva A
2534
 4895  F81EF4  20 FD 1E      		jsr	?01		; converte parte bassa
2535
 4896  F81EF7  AA            		tax			; x = low digit
2536
 4897  F81EF8  68            		pla
2537
 4898  F81EF9  4A            		lsr	a		; parte alta
2538
 4899  F81EFA  4A            		lsr	a
2539
 4900  F81EFB  4A            		lsr	a
2540
 4901  F81EFC  4A            		lsr	a
2541
 4902  F81EFD  29 0F         	?01:	and	#$0F		; maschera nibble
2542
 4903  F81EFF  C9 0A         		cmp	#10
2543
  Tue Jul 17 11:00:15 2018                                                                                               Page   42
2544
 
2545
 
2546
 
2547
 
2548
 4904  F81F01  90 02         		bcc	?02
2549
 4905  F81F03  69 06         		adc	#6
2550
 4906  F81F05  69 30         	?02:	adc	#'0'
2551
 4907  F81F07  60            		rts
2552
 4908
2553
 4909                        	;----------------------------------------------------------
2554
 4910
2555
 4911  F81F08
2556
 4912                        	;----------------------------------------------------------
2557
 4913
2558
 4914                        	; init CRTC - DOT 25.175MHz, CCLK = 3.146875MHz, FH (-) = 31.469KHz
2559
 4915                        	; FV (+) = 70Hz - 449 raster lines -- HD6445
2560
 4916  F81F08                	CRTCREG:
2561
 4917  F81F08  00 63 01 50 02 		.DB	$00, $63, $01, $50, $02, $5A, $03, $D4
2562
               5A 03 D4
2563
 4918  F81F10  04 1B 05 01 06 		.DB	$04, $1B, $05, $01, $06, $19, $07, $1B
2564
               19 07 1B
2565
 4919  F81F18  08 00 09 0F 0A 		.DB	$08, $00, $09, $0F, $0A, $20, $0B, $0F
2566
               20 0B 0F
2567
 4920  F81F20  0C 00 0D 00 0E 		.DB	$0C, $00, $0D, $00, $0E, $00, $0F, $00
2568
               00 0F 00
2569
 4921  F81F28  FF            		.DB	$FF
2570
 4922  F81F29  1E 00 1F 00 20 		.DB	$1E, $00, $1F, $00, $20, $00, $FF
2571
               00 FF
2572
 4923  F81F30
2573
 4924  F81F30                	BootMsg:
2574
 4925  F81F30                		SCNPRINT
2575
 4926  F81F30  02 01         		cop	$01
2576
 4927                        		.MNLIST
2577
 4928  F81F32  4D 61 63 68 69 		.DB	'Machine 65C816 (native mode) model B16/01 - '
2578
               6E 65 20 36 35
2579
               43 38 31 36 20
2580
               28 6E 61 74 69
2581
               76 65 20 6D 6F
2582
               64 65 29 20 6D
2583
               6F 64 65 6C 20
2584
               42 31 36 2F 30
2585
               31 20 2D 20
2586
 4929  F81F5E  28 63 29 20 32 		.DB	'(c) 2012, Dream SpA.', $0D, $00
2587
               30 31 32 2C 20
2588
               44 72 65 61 6D
2589
               20 53 70 41 2E
2590
               0D 00
2591
 4930  F81F74                		SCNPRINT
2592
 4931  F81F74  02 01         		cop	$01
2593
 4932                        		.MNLIST
2594
 4933  F81F76  42 49 4F 53 20 		.DB	'BIOS bootstrap B16 rev. 1.0 (2013/06/05) - VIDEO RGB ', $00
2595
               62 6F 6F 74 73
2596
               74 72 61 70 20
2597
               42 31 36 20 72
2598
               65 76 2E 20 31
2599
               2E 30 20 28 32
2600
               30 31 33 2F 30
2601
               36 2F 30 35 29
2602
               20 2D 20 56 49
2603
               44 45 4F 20 52
2604
               47 42 20 00
2605
  Tue Jul 17 11:00:15 2018                                                                                               Page   43
2606
 
2607
 
2608
 
2609
 
2610
 4934  F81FAC  2C 6D 01      		bit	!DP01ADDR+VBBRam
2611
 4935  F81FAF  10 2F         		bpl	?10
2612
 4936  F81FB1                		SCNPRINT
2613
 4937  F81FB1  02 01         		cop	$01
2614
 4938                        		.MNLIST
2615
 4939  F81FB3  56 47 41 20 63 		.DB	'VGA compatible ', $00
2616
               6F 6D 70 61 74
2617
               69 62 6C 65 20
2618
               00
2619
 4940  F81FC3  2C 6C 01      		bit	!DP01ADDR+VBBFlag
2620
 4941  F81FC6  70 0D         		bvs	?05
2621
 4942  F81FC8                		SCNPRINT
2622
 4943  F81FC8  02 01         		cop	$01
2623
 4944                        		.MNLIST
2624
 4945  F81FCA  52 36 35 34 35 		.DB	'R6545EAP', $00
2625
               45 41 50 00
2626
 4946  F81FD3  80 19         		bra	?20
2627
 4947  F81FD5                	?05:	SCNPRINT
2628
 4948  F81FD5  02 01         		cop	$01
2629
 4949                        		.MNLIST
2630
 4950  F81FD7  48 44 36 34 34 		.DB	'HD6445', $00
2631
               35 00
2632
 4951  F81FDE  80 0E         		bra	?20
2633
 4952  F81FE0                	?10:	SCNPRINT
2634
 4953  F81FE0  02 01         		cop	$01
2635
 4954                        		.MNLIST
2636
 4955  F81FE2  50 41 4C 20 4D 		.DB	'PAL MOS8563', $00
2637
               4F 53 38 35 36
2638
               33 00
2639
 4956  F81FEE                	?20:	SCNPRINT
2640
 4957  F81FEE  02 01         		cop	$01
2641
 4958                        		.MNLIST
2642
 4959  F81FF0  0D 0D 00      		.DB	$0D, $0D, $00
2643
 4960  F81FF3  60            		rts
2644
 4961  F81FF4
2645
 4962
2646
 4963                        	; ----- init usb 0 ------
2647
 4964  F81FF4                	initusb0:
2648
 4965  F81FF4  64 43         		stz	usb0st		; clear usb0 status
2649
 4966  F81FF6  A9 08         		lda	#CB2IFRB
2650
 4967  F81FF8  8D CD FD      		sta	!VIA3+VIAIFR
2651
 4968  F81FFB  A9 15         		lda	#CMD_SET_USB_MODE
2652
 4969  F81FFD  8D D1 FD      		sta	!usb0cmd
2653
 4970  F82000  EA            		nop
2654
 4971  F82001  EA            		nop
2655
 4972  F82002  EA            		nop
2656
 4973  F82003  EA            		nop
2657
 4974  F82004  A9 07         		lda	#SET_USB_RES	; reset usb0 bus
2658
 4975  F82006  8D D0 FD      		sta	!usb0dat
2659
 4976  F82009  20 33 20      		jsr	delay32us
2660
 4977  F8200C  AD D0 FD      		lda	!usb0dat
2661
 4978  F8200F  C9 51         		cmp	#CMD_RET_SUCCESS
2662
 4979  F82011  D0 1F         		bne	?end		; fail
2663
 4980  F82013  20 48 20      		jsr	delay10ms
2664
 4981  F82016  A9 15         		lda	#CMD_SET_USB_MODE
2665
 4982  F82018  8D D1 FD      		sta	!usb0cmd
2666
 4983  F8201B  EA            		nop
2667
  Tue Jul 17 11:00:15 2018                                                                                               Page   44
2668
 
2669
 
2670
 
2671
 
2672
 4984  F8201C  EA            		nop
2673
 4985  F8201D  EA            		nop
2674
 4986  F8201E  EA            		nop
2675
 4987  F8201F  A9 06         		lda	#SET_USB_HOST	; set usb0 bus mode
2676
 4988  F82021  8D D0 FD      		sta	!usb0dat
2677
 4989  F82024  20 33 20      		jsr	delay32us
2678
 4990  F82027  AD D0 FD      		lda	!usb0dat
2679
 4991  F8202A  C9 51         		cmp	#CMD_RET_SUCCESS
2680
 4992  F8202C  D0 04         		bne	?end		; fail
2681
 4993  F8202E  A9 80         		lda	#$80
2682
 4994  F82030  85 43         		sta	usb0st		; <7>: usb0 host mode ok
2683
 4995  F82032  60            	?end:	rts
2684
 4996
2685
 4997                        	; delay
2686
 4998
2687
 4999          000080        	T32US		.EQU	(32 * PHI2)
2688
 5000          009C40        	T10MS		.EQU	(10 * 1000 * PHI2)
2689
 5001
2690
 5002  F82033                	delay32us:
2691
 5003  F82033  A9 20         		lda	#$20		; T2 count PHI2 pulses
2692
 5004  F82035  1C 0B FD      		trb	VIA0+VIAACR
2693
 5005  F82038  A9 80         		lda	#T32US
2694
 5006  F8203A  8D 08 FD      		sta	!VIA0+VIAT2CL
2695
 5007  F8203D  9C 09 FD      		stz	!VIA0+VIAT2CH
2696
 5008  F82040  AD 0D FD      	?55:	lda	!VIA0+VIAIFR
2697
 5009  F82043  89 20         		bit	#T2IFRB
2698
 5010  F82045  F0 F9         		beq	?55
2699
 5011  F82047  60            		rts
2700
 5012
2701
 5013  F82048                	delay10ms:
2702
 5014  F82048  A9 20         		lda	#$20		; T2 count PHI2 pulses
2703
 5015  F8204A  1C 0B FD      		trb	VIA0+VIAACR
2704
 5016  F8204D  A9 40         		lda	#<T10MS
2705
 5017  F8204F  8D 08 FD      		sta	!VIA0+VIAT2CL
2706
 5018  F82052  A9 9C         		lda	#>T10MS
2707
 5019  F82054  8D 09 FD      		sta	!VIA0+VIAT2CH
2708
 5020  F82057  AD 0D FD      	?22:	lda	!VIA0+VIAIFR
2709
 5021  F8205A  89 20         		bit	#T2IFRB
2710
 5022  F8205C  F0 F9         		beq	?22
2711
 5023  F8205E  60            		rts
2712
 5024
2713
 5025  F8205F                	TEST12:
2714
 5026  F8205F  A0 00         		ldy	#0
2715
 5027  F82061  0B            		phd
2716
 5028  F82062  F4 00 60      		pea	#$6000
2717
 5029  F82065  2B            		pld
2718
 5030                        		; check EEROM emulator board
2719
 5031  F82066  8C 12 FC      	?00:	sty	.ABS.VIA2+VIADDRB
2720
 5032  F82069  CC 12 FC      		cpy	.ABS.VIA2+VIADDRB
2721
 5033  F8206C  D0 4E         		bne	?09		; fail -- goto old way
2722
 5034  F8206E  C8            		iny
2723
 5035  F8206F  D0 F5         		bne	?00
2724
 5036  F82071
2725
 5037                        		; ok, seem present
2726
 5038  F82071  AD 1F FC      		lda	!VIA2+VIAPRANH
2727
 5039  F82074  29 10         		and	#$10
2728
 5040  F82076  D0 44         		bne	?09		; BUSY -- goto old way
2729
  Tue Jul 17 11:00:15 2018                                                                                               Page   45
2730
 
2731
 
2732
 
2733
 
2734
 5041  F82078  88            		dey
2735
 5042  F82079  8C 12 FC      		sty	.ABS.VIA2+VIADDRB	; port B out
2736
 5043
2737
 5044                        		; transfer emulator data to $E0 bank
2738
 5045  F8207C  A9 E8         		lda	#$E8
2739
 5046  F8207E  85 02         		sta	<2
2740
 5047  F82080  64 00         		stz	<0
2741
 5048  F82082  64 01         		stz	<1
2742
 5049  F82084  9C 10 FC      		stz	!VIA2+VIAPRB
2743
 5050  F82087  8D 0D FC      		sta	!CREMEON
2744
 5051  F8208A                		INDEX16
2745
 5052  F8208A  C2 10         		rep	#PXFLAG
2746
 5053                        		.LONGI	on
2747
 5054                        		.MNLIST
2748
 5055  F8208C  A0 00 00      	?lp1:	ldy	#0
2749
 5056  F8208F  BB            		tyx
2750
 5057  F82090  BF 00 18 01   	?lp2:	lda	>EMURAM,x
2751
 5058  F82094  97 00         		sta	[0],y
2752
 5059  F82096  C8            		iny
2753
 5060  F82097  E8            		inx
2754
 5061  F82098  E0 00 08      		cpx	#$0800
2755
 5062  F8209B  90 F3         		bcc	?lp2
2756
 5063  F8209D                		ACC16CLC
2757
 5064  F8209D  C2 21         		rep	#(PMFLAG.OR.PCFLAG)
2758
 5065                        		.LONGA	on
2759
 5066                        		.MNLIST
2760
 5067  F8209F  8A            		txa
2761
 5068  F820A0  65 00         		adc	<0
2762
 5069  F820A2  85 00         		sta	<0
2763
 5070  F820A4                		ACC08
2764
 5071  F820A4  E2 20         		sep	#PMFLAG
2765
 5072                        		.LONGA	off
2766
 5073                        		.MNLIST
2767
 5074  F820A6  90 02         		bcc	?nxt
2768
 5075  F820A8  E6 02         		inc	<2
2769
 5076  F820AA  EE 10 FC      	?nxt:	inc	!VIA2+VIAPRB
2770
 5077  F820AD  D0 DD         		bne	?lp1
2771
 5078  F820AF                		CPU08
2772
 5079  F820AF  E2 30         		sep	#(PMFLAG.OR.PXFLAG)
2773
 5080                        		.LONGA	off
2774
 5081                        		.LONGI	off
2775
 5082                        		.MNLIST
2776
 5083  F820B1  8D 0C FC      		sta	!CREMEOFF
2777
 5084  F820B4  8D 08 FC      		sta	!CRXFEOFF	; disabilita flash F00000 - F7FFFF
2778
 5085  F820B7  2B            		pld
2779
 5086  F820B8  A9 FF         		lda	#$FF
2780
 5087  F820BA  00 00         		brk
2781
 5088
2782
 5089  F820BC  A9 55         	?09:	lda	#$55
2783
 5090  F820BE  2B            		pld
2784
 5091  F820BF  A9 55         		lda	#$55
2785
 5092  F820C1  00 00         		brk
2786
 5093
2787
 5094  F820C3                	shutdown:
2788
 5095                        		.PUBLIC shutdown
2789
 5096
2790
 5097  F820C3  58            		cli
2791
  Tue Jul 17 11:00:15 2018                                                                                               Page   46
2792
 
2793
 
2794
 
2795
 
2796
 5098  F820C4  20 E4 20      		jsr	asksdown
2797
 5099  F820C7  B0 16         		bcs	?100
2798
 5100  F820C9  AD 10 FD      	?51:	lda	VIA1+VIAPRB
2799
 5101  F820CC  CD 10 FD      		cmp	VIA1+VIAPRB
2800
 5102  F820CF  D0 F8         		bne	?51
2801
 5103  F820D1  29 10         		and	#$10
2802
 5104  F820D3  F0 F4         		beq	?51
2803
 5105
2804
 5106                        		; OFF command
2805
 5107  F820D5  A2 4A         		ldx	#RTCEXTCTRLA
2806
 5108  F820D7  8E 4C FD      		stx	RTCALE
2807
 5109  F820DA  A9 08         		lda	#$08		; POWERON -> HIGH
2808
 5110  F820DC  0C 4D FD      		tsb	RTCDATA
2809
 5111
2810
 5112  F820DF                	?100:	SCNPRINT
2811
 5113  F820DF  02 01         		cop	$01
2812
 5114                        		.MNLIST
2813
 5115  F820E1  0D 00         		.DB	13,0
2814
 5116  F820E3  6B            		rtl
2815
 5117
2816
 5118                        	; return CF=0 if YES, CF=1 if NO
2817
 5119  F820E4                	asksdown:
2818
 5120  F820E4                		SCNPRINT
2819
 5121  F820E4  02 01         		cop	$01
2820
 5122                        		.MNLIST
2821
 5123  F820E6  0D 53 68 75 74 		.DB	13, 'Shutdown machine. Continue <Y/N> ?',0
2822
               64 6F 77 6E 20
2823
               6D 61 63 68 69
2824
               6E 65 2E 20 43
2825
               6F 6E 74 69 6E
2826
               75 65 20 3C 59
2827
               2F 4E 3E 20 3F
2828
               00
2829
 5124  F8210A  20 1E 21      	?10:	jsr	getkey0
2830
 5125  F8210D  B0 FB         		bcs	?10		; control key
2831
 5126  F8210F  AA            		tax
2832
 5127  F82110  EB            		xba
2833
 5128  F82111  A8            		tay
2834
 5129  F82112  D0 F6         		bne	?10		; CTL, ALT, SHIFT
2835
 5130  F82114  E0 79         		cpx	#'y'
2836
 5131  F82116  18            		clc
2837
 5132  F82117  F0 04         		beq	?20
2838
 5133  F82119  E0 6E         		cpx	#'n'
2839
 5134  F8211B  D0 ED         		bne	?10
2840
 5135  F8211D  60            	?20:	rts
2841
 5136  F8211E
2842
 5137                        	; wait a pressed key
2843
 5138  F8211E                	getkey0:
2844
 5139  F8211E                	?02:	KBGETIN			; system call - get key
2845
 5140  F8211E  02 17         		cop	$17
2846
 5141                        		.MNLIST
2847
 5142  F82120  C9 00         		cmp	#0
2848
 5143  F82122  F0 FA         		beq	?02		; loop -- wait pressed key
2849
 5144  F82124  AA            		tax			; X=key code
2850
 5145  F82125  EB            		xba
2851
 5146  F82126  18            		clc
2852
 5147  F82127  A8            		tay			; Y=control key flag
2853
  Tue Jul 17 11:00:15 2018                                                                                               Page   47
2854
 
2855
 
2856
 
2857
 
2858
 5148  F82128  10 01         		bpl	?04
2859
 5149  F8212A  38            		sec			; flag control key
2860
 5150  F8212B  AF 64 01 00   	?04:	lda	>DP01ADDR+KbdFlag
2861
 5151  F8212F  EB            		xba			; B = flag ALT, CTL, SHIFT
2862
 5152  F82130  18            		clc
2863
 5153  F82131  8A            		txa			; key code
2864
 5154  F82132  60            		rts
2865
 
2866
 
2867
             Lines Assembled : 4990                  Errors : 0
2868
 
2869
 
2870