WebSVN – MB01 Project – Blame – /trunk/gal/20140501-MB01-TEST_DMA/PLD/#0168.LST

Rev	Author	Line No.	Line
1	-	1	OrCAD LOGIC COMPILER v2.01 N 12/09/94 (Source file .\PLD\#0168.PLD)
		2
		3	1 \|\| FILE: #0168.PLD
		4	2 \|\| PROJ: 20170501
		5	3 \|\| FD-02 FDC/ATA/DMA BOARD
		6	4 \|\|
		7	5 \|\| PART: G26CV12-#0168
		8	6 \|\|
		9	7 \|\| DEV : GAL26CV12
		10	8 \|\|
		11	9 \|\| DESC: ATA CONTROL
		12	10 \|\|
		13	11 \|
		14	12 \|GAL26CV12
		15	13 \|
		16	14 \|\| INPUT
		17	15 \| 1:A0, 2:A1, 3:A2, 4:A3, 5:PHI2, 6:IO, 8:RW, 9:PHI0, 10:DMA,
		18	16 \| 11:GEN, 12:MW0, 13:IOR, 14:IOW, 28:INT,
		19	17 \|\| OUTPUT
		20	18 \| 15:WRH, 16:WRL, 17:WRD, 18:RDH, 19:RDD, 20:WE, 22:GA, 23:RD,
		21	19 \| 24:RDL, 25:CS0, 26:CS1, 27:IRQ
		22	20 \|
		23	21 \| ACTIVE-LOW: CS0, CS1, WRH, WRL, WRD, RDH, RDL, RDD, RD, WE, GA
		24	22
		25	23 \|
		26	24 \|
		27	25 \| SIGNATURE: "0168 "
		28	26 \|
		29	27 \|\| --------------------------------------------------------
		30	28 \|\| common signals when dma disabled (DMA = 1 => cpu access)
		31	29 \|\|
		32	30 \| ATA = DMA & IO' \|\| ata0 => FDA0-FDAF ata1 => FDB0-FDBF
		33	31 \| S01 = ATA & A3' & A2' & A1' & A0 \|\| FDB1
		34	32 \| S02 = ATA & A3' & A2' & A1 \|\| FDB2-FDB3
		35	33 \| S04 = ATA & A3' & A2 \|\| FDB4-FDB7
		36	34 \| S08 = ATA & A3 & A2' & A1' & A0' \|\| FDB8
		37	35 \| S0A = ATA & A3 & A2' & A1 & A0' \|\| FDBA
		38	36 \| S0B = ATA & A3 & A2' & A1 & A0 \|\| FDBB
		39	37 \| S0E = ATA & A3 & A2 & A1 & A0' \|\| FDBE
		40	38 \| SATA = (S01 # S02 # S04 # S08 # S0E) \|\| valid ata registers
		41	39 \| SATAX = (S01 # S02 # S04 # S0E) \|\| valid ata registers (no data reg.)
		42	40
		43	41 \| CRD = SATA & RW & PHI2 \|\| cpu read ata
		44	42 \|\| CWR0 = SATA & RW' & PHI2 & MW0 \|\| cpu write ata (02)
		45	43
		46	44 \|\| NOTA: questo funziona
		47	45 \| CWR0 = SATAX & RW' & PHI2 & MW0 \|\| cpu write ata (02)
		48	46 \| CWR2 = S08 & RW' & PHI0 & PHI2 & MW0' \|\| cpu write ata (02)
		49	47
		50	48 \|\| PROVA:
		51	49 \| CWR0 = SATAX & RW' & PHI2 \|\| cpu write ata (02)
		52	50 \| CWR2 = S08 & RW' & PHI0 & PHI2 \|\| cpu write ata (02)
		53	51
		54	52 \| CWE = (CWR0 # CWR2) \|\| cpu write ata
		55	53
		56	54 \|\|
		57	55 \|\| signals when dma0 access ata
		58
		59
		60	58 \|\|
		61	59 \|\| output signals
		62	60 \|\| WRL = S0A & RW' & PHI0 \|\| cpu write low latch
		63	61 \|\| WRH = S0B & RW' & PHI0 \|\| cpu write high latch
		64	62 \| WRLA = S0A & RW' & PHI2 & MW0 \|\| cpu write low latch
		65	63 \| WRHA = S0B & RW' & PHI2 & MW0 \|\| cpu write high latch
		66	64 \| WRLB = S0A & RW' & PHI0 & MW0' \|\| cpu write low latch
		67	65 \| WRHB = S0B & RW' & PHI0 & MW0' \|\| cpu write high latch
		68	66 \| WRL = (WRLA # WRLB)
		69	67 \| WRH = (WRHA # WRHB)
		70	68 \| RDL = S0A & RW & PHI2 \|\| cpu read low latch
		71	69 \| RDH = S0B & RW & PHI2 \|\| cpu read high latch
		72	70 \| WRD = S08 & RW' & GEN \|\| cpu dummy write latch
		73	71 \| RDD = S08 & RW & PHI2 \|\| cpu dummy read latch
		74	72 \| RD = CRD # DRD \|\| cpu read ata port
		75	73 \| WE = CWE # DWR \|\| cpu write ata port
		76	74 \| GA = (S01 # S02 # S04 # S0E) \|\| enable internal data bus
		77	75 \| CS0 = (S01 # S02 # S04 # S08) & GEN \|\| enable ata port /CS0
		78	76 \|\| CS0 = ((S01 # S02 # S04) & GEN) # S08 \|\| enable ata port /CS0
		79	77
		80	78 \| CS1 = S0E & GEN \|\| enable ata port /CS1
		81	79 \| IRQ = INT' \|\| int. inversion
		82
		83
		84
		85
		86
		87
		88	I202 7/25/17 11:04 am (Tuesday)
		89
		90
		91	OrCAD DEVICE FITTER v2.01 12/09/94 (Source file .\PLD\#0168.PLA)
		92
		93
		94
		95	RESOLVED EXPRESSIONS (Reduction 0)
		96
		97
		98
		99
		100	105 A0' A1 A2' A3 IO' RW' PHI0 DMA MW0'
		101
		102	WRH 113 A0 A1 A2' A3 PHI2 IO' RW' DMA MW0
		103
		104
		105	RDL 29 A0' A1 A2' A3 PHI2 IO' RW DMA
		106
		107	RDH 86 A0 A1 A2' A3 PHI2 IO' RW DMA
		108
		109
		110
		111
		112
		113
		114	39 A0' A1 A2 A3 PHI2 IO' RW DMA
		115
		116	41 A1 A2' A3' PHI2 IO' RW DMA
		117
		118	43 DMA' IOR'
		119
		120	WE 62 A0' A1' A2' A3 PHI2 IO' RW' PHI0 DMA MW0'
		121	63 A0' A1' A2' A3 PHI2 IO' RW' PHI0 DMA
		122	64 A0' A1 A2 A3 PHI2 IO' RW' DMA MW0
		123	65 A0 A1' A2' A3' PHI2 IO' RW' DMA MW0
		124
		125	67 A0 A1' A2' A3' PHI2 IO' RW' DMA
		126	68 A1 A2' A3' PHI2 IO' RW' DMA MW0
		127	69 A1 A2' A3' PHI2 IO' RW' DMA
		128	70 A2 A3' PHI2 IO' RW' DMA MW0
		129	71 A2 A3' PHI2 IO' RW' DMA
		130	72 DMA' IOW'
		131
		132	GA 49 A0' A1 A2 A3 IO' DMA
		133	50 A0 A1' A2' A3' IO' DMA
		134	51 A1 A2' A3' IO' DMA
		135	52 A2 A3' IO' DMA
		136
		137	CS0 20 A0' A1' A2' A3 IO' DMA GEN
		138	21 A0 A1' A2' A3' IO' DMA GEN
		139	22 A1 A2' A3' IO' DMA GEN
		140	23 A2 A3' IO' DMA GEN
		141
		142	CS1 11 A0' A1 A2 A3 IO' DMA GEN
		143
		144	IRQ 2 INT'
		145
		146
		147
		148
		149	Rows
		150
		151
		152
		153
		154	2. A1 4 - - - High
		155	3. A2 8 - - - High
		156	4. A3 12 - - - High
		157	5. PHI2 16 - - - High
		158
		159	8. RW 24 - - - High
		160	9. PHI0 28 - - - High
		161	10. DMA 32 - - - High
		162	11. GEN 36 - - - High
		163	12. MW0 40 - - - High
		164	13. IOR 44 - - - High
		165	14. IOW 48 - - - High
		166	15. WRH 51 112 9 2 Low (Three-state)
		167	16. WRL 47 103 9 2 Low (Three-state)
		168	17. WRD 43 94 9 1 Low (Three-state)
		169	18. RDH 39 85 9 1 Low (Three-state)
		170	19. RDD 35 74 11 1 Low (Three-state)
		171	20. WE 31 61 13 11 Low (Three-state)
		172	22. GA 27 48 13 4 Low (Three-state)
		173	23. RD 23 37 11 6 Low (Three-state)
		174	24. RDL 19 28 9 1 Low (Three-state)
		175	25. CS0 15 19 9 4 Low (Three-state)
		176	26. CS1 11 10 9 1 Low (Three-state)
		177	27. IRQ 6 1 9 1 High (Three-state)
		178	28. INT 2 - - - High
		179	29. - - 0 1 0
		180	30. - - 121 1 0
		181	---- ----
		182	122 35 (29%)
		183
		184
		185	I200 No fatal errors found in source code (device phase).
		186	I201 No warnings.
		187
		188
		189
		190
		191	*
		192	QP28* QF6432* QV1024*
		193
		194
		195
		196	L0520 1111111111111111111111111111111111111111111111111111*
		197	L0572 1011011101110111111110111111111101110111111111111111*
		198	L0988 1111111111111111111111111111111111111111111111111111*
		199	L1040 1011101110110111111110111111111101110111111111111111*
		200	L1092 0111101110111011111110111111111101110111111111111111*
		201	L1144 1111011110111011111110111111111101110111111111111111*
		202	L1196 1111111101111011111110111111111101110111111111111111*
		203	L1456 1111111111111111111111111111111111111111111111111111*
		204	L1508 1011011110110111011110110111111101111111111111111111*
		205	L1924 1111111111111111111111111111111111111111111111111111*
		206	L1976 1011101110110111011110110111111101111111111111111111*
		207	L2028 1011011101110111011110110111111101111111111111111111*
		208	L2080 0111101110111011011110110111111101111111111111111111*
		209	L2132 1111011110111011011110110111111101111111111111111111*
		210	L2184 1111111101111011011110110111111101111111111111111111*
		211	L2236 1111111111111111111111111111111110111111111110111111*
		212	L2496 1111111111111111111111111111111111111111111111111111*
		213	L2548 1011011101110111111110111111111101111111111111111111*
		214	L2600 0111101110111011111110111111111101111111111111111111*
		215	L2652 1111011110111011111110111111111101111111111111111111*
		216	L2704 1111111101111011111110111111111101111111111111111111*
		217	L3172 1111111111111111111111111111111111111111111111111111*
		218	L3224 1011101110110111011110111011011101111111101111111111*
		219	L3276 1011101110110111011110111011011101111111111111111111*
		220	L3328 1011011101110111011110111011111101111111011111111111*
		221	L3380 0111101110111011011110111011111101111111011111111111*
		222	L3432 1011011101110111011110111011111101111111111111111111*
		223	L3484 0111101110111011011110111011111101111111111111111111*
		224	L3536 1111011110111011011110111011111101111111011111111111*
		225	L3588 1111011110111011011110111011111101111111111111111111*
		226	L3640 1111111101111011011110111011111101111111011111111111*
		227	L3692 1111111101111011011110111011111101111111111111111111*
		228	L3744 1111111111111111111111111111111110111111111111111011*
		229	L3848 1111111111111111111111111111111111111111111111111111*
		230	L3900 1011101110110111011110110111111101111111111111111111*
		231	L4420 1111111111111111111111111111111111111111111111111111*
		232	L4472 0111011110110111011110110111111101111111111111111111*
		233	L4888 1111111111111111111111111111111111111111111111111111*
		234	L4940 1011101110110111111110111011111101110111111111111111*
		235	L5356 1111111111111111111111111111111111111111111111111111*
		236	L5408 1011011110110111011110111011111101111111011111111111*
		237	L5460 1011011110110111111110111011011101111111101111111111*
		238	L5824 1111111111111111111111111111111111111111111111111111*
		239	L5876 0111011110110111011110111011111101111111011111111111*
		240	L5928 0111011110110111111110111011011101111111101111111111*
		241	L6344 1101010101010101010101010011000000110001001101100011*
		242	L6396 100000100000001000000010000000100000*
		243	C283E*
		244
		245	I202 7/25/17 11:04 am (Tuesday)
		246	I203 Memory usage 12K
		247	I204 Elapsed time 1 second
		248

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