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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0168.PLD |
| 2 | || PROJ: 20170501 |
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| 3 | || FD-02 FDC/ATA/DMA BOARD |
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| 4 | || |
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| 5 | || PART: G26CV12-#0168 |
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| 6 | || |
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| 7 | || DEV : GAL26CV12 |
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| 8 | || |
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| 9 | || DESC: ATA CONTROL |
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| 10 | || |
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| 11 | | |
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| 12 | |GAL26CV12 |
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| 13 | | |
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| 14 | || INPUT |
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| 15 | | 1:A0, 2:A1, 3:A2, 4:A3, 5:PHI2, 6:IO, 8:RW, 9:PHI0, 10:DMA, |
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| 16 | | 11:GEN, 12:MW0, 13:IOR, 14:IOW, 28:INT, |
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| 17 | || OUTPUT |
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| 18 | | 15:WRH, 16:WRL, 17:WRD, 18:RDH, 19:RDD, 20:WE, 22:GA, 23:RD, |
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| 19 | | 24:RDL, 25:CS0, 26:CS1, 27:IRQ |
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| 20 | | |
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| 21 | | ACTIVE-LOW: CS0, CS1, WRH, WRL, WRD, RDH, RDL, RDD, RD, WE, GA |
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| 22 | |||
| 23 | | |
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| 24 | | |
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| 25 | | SIGNATURE: "0168 " |
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| 26 | | |
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| 27 | || -------------------------------------------------------- |
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| 28 | || common signals when dma disabled (DMA = 1 => cpu access) |
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| 29 | || |
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| 30 | | ATA = DMA & IO' || ata0 => FDA0-FDAF ata1 => FDB0-FDBF |
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| 31 | | S01 = ATA & A3' & A2' & A1' & A0 || FDB1 |
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| 32 | | S02 = ATA & A3' & A2' & A1 || FDB2-FDB3 |
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| 33 | | S04 = ATA & A3' & A2 || FDB4-FDB7 |
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| 34 | | S08 = ATA & A3 & A2' & A1' & A0' || FDB8 |
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| 35 | | S0A = ATA & A3 & A2' & A1 & A0' || FDBA |
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| 36 | | S0B = ATA & A3 & A2' & A1 & A0 || FDBB |
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| 37 | | S0E = ATA & A3 & A2 & A1 & A0' || FDBE |
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| 38 | | SATA = (S01 # S02 # S04 # S08 # S0E) || valid ata registers |
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| 39 | | SATAX = (S01 # S02 # S04 # S0E) || valid ata registers (no data reg.) |
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| 40 | |||
| 41 | | CRD = SATA & RW & PHI2 || cpu read ata |
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| 42 | || CWR0 = SATA & RW' & PHI2 & MW0 || cpu write ata (02) |
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| 43 | | CWR0 = SATAX & RW' & PHI2 & MW0 || cpu write ata (02) |
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| 44 | | CWR2 = S08 & RW' & PHI0 & PHI2 & MW0' || cpu write ata (02) |
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| 45 | |||
| 46 | || CWR1 = SATA & RW' & PHI0 & MW0' || cpu write ata (00) |
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| 47 | || CWE = (CWR0 # CWR1) || cpu write ata |
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| 48 | | CWE = (CWR0 # CWR2) || cpu write ata |
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| 49 | |||
| 50 | || |
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| 51 | || signals when dma0 access ata |
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| 52 | | DRD = DMA' & IOR' || dma read ata port 0 |
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| 53 | | DWR = DMA' & IOW' || dma write ata port 0 |
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| 54 | || |
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| 55 | || output signals |
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| 56 | || WRL = S0A & RW' & PHI0 || cpu write low latch |
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| 57 | || WRH = S0B & RW' & PHI0 || cpu write high latch |
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| 58 | | WRLA = S0A & RW' & PHI2 & MW0 || cpu write low latch |
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| 59 | | WRHA = S0B & RW' & PHI2 & MW0 || cpu write high latch |
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| 60 | | WRLB = S0A & RW' & PHI0 & MW0' || cpu write low latch |
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| 61 | | WRHB = S0B & RW' & PHI0 & MW0' || cpu write high latch |
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| 62 | | WRL = (WRLA # WRLB) |
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| 63 | | WRH = (WRHA # WRHB) |
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| 64 | | RDL = S0A & RW & PHI2 || cpu read low latch |
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| 65 | | RDH = S0B & RW & PHI2 || cpu read high latch |
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| 66 | | WRD = S08 & RW' & GEN || cpu dummy write latch |
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| 67 | | RDD = S08 & RW & PHI2 || cpu dummy read latch |
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| 68 | | RD = CRD # DRD || cpu read ata port |
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| 69 | | WE = CWE # DWR || cpu write ata port |
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| 70 | | GA = (S01 # S02 # S04 # S0E) || enable internal data bus |
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| 71 | | CS0 = (S01 # S02 # S04 # S08) & GEN || enable ata port /CS0 |
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| 72 | || CS0 = ((S01 # S02 # S04) & GEN) # S08 || enable ata port /CS0 |
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| 73 | |||
| 74 | | CS1 = S0E & GEN || enable ata port /CS1 |
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| 75 | | IRQ = INT' || int. inversion |