Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | - | 1 | || FILE: #0167.PLD |
| 2 | || PROJ: 20170501 |
||
| 3 | || FD-02 FDC/ATA/DMA BOARD |
||
| 4 | || |
||
| 5 | || PART: G18V10-#0167 |
||
| 6 | || |
||
| 7 | || DEV : GAL18V10 |
||
| 8 | || |
||
| 9 | || DESC: DMA CONTROL |
||
| 10 | || |
||
| 11 | | |
||
| 12 | |GAL18V10 |
||
| 13 | | |
||
| 14 | || INPUT |
||
| 15 | | 1:CLK, 2:AEN0, 3:HRQ0, 4:RES, 5:DMA, 6:FDC, 7:HRQ1, 8:AEN1, 9:EOP1, |
||
| 16 | || OUTPUT |
||
| 17 | | 19:Q0, 18:HLD0, 17:OE0, 16:PRES, 15:TC, 14:MGE, 13:OE1, 12:HLD1, 11:Q1 |
||
| 18 | | |
||
| 19 | | ACTIVE-LOW: OE0, OE1 |
||
| 20 | | |
||
| 21 | | SIGNATURE: "0167 " |
||
| 22 | | |
||
| 23 | || -------------------------------------------------------- |
||
| 24 | || |
||
| 25 | | Q[1..0] = CLK // Q[1..0] + 1 || Q0 = CLK/2, Q1 = CLK/4 |
||
| 26 | | AEN0X = AEN0 & DMA' & FDC || dma0 enable |
||
| 27 | | AEN1X = AEN1 & DMA' & FDC' || dma1 enable |
||
| 28 | | OE0 = AEN0X || dma0 bus enable |
||
| 29 | | OE1 = AEN1X || dma1 bus enable |
||
| 30 | | HLD0 = HRQ0 & DMA' & FDC || dma0 hold bus |
||
| 31 | | HLD1 = HRQ1 & DMA' & FDC' || dma1 hold bus |
||
| 32 | | TC = EOP1' || terminal count for fdc |
||
| 33 | | PRES = RES' || reset positive pulse |
||
| 34 | | MGE = AEN0X # AEN1X || ram gate enable for cpu access |